KR102617290B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, which includes a first drive integrated circuit for driving a first pixel array, a second drive integrated circuit for driving a second pixel array, and power required to drive the first and second pixel arrays. and a power integrated circuit that generates power and supplies it to the first and second drive ICs. The driving start timing of the second pixel array is delayed from the driving start timing of the first pixel array by a predetermined start delay time.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device that generates the power required to drive a pixel array divided into a pixel array for the left eye and a pixel array for the right eye using a single power module integrated circuit (hereinafter referred to as “PMIC”). will be.

Virtual reality technology is being applied to defense, architecture, tourism, movies, multimedia, and gaming fields. Virtual reality refers to a specific environment or situation that feels similar to the real environment using stereoscopic imaging technology.

In order to maximize the immersion of virtual reality, virtual reality technology is being applied to personal immersion apparatus. Representative personal immersive devices include Head Mounted Display (HMD), Face Mounted Display (FMD), and Eye Glasses-type Display (EGD).

The performance of personal immersive devices is not improving as expected due to uncomfortable external design, three-dimensional effect of stereoscopic images, immersion, and fatigue. Recently, in order to implement virtual reality using a smart phone, there is a method of displaying a three-dimensional image on the display panel of the smart phone and attaching the smart phone to the HMD device worn by the user. Since the display device of a smartphone is not designed to optimize virtual reality, the method of displaying virtual reality images using a smartphone cannot implement high-quality virtual reality.

The display panel of the personal immersive device can be separated into a display panel for the left eye and a display panel for the right eye. In order to simultaneously drive two display panels in one personal immersive device, a PMIC that generates the power required to drive the display panels is required. A drive IC (Integrated Circuit) is connected to each of the two display panels.

To drive two display panels, one or two PMICs can be used. When using one PMIC, one PMIC with many output channels can be connected to two display panels. When two display panels are driven simultaneously with one PMIC output, the display panel load connected to one PMIC increases by more than two times, so it is necessary to increase the load transient characteristics of the PMIC. Because of this, one PMIC currently in use cannot drive two display panels at the same time, so a new PMIC design is needed.

When driving multiple display panels simultaneously with one PMIC, an in-rush peak occurs at the output of the PMIC in the case of a dynamic load. In-rush current causes damage to the drive IC or display panel and causes abnormal display on the display panel.

The present invention provides a display device that can drive multiple display panels with one PMIC without increasing the load variation characteristics of the PMIC.

A display device according to an embodiment of the present invention includes a first drive integrated circuit for driving a first display panel, a second drive integrated circuit for driving a second display panel, and power required to drive the first and second display panels. and a power integrated circuit that generates and supplies power to the first and second drive ICs.

The driving start timing of the second display panel is delayed from the driving start timing of the first display panel by a predetermined start delay time.

The present invention can improve three-dimensional effect and immersion in personal immersive devices and reduce user fatigue by optimizing the panel structure, resolution, response characteristics, and driving method of the display device.

In addition, the present invention controls the start timing of the display panels differently so that multiple display panels can be driven by one PMIC without increasing the load variation characteristics of the PMIC.

1 is an exploded perspective view showing a personal immersive device according to an embodiment of the present invention.
FIG. 2 is a diagram showing the first and second display panels in the display module shown in FIG. 1.
FIG. 3 is a diagram showing the distance between the first and second display panels shown in FIG. 2.
Figures 4 to 6 are diagrams showing response speed measurement results of the present invention.
FIG. 7 is a block diagram showing the configuration of the display panel shown in FIG. 2.
FIG. 8 is a diagram briefly showing a portion of the pixel array shown in FIG. 7.
9 is an equivalent circuit diagram showing an example of a pixel circuit.
FIG. 10 is a waveform diagram showing signals input to the pixel shown in FIG. 9.
Figure 11 is a waveform diagram showing a duty driving method of a pixel circuit according to an embodiment of the present invention.
Figure 12 is a diagram showing the BDI effect in the duty driving method of a pixel circuit according to an embodiment of the present invention.
Figure 13 is a diagram showing the principle of maintaining data in a pixel without additional data addressing within one frame period.
Figure 14 is a diagram showing a display device of a personal immersive device according to an embodiment of the present invention.
FIG. 15 is a diagram showing the drive IC shown in FIG. 14 in detail.
FIG. 16 is a diagram showing registers connected to the timing controller shown in FIG. 15.
Figure 17 is a diagram comparing PMIC load changes when display panels start to be driven simultaneously in a power on sequence and when two display panels start to be driven with a predetermined time difference.
Figure 18 is a diagram comparing PMIC load changes when the display panels start to be driven simultaneously while the data voltage and reference voltage are output from the drive IC after the power-on sequence and when the two display panels start to be driven with a predetermined time difference. am.
Figure 19 is a diagram showing the time difference in drive start timing between display panels.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

Referring to Figure 1, the personal immersive device of the present invention includes a lens module 12, a display module 13, a main board 14, a head gear 11, a side frame 15, and a front cover. (front cover) (16), etc.

The display module 13 includes a display panel driving circuit for driving each of the two display panels and displays the input image received from the main board 14. The display panels are divided into a first display panel visible to the user's left eye and a second display panel visible to the user's right eye. The display module displays image data input from the main board on display panels. The image data may be 2D/3D image data that implements a video image of virtual reality (VR) or augmented reality (AR). The display module 13 can display various information input from the main board in the form of text, symbols, etc.

The lens module 12 includes an ultra-wide-angle lens, that is, a pair of fisheye lenses, to expand the angle of view of the user's left and right eyes. The pair of fisheye lenses includes a left eye lens disposed in front of the first display panel and a right eye lens disposed in front of the second display panel.

The main board 14 includes a host system processor that executes virtual reality software and supplies left eye input images and right eye input images to the display module 13. The host system processor is connected to external input devices, various sensors, communication modules, display modules, etc. The host system processor controls various functions of the personal immersive device. The host system processor may be an application processor (AP). The interface module is connected to external devices through interfaces such as Universal serial bus (USB) and High definition multimedia interface (HDMI). Sensors include various sensors such as gyro sensors and acceleration sensors. The processor of the main board 14 corrects the left-eye and right-eye image data in response to the output signal of the sensor module and transmits the left-eye and right-eye image data of the input image received through the interface module to the display module 13. The host system processor can generate left-eye images and right-eye images that match the resolution of the display panel based on the depth information analysis results of the 2D image and transmit them to the display module 13.

The headgear 11 includes a back cover exposing the fisheye lenses and a band connected to the back cover. The back cover, side frame 15, and front cover 16 of the headgear 11 are assembled to secure an internal space where the components of the personal immersive device are placed and to protect the components. Components include a lens module 12, a display module 13, and a main board 14. The band connects to the back cover. Users wear the personal immersive device on their head with a band. When a user puts the personal immersive device on his or her head, he or she looks at different display panels with his or her left and right eyes through fisheye lenses.

The side frame (15) is fixed between the head gear (11) and the front cover (16) to secure the gap in the internal space where the lens module (12), display module (13), and main board (14) are placed. do. The front cover 16 is disposed on the front of the personal immersive device.

The personal immersive device of the present invention may be implemented with a head mounted display (HMD) structure as shown in FIG. 1, but is not limited to this. For example, the present invention may be designed as an Eye Glasses-type Display (EGD) structure.

FIG. 2 is a diagram showing the first and second display panels PNL1 and PNL2 in the display module 13 shown in FIG. 1 . FIG. 3 is a diagram showing the distance between the first and second display panels PNL1 and PNL2 shown in FIG. 2. Each of the first and second display panels (PNL1, PNL2) is implemented as an Organic Light Emitting Diode (“OLED”) display panel with fast response speed, excellent color reproduction characteristics, and wide viewing angle characteristics. do. In the case of EGD, the display panels PNL1 and PNL2 may be implemented as transparent OLED display panels.

Referring to Figures 2 and 3, the first and second display panels (PNL1 and PNL2) are manufactured separately and arranged separately on the display module 13. At least a portion of the display panel driving circuit may be disposed between the first and second display panels PNL1 and PNL2. In FIG. 2, DIC (Drive Integrated Circuit) is an IC chip in which the timing controller and data driver shown in FIG. 7 are integrated. GIP (Gate In Panel) is a circuit in which the gate driver and EM driver shown in FIG. 7 are integrated on the same substrate along with a pixel array.

The center of the pixel array of the first display panel (PNL1) and the center of the pixel array of the second display panel (PNL2) are substantially equal to the distance (Le) between the user's eyes. The distance Lp between the center of the pixel array of the first display panel PNL1 and the center of the pixel array of the second display panel PNL2 may be set to Le ± α. The user's interocular distance (Le) is the distance between the pupil of the left eye and the pupil of the right eye and is approximately 6.5 cm, and may vary slightly depending on race. α is a design margin that takes into account the display panel driving circuit portion disposed between the first display panel (PNL1) and the second display panel (PNL2), process deviation, etc., and may be set to 10% of Le.

The pixel array (AA) of each of the first and second display panels (PNL1, PNL2) has a landscape in which the length in the horizontal direction (x) is longer than the length in the vertical direction (y), considering the vertical viewing angle and the left and right viewing angle. It has an aspect ratio of type. In personal immersive devices, the effect of improving the viewing angle is greater when the left and right viewing angles are widened rather than the top and bottom viewing angles. In the present invention, in order to maximize the left and right viewing angles in a personal immersive device, each of the first and second display panels (PNL1 and PNL2) is manufactured as a landscape type OLED display panel.

The screen ratio of the landscape type has more pixels in the horizontal direction (x) than the number of pixels in the vertical direction (y), and the length in the horizontal direction (x) is longer than the length in the vertical direction (y). Meanwhile, in the portrait type screen ratio, the number of pixels in the vertical direction (y) is greater than the number of pixels in the horizontal direction (x), and the length in the vertical direction (y) is longer than the length in the horizontal direction (x). The present inventors compared and tested the three-dimensional effect, immersion, and fatigue felt by users by changing various display panels in a personal immersive device. According to the results of this experiment, it was confirmed that the three-dimensional effect felt by the user was greatly improved when the pixel arrays of the display panels (PNL1 and PNL2) were separated by the distance between the user's eyes, as shown in FIG. 3. When the pixel arrays of the display panels (PNL1, PNL2) are separated and the distance between the centers of the pixel arrays matches the user's left and right eyes, the viewing angle is wide and the three-dimensional effect is greatly improved. In the personal immersive device of the present invention, the pupil of the user's left eye coincides with the center of the first pixel array, and the pupil of the user's right eye coincides with the center of the second pixel array.

Compared to the portrait type screen ratio, the three-dimensional effect felt by the user is better in the landscape type screen ratio. The present invention can increase the three-dimensional effect by separately arranging a landscape-type left-eye display panel and a right-eye display panel in a personal immersive device.

The pixel arrays (AA) can be arranged 1:1 on separate substrates so that the first pixel array (AA) on which the left-eye image is displayed and the second pixel array (AA) on which the right-eye image is displayed are separated. there is. In this case, the first pixel array AA is disposed on the substrate of the first display panel PNL1, and the second pixel array is disposed on the substrate of the second display panel PNL2. In another embodiment, the first and second pixel arrays may be separated on one substrate. In this case, pixel arrays are separated on one display panel. Here, separating the pixel arrays means that the data line, gate line (or scan line), and pixels are separated. Although the first and second pixel arrays are separated, they can be driven by the same driving signal system, so they can share at least a portion of the display panel driving circuit.

When two pixel arrays (AA) are separated and arranged on one substrate, various effects in addition to the three-dimensional improvement effect can be provided. One of the conventional VR devices forms one pixel array on one substrate, and displays a left-eye image and a right-eye image on the pixel array, without separating the pixel array. Compared to this prior art, the present invention divides the display panels (PNL1, PNL2) into two to separate the pixel arrays (AA) or separates the two pixel arrays (AA) on one substrate to separate the pixels. Because the arrays (AA) are separated, there is a difference in whether or not the pixel array is classified. Due to this difference, the present invention allows more freedom in the arrangement design of the pixel arrays compared to the prior art, and provides three-dimensional effect by arranging each of the pixel arrays (AA) at an optimal viewing angle ratio of 1:1 between the left and right eyes of a person. can be maximized.

In terms of productivity, the display panel structure of the present invention has the effect of lowering the defect rate and increasing yield because the pixel array area reduction is reduced.

As the spacing between pixel arrays (AA) narrows, the screen size becomes smaller and the displayed image becomes narrower. If the gap between pixel arrays (AA) widens, the center position of the pixel arrays corresponding to both eyes of the user may move to the outskirts of the screen, resulting in a decrease in immersion and three-dimensional effect. The distance between a person's eyes is 65mm, and when the center point of the separated pixel arrays (AA) and the pupil of both eyes of the person exactly match, the user can perceive the three-dimensional image in the personal immersive device with the most stereoscopic effect.

If the gap between pixel arrays is too narrow or wide, the viewing angle can be compensated optically using a fisheye lens (LENS), or the left-eye image and right-eye image can be adjusted to match the distance between the user's eyes through image processing. However, this method does not apply to the viewing angle. This causes a decrease in display efficiency. In other words, when the pixel arrays are separated as in the present invention and the center of each pixel array is accurately placed 1:1 between the user's left and right pupil, the user can enjoy the most accurate three-dimensional image. In a personal immersive device, a fisheye lens (LENS) exists between the user's eyes and the display panel, and the distance between the user's eyes and the display panel is very short, on the order of several centimeters. When a user views an image reproduced on the display panels (PNL1, PNL2) through a fisheye lens, the user sees an image enlarged 4 to 5 times than the actual screen displayed on the display panels (PNL1, PNL2). In this close viewing and fisheye lens application environment, if the resolution of the display panel is low, the non-emissive area of the pixels is enlarged, causing a strong perception of the screen door effect, reducing the sense of immersion. In order to increase the sense of immersion in the personal immersive device, the pixel array of each of the first and second display panels (PNL1, PNL2) has a resolution of QHD (1440 It has a pixel aperture ratio. In 1440×1280, 1440 is the number of pixels (horizontal resolution) in the horizontal direction (x) in the pixel array (AD), and 1280 is the number of lines (vertical resolution) in the vertical direction (y). Considering the technology level of OLED display panels that can be mass-produced, it can have a pixel density of 500 ppi to 600 ppi and a pixel aperture ratio of 14% to 20%.

When displaying 3D video on a personal immersive device, screen drag or motion blur may be perceived as total latency increases. Screen drag or motion blur in 3D videos not only reduces video quality but also increases user fatigue. The total delay time is the sum of the system processing time required to process data from the main board 14 and transmit it to the display module 13 and the display time of the display module 13. am. The delay time of the display module 13 is the sum of the frame delay time in which the input image is delayed for one frame period and the response speed of the pixel.

The present invention reduces user fatigue when displaying 3D video on a personal immersive device by reducing the response speed of pixels and increasing the frame rate or refresh rate. To this end, the present invention manufactures the switch element and driving element of the pixel in each of the display panels (PNL1 and PNL2) with an n-type MOSFET (metal oxide semiconductor) to speed up the response speed of the pixel circuit to less than 2ms and the frame rate to 90Hz. Raising it above this speeds up the data update cycle. If the frame rate is 90Hz, one frame period, which is the data update cycle, is approximately 11.1ms. Accordingly, the present invention can reduce the delay time of the display module 13 in a personal immersive device to approximately 13 ms, thereby reducing the total delay time to 25 ms or less. In the data update cycle, data of the input image is addressed to pixels.

Figures 4 to 6 are diagrams showing response speed measurement results of the present invention. 4 to 6, the x-axis represents time (msec), and the y-axis represents the relative value of luminance measured with a luminance meter. FIG. 6 is an enlarged view of the rising section of measured luminance in FIG. 5. 5 and 6, 4T2C is the response speed of the pixel circuit including four n-type MOSFET transistors and two capacitors as shown in FIG. 9. 6T1C is the response speed of a pixel circuit (not shown) including six p-type MOSFET transistors and one capacitor.

There are two ways to measure response speed: B to W (Black to White) and G to G (Gray to Gray).

B to W measures the time it takes for a pixel to change from black to white. In the case of LCD, B to W measures the time it takes for the liquid crystal display to fully close from a fully open state, or the time from a closed state to fully open.

G to G (Gray to Gray) measures response speed between light gray close to white and dark gray close to black. Generally, G to G measures the time from 10% luminance to 90% luminance when white luminance is 100%.

The response speed measurement method of the present invention was measured using the G to G method. The response speed measurement method of the present invention displays a black image on the screen for a predetermined time (e.g., 500 msec), then displays a white image for a predetermined time, and then displays the black image again for a predetermined time and measures the luminance on the screen. The luminance measured with a luminance meter is created as a histogram, and the histogram (red at the bottom) with the highest frequency of black measured luminance is defined as black luminance (0%), and the histogram (red at the top) with the highest frequency of white measured luminance is defined as black luminance (0%). ) is defined as white luminance (100%). As the screen changes, the change from 10% of white luminance (100%) to 90% of white luminance (100%) is measured as Rising Time, and the change from 90% of white luminance (100%) to white luminance (100%) is measured as Rising Time. Measure the falling time that falls to 10% of %). The response speed of the present invention is measured as Response Time = Rising Time + Falling Time. Therefore, the response speed of the present invention is measured as the sum of the response time when the luminance increases from 10% to 90% of white luminance (100%) and the response time when the luminance decreases from 90% to 10%.

The present invention uses a display panel implementing a pixel array with a pixel circuit (4T2C) using n-type MOSFETs to achieve a response speed greater than 0 and less than 2 msec measured in the same manner as above.

As can be seen in Figures 5 and 6, a pixel circuit using an n-type MOSFET at a frame rate of 60 Hz quickly increases the brightness of the pixel to more than 90% of the target brightness within 2 ms. Therefore, the pixel circuit (4T2C) using n-type MOSFET has a response speed of less than 2 msec, which is much shorter than 1 frame period (about 16.67 ms). In comparison, the pixel circuit (6T1C) using a p-type MOSFET at a frame rate of 60 Hz can increase the luminance of the pixel to more than 90% of the target luminance after more than 2 frame periods (approximately 2 x 16.67 ms) have elapsed. Because its response speed is more than 2 frame period.

The present invention duty-drives each of the display panels (PNL1, PNL2) to control the duty ratio of pixels to 50% or less when displaying 3D video in a personal immersive device, thereby using the BDI (Black Data Insertion) effect to control the user's Fatigue can be further reduced. The duty ratio (%) of pixels is the ratio of the time they emit light in a given light emission time. For example, when the given light emission time is 1 frame period, pixels emitting light with a duty ratio of 50% or less means that they emit light for less than 1/2 of the 1 frame period. Duty driving of pixels uses the BDI effect to improve motion blur and reduce image retention time (low persistence), prevent afterimages and flicker, and reduce the amount of pixel current in low gray levels. By reducing this, it provides the effect of reducing user fatigue in 3D videos.

FIG. 7 is a block diagram showing the configuration of the display panel shown in FIG. 2. FIG. 8 is a diagram briefly showing a portion of the pixel array shown in FIG. 7. 9 is an equivalent circuit diagram showing an example of a pixel circuit. FIG. 10 is a waveform diagram showing signals input to the pixel shown in FIG. 9.

7 to 10, each of the display panels PNL1 and PNL2 according to an embodiment of the present invention has a pixel array AA that displays an input image, and data of the input image is written into the pixel array AA. A display panel driving circuit is provided to do this.

The display panel driving circuit includes a data driver 102, a gate driver 104, an EM driver 106, and a timing controller 110. Additionally, the display panel driving circuit includes a power circuit not shown. The power circuit generates power necessary to drive the data driver 102, the gate driver 104, the EM driver 106, the timing controller 110, and the display panels PNL1 and PNL2.

At least a portion of the display panel driving circuit may be disposed on the substrate surface between the first and second pixel arrays. At least a portion of the display panel driving circuits 102, 104, 106, and 110 may be shared by the first display panels PNL1 and PNL2. The display panel driving circuits 102, 104, 106, and 110 address data to the pixels 10 of the display panels PNL1 and PNL2 at a high frame rate of 90Hz or more and write data to the pixels. do.

In the pixel array AA, a plurality of data lines 11 and a plurality of gate lines 12a, 12b, and 12c intersect, and the pixels 10 are arranged in a matrix form. The pixel array (AA) includes a reference voltage line (hereinafter referred to as “REF line”) 16 commonly connected to the pixels 10, and a VDD line that supplies a high-potential driving voltage (VDDEL) to the pixels 10. Includes (not shown). A predetermined initialization voltage (Vini) may be supplied to the pixels 10 through the REF line 16.

The gate lines 12a, 12b, and 12c include a plurality of first scan lines 12a to which a first scan pulse SCAN1 is supplied and a plurality of second scan lines to which a second scan pulse SCAN2 is supplied. It includes (12b) and a plurality of EM signal lines (12c) to which an emission (EM) signal (EM) is supplied.

Each of the pixels 10 is divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels 10 may further include a white subpixel. Wires such as one data line 11, gate lines 12a, 12b, and 12c, REF line 16, and VDD line are connected to each pixel.

The 1 frame period is a scanning period in which data is addressed to the pixels and data of the input image is written to each pixel, and after the scanning period, the pixels emit light at a preset duty ratio according to an alternating current EM signal (EM). It is divided into duty driving periods. An alternating current EM signal (EM) is generated at a duty ratio of 50% or less during the duty driving period, causing the pixels to emit light at a duty ratio of 50% or less. Since the scanning period is only approximately one horizontal period, most of one frame period is the duty drive period. The pixels 10 charge a capacitor with data voltage during the scanning period. The pixels 10 repeatedly emit light (or turn on) and not emit light (or turn off) according to the alternating current EM signal (EM). Each of the pixels 10 repeatedly turns on and off within one frame period, emits light at a duty ratio of 50% or less, and repeats On/Off. The pixels 10 are turned off and then emit light using the voltage charged in the capacitor, so that they do not receive additional data voltage during the duty driving period after the scanning period and are driven at a duty ratio of 50% or less to display data with the same luminance during one frame period. .

The data driver 102 converts the data (DATA) of the input image received from the timing controller 110 into a gamma compensation voltage under the control of the timing controller 110 to generate a data voltage, and transmits the data voltage to the data lines ( 11) is output. The data driver 102 may output a predetermined reference voltage Vref to the data lines 11 during the initialization period ti in order to initialize the driving elements of the pixels 10.

The gate driver 104 supplies the first and second scan pulses SCAN1 and SCAN2 to the scan lines 12a and 12b under the control of the timing controller 110. The first and second scan pulses SCAN1 and SCAN2 are synchronized to the data voltage. The first scan pulse SCAN1 maintains the on level when the data voltage is supplied to the pixels and turns on the switch element T3 to select the pixels 10 to be charged with the data voltage. . The second scan pulse SCAN2 rises simultaneously with the first scan pulse SCAN1 and is polled before the first scan pulse SCAN1 to initialize the pixels 10 during the initialization period ti. The second scan pulse SCAN2 rises simultaneously with the first scan pulse SCAN1 in the pixels 10 and falls before the sampling period ts.

The gate driver 104 shifts the scan pulses SCAN1 and SCAN2 using a shift register to sequentially supply the pulses to the scan lines 12a and 12b. The shift register of the gate driver 104 may be formed directly on the substrate of the display panel 100 together with the pixel array AA through a GIP process.

The EM driver 106 is a duty driver that outputs an EM signal (EM) under the control of the timing controller 110 and supplies it to the EM signal lines 12c. The EM driver 106 sequentially supplies the EM signal EM to the EM signal lines 12c by shifting the EM signal EM using a shift register. The EM driver 106 repeatedly toggles the EM signal EM during the duty driving period under the control of the timing controller 110 to drive the pixels at a duty ratio of 50% or less. The shift register of the EM driver 106 may be formed directly on the substrate of the display panel 100 along with the pixel array through a GIP process.

The timing controller 110 receives digital video data (DATA) of the left-eye/right-eye input images received from the main board 14 and a timing signal synchronized therewith. The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (CLK), and a data enable signal (DE). The timing controller 110 provides a data timing control signal for controlling the operation timing of the data driver 102 based on the timing signal received from the main board 14 and the DCS (Display Command Set) register setting value, and a gate driver 104. ) generates a gate timing control signal for controlling the operation timing of the EM driver 106, and a duty timing control signal for controlling the operation timing of the EM driver 106. The timing controller 110 controls the duty ratio of the EM signal using a duty timing control signal.

Each of the pixels 10 includes an OLED, a plurality of thin film transistors (TFTs) (T1 to T4), and a storage capacitor (Cst), as shown in FIG. 9 . A capacitor (C) may be connected between the drain of the second TFT (T2) and the second node (B). In Figure 9, “Coled” represents the parasitic capacitance of OLED. TFTs are implemented as n-type MOSFETs. The pixels 10 sample the threshold voltage of the driving element during the scanning period, receive the data voltage of the input image, and emit light at a duty ratio of 50% or less during the duty driving period (tem). The scanning period includes an initialization period (ti) to initialize the pixels 10, a sampling period (ts) to sample the threshold voltage of the driving element (T1) in the pixels 10, and a data voltage of the input image to the pixels ( 10) It is divided into the programming period (tw) supplied.

The OLED emits light with a current amount adjusted by the first TFT (T1) according to the data voltage output from the data driver 102. The current path of the OLED is switched by the second TFT (T2). OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL) may be included, but is not limited thereto. The anode of the OLED is connected to the second node (B), and the cathode is connected to the VSS electrode to which a low-potential power supply voltage or base voltage (VSS) is applied. “Coled” is a parasitic capacitance formed between the anode and cathode of OLED.

The first TFT (T1) is a driving element that controls the current flowing through the OLED according to the gate-source voltage (Vgs). The first TFT (T1) includes a gate connected to the first node (A), a drain connected to the source of the second TFT (T2), and a source connected to the second node (B).

The second TFT (T2) is a switch element that switches the current flowing through the OLED in response to the EM signal (EM). The EM signal EM is generated at an on level during the sampling period and repeats the on level and off level during the duty driving period to be generated at a duty ratio of 50% or less. The drain of the second TFT (T2) is connected to the VDD line to which the high-potential driving voltage (VDDEL) is supplied. The source of the second TFT (T2) is connected to the drain of the first TFT (T1). The gate of the second TFT (T2) is connected to the EM signal line 12c and receives an EM signal. The EM signal (EM) is generated at an on level (or high logic level) within the sampling period (ts) to turn on the second TFT (T2), and the initialization period (ti) and the programming period ( tw), it is inverted to the off level (or low logic level) to turn off the second TFT (T2). Additionally, the EM signal EM repeats the on level and off level according to the PWM duty ratio during the duty driving period tem and is generated at a duty ratio of 50% or less. The OLED emits light with a duty ratio of 50% or less due to the second TFT (T2) switching according to the EM signal (EM).

The third TFT (T3) is a switch element that supplies the data voltage (Vdata) to the first node (A) in response to the first scan pulse (SCAN1). The third TFT (T3) includes a gate connected to the first scan line (12a), a drain connected to the data line (11), and a source connected to the first node (A). The first scan pulse SCAN1 is supplied to the pixels 10 through the first scan line 12a. The first scan signal SCAN1 is generated at an on level for approximately one horizontal period (1H) to turn on the third TFT (T3), and is inverted to an off level during the duty driving period (tem) to turn the third TFT (T3). ) turns off.

The fourth TFT (T4) is a switch element that supplies the reference voltage (Vref) to the second node (B) in response to the second scan pulse (SCAN2). The fourth TFT (T4) includes a gate connected to the second scan line 12b, a drain connected to the REF line 16, and a source connected to the second node (B). The second scan pulse SCAN2 is supplied to the pixels 10 through the second scan line 12b. The second scan signal SCAN2 is generated at an on level within the initialization period ti to turn on the fourth TFT (T4), and remains at an off level for the remaining period to turn the fourth TFT (T4) into an off state. Control.

The storage capacitor (Cst) is connected between the first node (A) and the second node (B) and stores the difference voltage between the two ends to maintain the gate-source voltage (Vgs) of the TFT (T1). The storage capacitor (Cst) samples the threshold voltage (Vth) of the first TFT (T1), which is a driving element, in a source-follower method. A capacitor (C) is connected between the VDD line and the second node (B). When the potential of the first node (A) changes according to the data voltage (Vdata) during the programming period (tw), the capacitors (Cst, C) distribute the change as a voltage and reflect it in the voltage of the second node (B). do.

The scanning period of the pixel 10 is divided into an initialization period (ti), a sampling period (ts), and a programming period (tw). The scanning period is set to approximately 1 horizontal period (1H) to write data to pixels arranged in 1 horizontal line of the pixel array. During the scanning period, the threshold voltage of the first TFT (T1), which is the driving element of the pixel 10, is sampled and the data voltage is compensated by the threshold voltage. Therefore, during one horizontal period (1H), the data DATA of the input image is compensated by the threshold voltage of the driving element and written into the pixel 10.

When the initialization period (ti) starts, the first and second scan pulses (SCAN1, SCAN2) rise to the on level. At the same time, the EM signal EM is polled and changes to the off level. During the initialization period (ti), the second TFT (T2) is turned off to block the current path of the OLED. The third and fourth TFTs T3 and T4 are turned on during the initialization period ti. During the initialization period ti, a predetermined reference voltage Vref is supplied to the data line 11. During the initialization period (ti), the voltage of the first node (A) is initialized to the reference voltage (Vref), and the voltage of the second node (B) is initialized to a predetermined initialization voltage (Vini). After the initialization period (t1), the second scan pulse (SCAN2) changes to the off level to turn off the fourth TFT (T4). The on level is the gate voltage level of the TFT at which the switch elements (T2 to T4) of the pixel turn on. The off level is a gate voltage level that turns off the switch elements (T2 to T4) of the pixel.

During the sampling period ts, the first scan pulse SCAN1 maintains the on level, and the second scan pulse SCAN2 maintains the off level. The EM signal (EM) rises to the on level at the beginning of the sampling period (ts). During the sampling period ts, the second and third TFTs T2 and T3 are turned on. During the sampling period ts, the second TFT T2 is turned on in response to the on-level EM signal EM. During the sampling period (ts), the third TFT (T3) is maintained in an on state by the first scan signal (SCAN1) at the on level. During the sampling period ts, a reference voltage Vref is supplied to the data line 11. During the sampling period (ts), the voltage of the first node (A) is maintained at the reference voltage (Vref), while the voltage of the second node (B) increases by the drain-source current (Ids). According to this source-follower method, the gate-source voltage (Vgs) of the first TFT (T1) is sampled as the threshold voltage (Vth) of the first TFT (T1), and the sampled threshold voltage (Vth) ) is stored in the storage capacitor (Cst). During the sampling period (ts), the voltage of the first node (A) is the reference voltage (Vref), and the voltage of the second node (B) is Vref-Vth.

During the programming period (tw), the third TFT (T3) remains on according to the first scan signal (SCAN1) at the on level, and the remaining TFTs (T1, T2, and T4) are turned off. The data voltage (Vdata) of the input image is supplied to the data line 11 during the programming period (tw). The data voltage (Vdata) is applied to the first node (A), and the voltage distribution result between the capacitors (Cst, C) for the potential change (Vdata-Vref) of the first node (A) is applied to the second node (B) ) is reflected in the voltage of the gate-source voltage (Vgs) of the first TFT (T1) is programmed. During the programming period (tw), the voltage of the first node (A) is the data voltage (Vdata), and the voltage of the second node (B) is the capacitor (Cst) at “Vref-Vth” set through the sampling period (ts). The voltage distribution result between ,C) (C'*(Vdata-Vref)) is added to become "Vref-Vth+C'*(Vdata-Vref)". Ultimately, the voltage (Vgs) between the gate and source of the first TFT (T1) is programmed as “Vdata-Vref+Vth-C'*(Vdata-Vref)” through the programming period (tw). Here, C' is Cst/(Cst+C).

When the duty driving period tem begins, the EM signal EM rises and changes back to the on level, while the first scan pulse SCAN1 polls and changes to the off level. During the duty driving period (tem), the second TFT (T2) remains on to form a current path for the OLED. The first TFT (T1) adjusts the amount of current flowing through the OLED according to the data voltage during the duty driving period (tem).

The duty driving period (tem) continues from the programming period (tw) until the initialization period (ti) of the next frame. The present invention causes the pixels 10 to emit light at a duty ratio of 50% or less by switching the EM signal (EM) rather than causing the pixels to emit light continuously during this duty driving period (tem). When the EM signal (EM) is generated at the on level, the second TFT (T2) is turned on to form a current path of the OLED. During the duty driving period (tem), a current (Ioled) adjusted according to the gate-source voltage (Vgs) of the first TFT (T1) flows to the OLED, causing the OLED to emit light. During the duty driving period tem, the first and second scan signals SCAN1 and SCAN2 remain at the off level, so the third and fourth TFTs T3 and T4 are turned off.

The current (Ioled) flowing through the OLED during the duty driving period (tem) is given in Equation 1. OLED emits light using this current to express the brightness of the input image.

In Equation 1, k is a proportionality constant determined by the mobility of the first TFT (T1), parasitic capacitance, and channel capacity.

Since Vgs programmed through the programming period (tw) includes Vth, Vth is erased from Ioled in Equation 1. Accordingly, the influence of the threshold voltage (Vth) of the driving element, that is, the first TFT (T1), on the current (Ioled) of the OLED is eliminated.

Figure 11 is a waveform diagram showing a duty driving method of a pixel circuit according to an embodiment of the present invention. Figure 12 is a diagram showing the BDI effect in the duty driving method of a pixel circuit according to an embodiment of the present invention. In Figure 12, (a) is an image of 1 frame. Figure 12 (b) shows an example in which the non-duty driving period (light-off period) is sequentially shifted when an image such as (a) is displayed on pixels using the duty driving method. Figure 13 is a diagram showing the principle of maintaining data in a pixel without additional data addressing within one frame period.

Referring to Figures 11 and 12, the vertical synchronization signal (Vsync) is a timing signal that defines one frame period. During one frame period, one frame worth of image data is addressed and written into the pixels 10.

Data of the input image is addressed and written into pixels only during the initial scanning period of one frame period. The pixels are turned off in the off-level section of the EM signal (EM), but maintain the data voltage as shown in FIG. 9 and emit light with the same luminance during the lighting period after the turning-off period as the lighting period before the turning-off period.

The on level section (On) of the EM signal (EM) defines the lighting section in the pixel array. The on-level EM signal (EM) forms a current path for the OLED in the pixels 10 and turns on the OLED. In comparison, the off level section (Off) of the EM signal (EM) defines an unlit section in the pixel array. During the off period, an off-level EM signal (EM) is applied to the pixels 10. The pixels 10 in the unlit section display a black grayscale because the current path of the OLED is blocked and no current flows to the OLED.

The EM signal (EM) has two or more cycles within the duty driving period (tem) of one frame period. One cycle of the EM signal EM includes one on-level section and one off-level section. Therefore, during the duty driving period (tem), the on-level section (On) and the off-level section (Off) of the EM signal (EM) alternate so that the adjacent on-level section (On) has the off-level section (Off) in between. disconnected. Each of the pixels 10 is turned off at least once within the duty driving period (Off) by the EM signal (EM). Since the off-level section (Off) of the EM signal (EM) is shifted along the scan direction of the display panel, the unlit section in the pixel array (AA) also follows the off-level section (Off) of the EM signal (EM), as shown in FIG. is shifted.

This duty driving method drives the pixels 10 at a duty ratio of 50& or less to improve afterimages and flicker and reduce user fatigue, especially when displaying 3D video on a personal immersive device.

In the present invention, the data voltage of the pixels is maintained even without additional data being written during the duty driving period. This is explained in conjunction with FIG. 13 as follows.

Referring to FIG. 13, after writing data to pixels through data addressing, the first scan pulse SCAN1 maintains an off level for one frame period. As a result, after the data voltage is charged in the storage capacitor Cst, the first node A to which the gate of the first TFT T1 is connected is floating. When the source voltage (Vs) of the first TFT (T1) changes, the charge of the storage capacitor (Cst) remains constant and the gate voltage (Vg) changes along Vs. As a result, even if data is not written again after the pixels 10 are turned off due to the on-level section and the off-level section of the EM signal (EM), the gate-source voltage (Vgs) of the first TFT (T1), which is a driving element, is ) remains constant. Since the Vgs of the driving element T1 is maintained constant, the data written to the pixel 10 is maintained.

Figure 14 is a diagram showing a display device of a personal immersive device according to an embodiment of the present invention.

Referring to FIG. 14, the display device of the present invention includes first and second display panels (PNL1 and PNL2) and one PMIC.

Each of the first and second display panels (PNL1 and PNL2) is implemented as the above-described OLED display panel. Drive ICs (DIC1 and DIC2) are connected to each of the first and second display panels (PNL1 and PNL2). The first drive IC (DIC1) writes data of the input image to the pixels of the first display panel (PNL2). The second drive IC (DIC2) writes data of the input image to the pixels of the second display panel (PNL2).

The PMIC is mounted on the printed circuit board (PCB) of the display module 13. PMIC adjusts the input voltage using a DC-DC converter, charge pump, and regulator to generate the driving voltage necessary to drive the display panel. The PMIC generates a first driving voltage (DDVDH) in response to the first enable signal (EN1) and generates a second driving voltage (VDDEL) in response to the second enable signal (EN2). One of the first and second drive ICs (DIC1 and DIC2) supplies the first and second enable signals (EN1 and EN2) to the PMIC. The first driving voltage DDVDH is a reference driving power applied to the data driving part of the drive IC (DIC). The gamma compensation voltage generator of the drive IC (DIC) divides the first driving voltage (DDVDH) using a voltage dividing circuit to generate a gamma compensation voltage. The second driving voltage VDDEL is a pixel driving power source, as shown in FIG. 9 . The charge pump of the PMIC receives the second driving voltage (VDDE) and outputs the gate high voltage (VGH) and gate low voltage (VGL). The gate high voltage (VGH) is the high level voltage of the scan pulse and EM pulse, and the gate low voltage (VGL) is the low level voltage of the scan pulse and EM pulse.

The display device of the present invention uses one or more of the first to third embodiments below to set a time difference between the drive start timing of the first and second display panels (PNL1 and PNL2) to distribute the load variation on the time axis. This prevents PMIC load surges. As a result, the present invention can stably supply the power required to drive the display panels (PNL1 and PNL2) by connecting one PMIC to a plurality of display panels (PNL1 and PNL2). The present invention can connect the PMIC applied to existing mobile devices to multiple display panels (PNL1 and PNL2).

[First Example]

The drive start timing time difference between the drive ICs (DIC1 and DIC2) can be set using the external pin (EP) of the drive ICs (DIC1 and DIC2). The external pin (EP) of each of the drive ICs (DIC1, DIC2) is connected to an enable delay circuit in the drive ICs (DIC1, DIC2). The enable delay circuit adjusts the drive start timing of the drive ICs (DIC1 and DIC2) according to the logic state of the external pin (EP). For example, when a high logic voltage (eg, Vcc) is applied to the external pin (EP), the drive ICs (DIC1 and DIC2) begin to be driven at a preset reference timing. Conversely, when a low logic voltage (eg, GND=0V) is applied to the external pin (EP), the drive ICs (DIC1 and DIC2) begin to be driven after a predetermined start delay time (Δt) from the reference timing. If the external pin (EP) of the first drive IC (DIC) is in a high logic state and the external pin (EP) of the second drive IC (DIC) is in a low logic state, after the first drive IC (DIC1) starts to drive , the second drive IC (DIC2) is driven after a predetermined start delay time (Δt). The difference in driving start timing times of the drive ICs (DIC1, DIC2) results in a difference in output time between the drive ICs (DIC1, DIC2), resulting in a difference in scanning time of the display panels (PNL1, PNL2). In the present invention, the drive start timing time difference of the drive ICs (DIC1 and DIC2) can be set to a time difference at which the user does not notice a screen abnormality. For example, the drive start timing time difference of the drive ICs (DIC1 and DIC2) may be set to be greater than 0 and within 1 horizontal period.

[Second Embodiment]

The present invention can adjust the driving start timing of the drive ICs (DIC1 and DIC2) using register settings of the drive ICs (DIC1 and DIC2). In the case of a mobile device, the register settings may be timing data settings stored in OTP memory (one time programmable memory). For example, if the register setting value is Addr: 0xE9, value: 0x00, the drive ICs (DIC1, DIC2) start driving at the preset reference timing. If the register setting value is Addr: 0xE9, value: 0x01, the drive ICs (DIC1, DIC2) start driving after a predetermined start delay time (Δt) from the reference timing.

[Third Embodiment]

A time difference can be set between the data transmission timing between the host system processor (AP) and the drive ICs (DIC1 and DIC2). The host system processor (AP) is connected to external input devices, various sensors, communication modules, display modules, etc. The host system processor (AP) controls the entire personal immersive device. In the case of a mobile device, the host system processor (AP) may be an application processor.

The host processor (AP) includes first and second video signal interfaces (MIPI1 and MIPI2). The host processor (AP) is connected to the first drive IC (DIC1) through the first video signal interface (MIPI1) and starts transmitting the left eye image signal to the first drive IC (DIC1) at the reference timing. The left eye image signal includes data of an input image to be displayed on the first display panel PNL1 and a timing signal synchronized with the data. The host processor (AP) is connected to the second drive IC (DIC2) through the second video signal interface (MIPI2) and transmits the right eye video signal to the second drive IC (DIC2) after a predetermined start delay time (Δt) from the reference timing. Start transmitting. The right eye image signal includes data of an input image to be displayed on the second display panel PNL2 and a timing signal synchronized with the data. In the case of mobile devices, the video signal interface may be MIPI (Mobile Industry Processor Interface). Video signal transmission timing can be controlled in each of the first and second video signal interfaces (MIPI1 and MIPI2) according to user settings.

FIG. 15 is a diagram showing the drive ICs (DIC1 and DIC2) shown in FIG. 14 in detail.

Referring to FIG. 15, the drive IC (DIC) includes a timing controller (TCON), a gamma compensation voltage generator (GMAG), and a data driver. The data driver includes a data latch (DL), a level shifter (LS), a digital to analog converter (DAC), and an output buffer (AMP).

The first driving voltage DDVDH is supplied as a reference power source for the gamma compensation voltage generator (GMAG), the level shifter (LS), the digital to analog converter (DAC), and the output buffer (AMP).

The gamma compensation voltage generator (GMAG) divides the first driving voltage (DDVDH), outputs a gamma compensation voltage with a different voltage for each gray level, and supplies it to the digital-to-analog converter (DAC). The data latch (DL) latches the data received from the timing controller (TCON) and outputs it simultaneously, converting serially input data into parallel data. The level shifter (LS) shifts the voltage level of data input from the data latch (DL) to the input voltage range of the digital-to-analog converter (DAC). The digital-to-analog converter (DAC) generates a data voltage by converting data input through a level shifter (LS) into a gamma compensation voltage. The voltage level of the data voltage output from a digital-to-analog converter (DAC) varies depending on the gray level of the data. The output buffer (AMP) uses a voltage follower implemented as an operational amplifier (OP-AMP) to convert the data voltage input from the digital-to-analog converter (DAC) into the data of the display panels (PNL1, PNL2). conveyed through lines.

Figure 16 is a diagram showing registers connected to the timing controller (TCON).

Referring to FIG. 16, the drive IC further includes a one time programmable memory (OTP) and a display command set (DCS) register (DCS).

The OTP memory (OTP) stores data indicating the panel characteristics and driving timing settings of each display panel (PNL1, PNL2). The DCS register (DCS) reads panel data from OTP memory (OTP) in the power on sequence when the display device is turned on and transmits it to the timing controller (TCON). The timing controller (TCON) controls the driving timing of each of the display panels (PNL1 and PNL2). As described above, the timing controller (TCON) can differently control the driving start timing of the display panels (PNL1, PNL2) using the register settings in each of the display panels (PNL1, PNL2).

Figure 17 shows the PMIC load variation when the display panels (PNL1, PNL2) start to be driven simultaneously in the power on sequence and when the display panels (PNL1, PNL2) start to be driven with a predetermined time difference. This is a comparison drawing. Figure 17 shows the voltage (DDVDH(V)) and current (DDVDH(I)) measurement waveforms of the DDVDH output channel of the PMIC at the point when the PMIC's output begins to be generated during the power-on sequence. When two display panels (PNL1, PNL2) start to be driven simultaneously, the load on the output channel of the PMIC rapidly increases, generating an in-rush current, which increases the in-rush peak. In contrast, the present invention reduces the load fluctuation of the PMIC by delaying the start timing of any one of the two display panels (PNL1, PNL2) by a predetermined start delay time (Δt), thereby reducing the in-rush peak. lower it

Figure 18 is a diagram comparing PMIC load changes when the display panels start to be driven simultaneously while the data voltage and reference voltage are output from the drive IC after the power-on sequence and when the two display panels start to be driven with a predetermined time difference. am. When the power voltage of the drive ICs (DIC1, DIC2) is supplied in the power-on sequence, the drive ICs (DIC1, DIC2) output the data voltage (Vdata) and the reference voltage (Vref) of the input image. When the two drive ICs (DIC1, DIC2) start generating output at the same time, the display panels (PNL1, PNL2) are driven simultaneously, so the load on the output channel of the PMIC increases rapidly, increasing the in-rush peak. In contrast, the present invention delays the driving start timing of any one of the two display panels (PNL1, PNL2) by a predetermined start delay time (Δt) to reduce the load fluctuation range of the PMIC, reducing the in-rush peak. lower the

FIG. 19 is a diagram showing the time difference in driving start timing between the display panels PNL1 and PNL2. In FIG. 19, #1 to #1280 are line numbers of the pixel array AA in each of the display panels PNL1 and PNL2. 1Frame1~Frame9 represent frame period numbers.

Referring to FIG. 19, the scanning start timing (video start) differs by Δt due to the difference in driving start timing between the display panels (PNL1 and PNL2). Δt is set to a time during which the user cannot perceive binocular delay, for example, a time greater than 0 and less than or equal to 1 horizontal period (1H). 1 horizontal period (1H) is the time divided by 1 frame period by the number of lines. When the frame rate is 90Hz, one frame period is approximately 11.1 ms, and one horizontal period is approximately 1H = 11.1/1280 = 8.68 μs.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

PNL1, PNL2: Display panel AA: Pixel array
LENS: Fisheye lens 110: Timing controller
102: data driver 104: gate driver
106: EM driver PMIC: Power integrated circuit
DIC1, DIC2: Drive integrated circuit AP: Host system processor
MIPI1, MIPI2: video signal interface

Claims (8)

a first drive integrated circuit that drives the first pixel array of the first display panel;
a second drive integrated circuit that drives a second pixel array of a second display panel spaced apart from the first display panel; and
A power integrated circuit that generates power required to drive the first and second pixel arrays and supplies it to the first and second drive ICs,
The driving start timing of the second pixel array is delayed from the driving start timing of the first pixel array by a predetermined start delay time,
The display device of claim 1, wherein the predetermined start delay time is greater than 0 and less than or equal to 1 horizontal period. According to claim 1,
Each of the first drive integrated circuit and the second drive integrated circuit includes an external pin that defines a drive start timing according to a logic state,
The first drive integrated circuit starts driving at a reference timing in response to a first logic state of the external pin, and the second drive integrated circuit starts driving from the reference timing to the predetermined time in response to a second logic state of the external pin. A display device that starts operating at a timing delayed by the start delay time. According to claim 1,
The display device wherein the second drive integrated circuit begins to drive later than the first drive integrated circuit by the predetermined start delay time in response to a register setting value that is different from the register setting value of the first drive integrated circuit. According to claim 1,
Further comprising a host system processor that supplies image signals to the first and second drive integrated circuits,
The host system is,
Start transmitting a first image signal to the first pixel array at a reference timing through a first video signal interface,
A display device that starts transmitting a second image signal to the second pixel array through a second video signal interface at a timing delayed from the reference timing by the predetermined start delay time. delete According to claim 1,
A display device in which the scanning start timing of the second pixel array is slower than the scanning start timing of the first pixel array. According to claim 1,
A display device wherein each of the first and second pixel arrays is an Organic Light Emitting Diode (OLED) display panel. According to claim 1,
The first display panel is a display panel for left or right eyes,
The second display panel is a display panel for right eyes if the first display panel is a display panel for left eyes, and a display panel for left eyes if the first display panel is a display panel for right eyes.