KR102553878B1 - Non-volatile memory-based storage device, and device controller and method thereof - Google Patents

Abstract

A device controller of a storage device including non-volatile memory may pick a command from a submit queue and determine whether the peaked command is executable based on a state of device resources. The device controller may fetch the command in response to determining that the command is executable, allocate device resources to the fetched command, and execute it.

Description

Non-volatile memory based storage device, device controller and method

The disclosure relates to a non-volatile memory based storage device, device controller and method.

Read resources and write resources may separately exist in a resource pool of a non-volatile memory-based storage device such as a solid-state drive (SSD). Read and write resources can each be used to process a specific type of input/output (I/O). Resource pools can also contain shared resources shared by all types of I/O.

When the shared resources are exhausted, the storage device temporarily suspends command processing of all I/O types until the shared resources are available again. In particular, if the storage device fetches a large number of write commands, almost all of the shared resources may be occupied by the write commands. Typically, processing write commands takes longer, so shared resources can be occupied longer. Therefore, the read command may use the read resource, but the storage device may not be able to process the read command because the shared resource is exhausted. Also, if the storage device brings a write command when the write resource is exhausted, the storage device may block the shared resource until the write resource is available. Then, even if the storage device comes with a read command, it may not be able to process the read command. In this way, other commands wait due to exhaustion of some resources, and the wait command may cause a bottleneck in the command processing pipeline, so command waiting time may increase and command processing efficiency may decrease.

Certain embodiments may provide a non-volatile memory-based storage device capable of increasing command processing efficiency, a device controller or method thereof.

According to one embodiment, a device controller of a storage device including a non-volatile memory may be provided. The device controller may include device resources, command fetch logic, command preprocessing logic, and command processing logic. The command fetch logic may pick a first command from a first submit queue among a plurality of submission queues, and fetch the first command in response to determining that the first command is executable. The command preprocessing logic may determine whether the first command peaked in the command fetch logic is executable based on the state of the device resource. The command processing logic may allocate the device resource to the first command fetched by the command fetch logic and execute the first command in response to determining that the first command is executable.

In some embodiments, the instruction fetch logic may move the head pointer of the first submit queue to fetch the first instruction at the peak of the first instruction, without moving the head pointer of the first submit queue. can

In some embodiments, the command fetch logic may pick a second command from a second submit queue of the plurality of submit queues. The command pre-processing logic determines whether the second command is executable based on the state of the device resource, and in response to determining that the second command is not executable, sets the second submit queue to wait for the device resource. status can be specified.

In some embodiments, the instruction fetch logic may drop the second instruction rather than fetch it in response to determining that the second instruction is not executable.

In some embodiments, the command pre-processing logic may determine whether the second submission queue designated as the waiting state is available for processing based on a state of the device resource. In response to determining that the second submit queue is processable, the command fetch logic may pick the second command from the second submit queue, and the command preprocessing logic may determine whether the second command is executable. .

In some embodiments, the command pre-processing logic may determine that the second submission queue is processable when a resource in which the second command waits is available among the device resources.

In some embodiments, the command pre-processing logic may preferentially process the second submission queue over the other submission queues of the plurality of submission queues.

In some embodiments, the device controller may further include a pending command queue. The command fetch logic may pick the first command and the second command from the first submit queue. In response to the instruction pre-processing logic determining that the first instruction is executable and the second instruction not executable, the instruction fetch logic fetches the first instruction and the second instruction, wherein the instruction pre-processing logic The second command may be stored in the pending command queue.

In some embodiments, the command preprocessing logic may determine whether a third command stored in the pending command queue is executable based on a state of the device resource. In response to determining that the third command in the pending command queue is executable, the command processing logic may execute the third command in the pending command queue.

In some embodiments, the command pre-processing logic may preferentially process the pending command queue over the plurality of submit queues.

In some embodiments, the command fetch logic may pick the first command and the second command from the first submit queue. In response to the command preprocessing logic determining that the first command is executable and the second command is not executable, the command fetch logic fetches the first command from the first submit queue, and the second command can be packed in the first submission queue.

In some embodiments, the instruction fetch logic may move a head pointer of the first submit queue by the number of the first instructions, and may pack the second instructions from an entry to which the head pointer is moved.

In some embodiments, the command pre-processing logic may determine whether the packed first submit queue is processable based on a state of the device resource. In response to determining that the first submit queue is processable, the command fetch logic may pick the second command from the first submit queue, and the command preprocessing logic may determine whether the second command is executable. .

In some embodiments, the command pre-processing logic may preferentially process the first submission queue over the rest of the plurality of submission queues.

In some embodiments, the command preprocessing logic may determine that the first command is executable when a resource for executing the first command is available among the device resources, and may fetch the first command.

In some embodiments, the device resource may include a read resource dedicated to a read command, a write resource dedicated to a write command, and a shared resource shared by the read command and the write command. The command pre-processing logic determines that a resource for executing the first command is available when a resource corresponding to the input/output type of the first command and the shared resource among the read resource and the write resource are available, The first instruction can be fetched.

In some embodiments, the device resource may include multiple types of resources used to execute the first instruction. The command pre-processing logic may determine that a resource for executing the first command is not available when some type of resource among the plurality of types of resources is not available.

In some embodiments, the command preprocessing logic may not allocate a device resource to the first command if a resource for executing the first command is not available among the device resources.

According to another embodiment, a storage device including a non-volatile memory and a device controller may be provided. The device controller controls access to the non-volatile memory, fetches a first command from a first submission queue without moving the head pointer of the first submission queue, and determines whether the first command is executed based on a state of a device resource. It is determined whether the command is executable, and the head pointer of the first submission queue may be moved in response to determining that the first command is executable.

According to another embodiment, a method executed by a storage device including a non-volatile memory may be provided. The method includes picking a command from a submit queue, determining whether the command is executable based on a state of device resources, fetching the command in response to determining that the command is executable, and In response to determining that it is executable, allocating device resources to the command and executing the command.

1 is an exemplary block diagram of a storage system according to one embodiment.
2 is an exemplary block diagram of a storage system according to another embodiment.
3 is an exemplary block diagram of a device controller of a storage device according to one embodiment.
4 is a diagram illustrating device resources of a device controller according to one embodiment.
5 and 6 are diagrams for explaining an example of an operation of the device controller shown in FIG. 3 .
7 is a flowchart illustrating operation of a device controller of a storage device according to one embodiment.
8 is an exemplary block diagram of a device controller of a storage device according to another embodiment.
9 is a diagram illustrating a device controller of a storage device according to another embodiment.
FIG. 10 is a diagram for explaining an example of an operation of the device controller shown in FIG. 9 .
11 is a flowchart illustrating an operation of a device controller of a storage device according to another embodiment.
12 is a diagram illustrating a device controller of a storage device according to another embodiment.
FIG. 13 is a diagram for explaining an example of an operation of the device controller shown in FIG. 12;
14 is a flowchart illustrating an operation of a device controller of a storage device according to another embodiment.
15 is an example block diagram illustrating a computer system according to one embodiment.

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein.

And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification. In the flowchart described with reference to the drawings, the order of operations may be changed, several operations may be merged, a certain operation may be divided, and a specific operation may not be performed.

In addition, expressions written in the singular may be interpreted in the singular or plural unless explicit expressions such as “one” or “single” are used. Terms including ordinal numbers, such as first and second, may be used to describe various components, but the components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

1 is an exemplary block diagram of a storage system according to one embodiment.

Referring to FIG. 1 , the storage system 100 may include a host device 110 and a storage device 120 .

The host device 110 may include a computing platform (or computing device) capable of interfacing with the storage device 120 . The host device 110 may be, for example, a desktop computer, a server computer, a tablet computer, a laptop computer, a mobile phone such as a smartphone, a multimedia player ( multimedia players), game consoles, televisions, various types of Internet of Things (IoT) devices, etc., but are not limited thereto.

The host device 110 may include a processor 111 and a host memory 112 . The processor 111 may perform various operations (eg, arithmetic, logic, control, input/output, etc.) by executing instructions. The processor 111 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, or an application processor (AP). The host memory 112 may be system memory accessed and used by the processor 111 . Host memory 112 may include, for example, random access memory, such as dynamic random access memory (RAM).

The storage device 120 is a non-volatile memory-based storage device and may include a device controller 121 and a non-volatile memory 122 . The device controller 121 may control access to the nonvolatile memory 122 . In some embodiments, the device controller 121 may support a non-volatile memory express (NVMe) protocol as a protocol for accessing the non-volatile memory 122 . In some embodiments, non-volatile memory may include flash based memory, such as NAND flash memory. In some embodiments, the non-volatile memory may include, for example, phase-change memory, resistive memory, magnetoresistive memory, ferroelectric memory, or polymer memory. can

In some embodiments, the storage device 120 may be detachably connected to the host device 110 . In some embodiments, the storage device 120 may be integrated within the host device 110 or non-removably coupled to the host device 110 .

The host device 110 may perform various operations by submitting commands to the storage device 120 . For example, the host device 110 submits a read command to the storage device 120 to read data from the storage device 120 or submits a write command to the storage device 120 to store data. Data may be stored on the device 120 .

In order for the host device 110 to read or write data from the storage device 120, the processor 111 generates a command (eg, a read command or a write command) and submits a submission queue of the host memory 112. A command may be submitted (or written) to the queue, SQ) 112a. In some embodiments, the submission queue 112a may support the NVMe protocol. The device controller 121 peeks the command submitted to the submit queue 112a of the host memory 112, determines whether the command is executable based on the device resource status of the device controller 121, and determines whether the command is executed. In response to determining that it is executable, the instruction may be fetched and executed. In some embodiments, “picking” a command may refer to an action that brings a command from a submit queue to the device controller but allows the command to remain on the submit queue for re-fetching. Thus, the device controller 121 peaks an instruction by fetching an instruction from the submission queue 112a without moving the head pointer of the submission queue 112a, and moves the head pointer of the submission queue 112a after the peak of the instruction to the submit queue. Fetch the instruction from 112a (ie, complete the instruction fetch operation). The device controller 121 may transfer data from the non-volatile memory 122 to the host memory 112 by executing a read command or transfer data from the host memory 112 to the memory device 122 by executing a write command. there is.

2 is an exemplary block diagram of a storage system according to another embodiment.

Referring to FIG. 2 , the storage system 200 may include a host device 210 and a storage device 220 .

The host device 210 may include a processor 211 and a host memory 212 . The storage device 220 may include a device controller 221 and a non-volatile memory 222 . Unlike the embodiment described with reference to FIG. 1 , the device controller 221 may further include a memory buffer 221a in which a submission queue in which commands from the host device 210 are submitted (or written) is formed. In some embodiments, the memory buffer 221a may be a controller memory buffer (CMB) supporting the NVMe protocol.

In order for the host device 210 to read or write data from the storage device 220, the processor 211 may generate a command and submit the command to a submission queue of the memory buffer 221a. The device controller 221 picks the command submitted to the submission queue of the memory buffer 221a, determines whether the command is executable based on the device resource status of the device controller 221, and responds to the determination that the command is executable. to fetch the command and execute the command. The device controller 221 may pick an instruction from the submit queue without moving the head pointer of the submit queue and fetch the instruction from the submit queue by moving the head pointer of the submit queue. The device controller 221 may transfer data from the memory device 222 to the host memory 212 by executing a read command or transfer data from the host memory 212 to the memory device 222 by executing a write command. .

3 is an exemplary block diagram of a device controller of a storage device according to an embodiment, FIG. 4 is a diagram illustrating a device resource of the device controller according to an embodiment, and FIGS. 5 and 6 are the device shown in FIG. 3 It is a drawing explaining an example of the operation of the controller.

Referring to FIG. 3 , the device controller 300 may include an instruction fetch logic 310 , a command preprocessing logic 320 , a command processing logic 330 and a device resource 340 .

In some embodiments, the device controller 300 further includes a memory buffer 350, and the memory buffer 350 may include a plurality of submission queues 351, 352, ..., 35n. In some embodiments, a plurality of submission queues 351 to 35n may be formed in a host memory (eg, 112 of FIG. 1 ) of the host device. The plurality of submission queues 351, 352, ..., 35n may be expressed as SQ1, SQ2, ..., SQn, respectively. The host device can generate commands and put the generated commands into the submission queue 35i. In some embodiments, after the host device puts the command into submit queue 35i, the register corresponding to submit queue 35i of device controller 300 (eg, the SQ tail doorbell register) is used as the new tail pointer. can be renewed

The instruction fetch logic 310 may pick an instruction from the submit queue 35i. When peaking an instruction from submit queue 35i, instruction fetch logic 310 may not move the head pointer of submit queue 35i. The command fetch logic 310 may temporarily store the peaked command in a buffer of the device controller 300 or a buffer of a storage device including the device controller 300 . In some embodiments, the command fetch logic 310 may select a target submit queue 35i from the plurality of submit queues 351 - 35n and pick a command from the selected submit queue 35i. The command fetch logic 310 may select the target submit queue 35i based on, for example, an arbitration mechanism supported by the device controller 300 . In some embodiments, instruction fetch logic 310 may determine the number of instructions to peak from submit queue 35i based on an arbitration burst size and the number of instructions available in submit queue 35i. . Arbitration burst size may mean the maximum number of commands that can be retrieved from the submission queue at one time. Instruction fetch logic 310 may determine, for example, the smaller of the arbitration burst size and the number of instructions available in submit queue 35i as the number of instructions to pick from submit queue 35i. The number of commands available in the submission queue 35i may correspond to the number of commands from the head to the tail of the submission queue 35i. The head may be an entry indicated by the head pointer in the submission queue 35i, and the tail may be an entry indicated by the tail pointer in the submission queue 35i. Accordingly, the instruction fetch logic 310 may peak as many instructions as it determines from the head of the submit queue 35i.

Command preprocessing logic 320 may determine the feasibility of the peak command based on the state of device resources 340 . Command pre-processing logic 320 may determine feasibility by determining whether device resources 340 are available for executing the peak command. In some embodiments, device resources 340 may include read resources 341 dedicated to read commands and write resources 342 dedicated to write commands. The device resource 340 may further include a shared resource 343 shared by a read command and a write command.

The command pre-processing logic 320 may determine that the command is executable when it is determined that a resource for executing the peak command is available among the device resources 340 . In some embodiments, since the type of resource may vary depending on the input/output (I/O) type of the peak command, the command preprocessing logic 320 may determine the I/O type of the peak command, the shared resource 343 ), and whether a resource for processing a peak command is available can be determined based on a resource corresponding to an I/O type among the read resource 341 and the write resource 342. In some embodiments, since the amount of resources required may vary depending on the size of the peak command, the command pre-processing logic 320 determines which resources are used to process the peak command based on the I/O type and size of the peak command. You can judge if it is possible. The command pre-processing logic 320 may determine that the command is not executable when the resource for processing the peak command among the device resources 340 is occupied for other I/O processing and cannot be used. For example, the command pre-processing logic 320 determines that the read command cannot be executed if the read resource 341 or the shared resource 343 is occupied and cannot be used, and the read resource 341 and the shared resource 343 are If available, it can be determined that the read command can be executed. In addition, the command pre-processing logic 320 determines that the write command cannot be executed when the write resource 342 or the shared resource 343 is occupied and unavailable, and the write resource 342 and the shared resource 343 are available. In this case, it can be determined that the write command can be executed.

If it is determined that the peaked command is executable, the command preprocessing logic 320 may fetch the corresponding command through the command fetch logic 310 and instruct the command processing logic 330 to execute the fetched command. The instruction fetch logic 310 may fetch instructions from the submit queue 35i by moving the head pointer by the number of fetched instructions (entries) in the submit queue 35i. Accordingly, the head pointer of the submission queue 35i may be moved to the next entry of the fetched instruction.

The command processing logic 330 may allocate device resources 340 to the fetched command and execute the fetched command. In some embodiments, command processing logic 330 may put the fetched command into a command processing pipeline for execution. The command processing logic 330 may put the fetched command into the command processing queue of the command processing pipeline, retrieve the command from the command processing queue, and execute the command. The instruction processing pipeline may include a series of processing engines that perform instruction processing (execution) using device resources 340 .

If instruction preprocessing logic 320 determines that the peaked instruction is not executable, instruction processing logic 330 may not fetch the peaked instruction. Therefore, the head pointer of the submission queue 35i can be maintained without being moved. The instruction preprocessing logic 320 may drop the peaked instruction without fetching it, without instructing the instruction processing logic 330 to execute the instruction. Accordingly, the command processing logic 330 may not allocate resources to the peak command and may not put the peak command into the command processing pipeline. In addition, the command pre-processing logic 320 may designate the submission queue 35i as a resource standby state. In some embodiments, the resource waiting state may include information indicating a waiting resource. Information indicating waiting resources may include, for example, the type of waiting resources and the amount of waiting resources.

After processing the target submission queue 35i, the device controller 300 selects the next target submission queue 35j from the plurality of submission queues 351 to 35n, and picks and peaks a command from the target submission queue 35j. The process of determining whether a command is executable can be repeated.

In some embodiments, the command preprocessing logic 320 may monitor the state of the device resource 340 and, based on the state of the device resource 340, determine whether the pending submission queue 35i is available for processing. . In some embodiments, the command pre-processing logic 320 may determine that the submission queue 35i is ready for processing when a resource of the submission queue 35i designated as a standby state becomes available. If it is determined that submit queue 35i is processable, command preprocessing logic 320 may designate submit queue 35i as an available submit queue 35i. Accordingly, as described above, an operation of determining whether a command is executable by peaking a command in the submission queue 35i may be performed. In some embodiments, when a resource of the submission queue 35i designated as a standby state becomes available, the command preprocessing logic 320 does not perform an operation to peak a command from the submission queue 35i, and the submission queue ( 35i) may fetch the instruction and instruct the instruction processing logic 330 to execute the instruction. In some embodiments, when a resource becomes available, command preprocessing logic 320 may preferentially process the queue 35i designated as pending over other submission queues. For example, the command pre-processing logic 320 may add the submission queue 35i designated as pending to the head of the list of available submission queues.

In some embodiments, when command processing logic 330 completes execution of a command of a particular I/O type, a resource of that I/O type may become available. When the command processing logic 330 completes processing of a particular type in the command processing pipeline, that type of resource may become available. For example, when the command processing logic 330 completes the execution of a read command, the read resource 341 and the shared resource 343 become available, and when the write command completes, the write resource 342 and the shared resource 343 may be in a usable state.

Referring to FIG. 4 , in some embodiments, a read resource 341 , a write resource 342 , and a shared resource 343 may each include various types of resources. The read resource 341 includes at least one of a read buffer 341a or a direct memory access (DMA) read descriptor 341b, and the write resource 342 includes a write buffer 342a or a DMA It may include at least one of the write descriptors 342b.

The read buffer 341a temporarily stores data read from a non-volatile memory (eg, 122 in FIG. 1 or 222 in FIG. 2 ), and the DMA read buffer 341b stores data read from a storage device to a host memory (eg, 222 in FIG. 2 ). Information related to DMA transfer to 112 in FIG. 1 or 212 in FIG. 2) may be stored. The write buffer 342a temporarily stores data to be written to the non-volatile memory 122 or 222, and the DMA write descriptor 342b stores information related to DMA transfer from the host memory 112 or 212 to the storage device. can

The shared resource 343 includes a plurality of types of shared resources, including an address translation cache (ATC) resource 343a, a host connection resource 343b, and a tag resource 343c. , channel resource 343d, core resource 343e, address translation resource 343f, physical region page (PRP)/scatter gather list (SGL) buffer 343g or command completion resource ( 343h) may include at least one.

The address translation cache 343a may store address translation data used when converting a virtual address referenced by a PRP or SGL parsed from an instruction into a physical address of the host memory 112 or 212 . The host connection resource 343b may include resources related to an interface (eg, a peripheral component interconnect express (PCIe) interface) used for connection with the host. The tag resource 343c may include a resource (tag) allocated for unique identification of an instruction within the instruction processing pipeline. The channel resource 343d may include channel related resources between the device controller 300 and the non-volatile memory 122 or 222 . The core resource 343e may include processing core resources for processing commands in command processing logic. The address conversion resource 343f converts a logical address (eg, a logical block address (LBA)) parsed from an instruction into a physical address (eg, a physical page number (PPN)) of the non-volatile memory 122 or 222 . The PRP/SGL buffer 343g may temporarily store the PRP or SGL parsed from the command The command completion resource 343h may include resources for completing command completion.

If an instruction requires resources of various types to execute, if some types of resources are available but some other types of resources are not available, the instruction preprocessing logic 320 determines that the instruction is not executable, and , may not fetch that instruction. In addition, among the plurality of types of shared resources 343a to 343h, some types of shared resources (eg, tag resources 343c) can be used, but some other types of shared resources (eg, address conversion resources ( If 343f)) is not available, command preprocessing logic 320 may determine that shared resource 343 is not available.

For example, as shown in FIGS. 5 and 6, two write commands and two read commands are input to the submission queue SQ1, and four write commands and one read command are input to the submission queue SQ2. Assume that four read commands and one write command are input to the submission queue (SQ3), the head pointer points to the first entry in the submission queue (SQ1, SQ2, and SQ3), and the arbitration burst size is 4. . In FIGS. 5 and 6 , a write command is indicated by “W” and a read command is indicated by “R”. Also, it is assumed that the write resource 342 among the device resources 340 is exhausted and unavailable.

In this case, the typical device controller may fetch the write command from the submit queue SQ1 and wait until the write resource 342 for execution of the fetched write command becomes available. Additionally, the device controller may block the shared resource 343 until a write resource becomes available. When the write resource 342 becomes available, the device controller may execute a write command and a read command fetched from the submit queue SQ1 and then fetch commands from the next submit queue SQ2. Therefore, the execution of all commands waits until the resource becomes available, which can lead to a long waiting time. In addition, since the write command occupies the shared resource 343 even while the write command is waiting, even if the read command is fetched while the read resource 341 is available, the read command continues until the shared resource 343 becomes available. may not be feasible.

In some embodiments, as shown in FIG. 5, command fetch logic 310 selects a target submit queue SQ1 from among a plurality of submit queues SQ1, SQ2, and SQ3, and writes two writes from submit queue SQ1. command and two read commands. Since the write resource 342 for executing the write command is not available, the command pre-processing logic 320 may designate the submission queue SQ1 as a resource standby state. In this case, since the submission queue SQ1 is in a command peak state, the head pointer of the submission queue SQ1 can be maintained without moving. The command fetch logic 310 may peak four write commands from the next submit queue SQ2. Similarly, since the write resource 342 for executing the write command is not available, the command pre-processing logic 320 may designate the submission queue SQ2 as a resource standby state. In this case, since the submission queue SQ2 is also in a command peak state, the head pointer of the submission queue SQ2 can be maintained without moving.

As shown in FIG. 6, the command pre-processing logic 320 may peak four read commands from the next submit queue SQ3. Since the read resource 341 and the shared resource 343 for executing the read command are available, the command fetch logic 310 fetches the read command, and the command processing logic 330 can execute the fetched read command. there is. In this case, since the command of the submission queue SQ3 has been fetched, the head pointer of the submission queue SQ3 can be moved. Therefore, since an immediately executable command can be executed first without waiting for the occupied resource (write resource 342) to be released, waiting time can be reduced and command processing efficiency can be increased accordingly.

7 is a flowchart illustrating operation of a device controller of a storage device according to one embodiment.

Referring to FIG. 7 , when there is an available submission queue (S730), the device controller may select a target submission queue from the available submission queues (S735). In some embodiments, an available submission queue may be a submission queue that has not been marked as pending. When there is no usable submission queue (S730), the device controller may end the operation. If a command exists in the target submission queue (S740), the device controller may pick the next command from the target submission queue (S745). The device controller may pick a command from the target submission queue and maintain the head pointer without moving (S745). In some embodiments, the device controller may pick commands corresponding to the minimum number of the arbitration burst size and the number of commands available in the target submission queue from the target submission queue (S745).

The device controller may determine the possibility of executing the peak command based on the state of device resources (S750). In some embodiments, the device controller may determine the execution possibility of the command based on the state of device resources, the I/O type of the command, and the size of the command (S750). When it is determined that the command is executable (S750), the device controller fetches the command and puts it into a command processing pipeline (or command processing queue) to execute the command (S755). The device controller may fetch a command by moving a head pointer in the target submission queue (S755). Next, the device controller may check again whether the next command exists in the target submission queue (S740).

When it is determined that the command is not executable (S750), the device controller may display the target submission queue as a resource standby state (S760), and check whether an available submission queue exists (S730). In some embodiments, the resource waiting state may include information indicating a waiting resource. The information indicating the standby resource may include, for example, at least one of the type of the standby resource or the amount of the standby resource.

If the command does not exist in the target submission queue (S740), the device controller may select the next target submission queue from available submission queues (S730 and S735), and repeat the operations described with reference to S740 to S760.

In some embodiments, in order to process the submission queue indicated as a waiting state, the device controller may check whether a submission queue designated as a waiting state exists (S710). If the submission queue designated as a standby state does not exist (S710), the device controller may select a target submission queue from available submission queues (S730 and S735), and repeat the operations described with reference to S740 to S760.

If there is a submission queue designated as a standby state (S710), the device controller may select a submission queue from among submission queues designated as a standby state (S715). The device controller may determine whether the waiting state of the selected submission queue can be released based on the state of the device resource (S720). In some embodiments, the device controller may determine whether the waiting state of the selected submission queue can be released based on information on the state of the device resource and the waiting state (S720). For example, if resources corresponding to the type of waiting resource and the amount of waiting resources are available in the device resource, the device controller may release the waiting state of the selected submission queue. If the waiting state cannot be released, the device controller may check whether a submission queue designated as waiting state additionally exists (S710).

If the waiting state can be released, the device controller can add the selected submission queue to the list of available submission queues (S725). In some embodiments, the device controller may add to the head of a list of available submission queues such that the selected submission queue is selected first according to the arbitration mechanism. Next, the device controller may check whether there is an additional submission queue displayed in a standby state (S710), and may repeat the operation described with reference to S715 to S725 or the operation described with reference to S730 to S760.

Next, an embodiment in which an address conversion resource is used as a shared resource will be described with reference to FIG. 8 .

8 is an exemplary block diagram of a device controller of a storage device according to another embodiment.

Referring to FIG. 8 , the device controller 800 may include an instruction fetch logic 810 , an instruction pre-processing logic 820 , a command processing logic 830 and an address conversion circuit 840 .

In some embodiments, the device controller 800 further includes a memory buffer 850, and the memory buffer 850 may include a plurality of submission queues 851, 852, ..., 85n. In some embodiments, a plurality of submission queues 851 - 85n may be formed in the host memory (eg, 112 of FIG. 1 ) of the host device.

The address translation circuit 840 may include an address translation cache 841 and control logic 842 . The address translation cache 841 has a plurality of entries, and each entry stores address translation data used when converting a virtual address to a physical address of the host memory (e.g., 112 in FIG. 1 or 212 in FIG. 2). can A virtual address can be an address referenced by the PRP or SGL of an instruction. Control logic 842 may check if the instruction (ie, the virtual address of the instruction) hits the address translation cache 841 . If the instruction is a hit, the control logic 842 can translate the instruction's virtual address to a physical address based on the hit entry. If an instruction misses in the address translation cache 841, the control logic 842 sends the physical address corresponding to the instruction's virtual address to the host device (e.g., 110 in FIG. 1 or 210 in FIG. 2). can request In some embodiments, control logic 842 may request a physical address via an address translation service (ATS)/page request interface (PRI).

The command fetch logic 810 may select a target submission queue 85i from the plurality of submission queues 851 - 85n and may pick a command from the selected submission queue 85i.

The instruction pre-processing logic 820 may determine an instruction's feasibility based on whether the peaked instruction is a hit in the address translation cache 841. If the instruction is a hit in the address translation cache 841, the instruction preprocessing logic 820 determines that the instruction is executable, fetches the instruction via the instruction fetch logic 810, and to the instruction processing logic 830. You can instruct the command to be executed. The command processing logic 830 may put the corresponding command into the command processing pipeline and convert the virtual address of the command to a physical address through the address conversion circuit 840 to execute the command. Even if the peaked instruction is a hit in the address translation cache 841, the instruction preprocessing logic 820 may determine that the instruction is not executable if other resources are insufficient to execute the peaked instruction.

If the peak command misses in the address translation cache 841, the control logic 842 of the address translation circuit 840 requests a physical address corresponding to the virtual address of the peak command to the host device, and the command pre-processing logic ( 820) may designate the submission queue 85i as a resource standby state. When the control logic 842 receives the physical address from the host device and the address translation cache 841 becomes available, the wait state of the submission queue 85i may be released and the command of the submission queue 85i may be executed.

FIG. 9 is a diagram illustrating a device controller of a storage device according to another embodiment, and FIG. 10 is a diagram illustrating an example of an operation of the device controller illustrated in FIG. 9 .

Referring to FIG. 9 , the device controller 900 includes a command fetch logic 910, a command preprocessing logic 920, a command processing logic 930, a device resource 940, and a pending command queue 960. can include

In some embodiments, the device controller 900 further includes a memory buffer 950, and the memory buffer 950 may include a plurality of submission queues 951, 952, ..., 95n. In some embodiments, a plurality of submission queues 951 - 95n may be formed in the host memory (eg, 112 of FIG. 1 ) of the host device.

In some embodiments, pending command queue 960 may include a pending read command queue 961 for storing non-executable read commands and a pending write command queue 962 for storing non-executable write commands. . In some embodiments, the size of the pending command queue may be set based on the arbitration burst size, the number of submit queues 951-95n, and the maximum number of commands that the device controller 900 can execute concurrently.

Instruction fetch logic 910 may pick an instruction from submit queue 95i. When peaking an instruction from submit queue 95i, instruction fetch logic 910 may not move the head pointer of submit queue 95i. In some embodiments, the command fetch logic 910 may select a target submit queue 95i from the plurality of submit queues 951 - 95n and pick a command from the selected submit queue 95i.

Command pre-processing logic 920 may determine the feasibility of the peak command based on the state of device resources 940 . In some embodiments, device resources 940 may include read resources 941 for processing read commands and write resources 942 for processing write commands. The device resource 940 may further include a shared resource 943 shared by a read command and a write command.

When the command pre-processing logic 920 determines that the peak command is executable, the command fetch logic 910 fetches the command and commands the command processing logic 930 to execute the fetched command. Instruction fetch logic 910 may fetch an instruction from submit queue 95i by moving the head pointer of submit queue 95i. The command processing logic 930 may allocate device resources 940 to the fetched command and execute the fetched command. If it is determined that the peaked instruction is not executable, the instruction preprocessing logic 920 may place the non-executable instruction into the pending instruction queue 960 without allocating resources and fetch the instruction through the instruction fetch logic 910. there is. That is, as it moves a non-executable instruction to the pending instruction queue 960, the instruction fetch logic 910 can move the head pointer in the submit queue 95i.

In some embodiments, if command preprocessing logic 920 determines that some of the peaked commands are executable and some others are not, it instructs command processing logic 930 to execute the executable commands and executes them. Commands that are not available may be put into the pending command queue 960 . For example, if the command that command fetch logic 910 peaked in submit queue 95i includes a read command and a write command, and read resource 941 is available but write resource 942 is exhausted, the command The preprocessing logic 920 puts the write command into the pending write command queue 962, and the command processing logic 930 can execute the read command. If the pending command queue 960 is full, the command preprocessing logic 920 may drop the peaked command instead of putting it into the pending command queue 960 . In some embodiments, upon dropping a peak command, the command pre-processing logic 920 may place the submit queue 95i in a wait-for-resource state, as described with reference to FIGS. 3-8.

After processing the target submission queue 95i, the device controller 900 selects the next target submission queue 95j from the plurality of submission queues 951 to 95n, fetches an instruction from the selected submission queue 95j, and fetches The process of determining whether a command is executable can be repeated.

In some embodiments, command preprocessing logic 920 monitors the status of device resources 940 and, if resources for executing commands stored in command pending queue 960 become available, command pending queue 960 ), and instructs the command processing logic 930 to execute the corresponding command. In some embodiments, command pre-processing logic 920 may peak commands stored in command pending queue 960 and determine whether the peaked command is executable.

For example, as shown in FIG. 10, two write commands (W0, W1) and one read command (R0) are input to the submission queue (SQ1), and one read command (R1) is input to the submission queue (SQ2). ) and two write commands (W2, W3) are input, two write commands (W4, W5) and one read command (R2) are input to the submit queue (SQ3), and the submit queue (SQ1, SQ2, SQ3) ), the head pointer points to the first entry, and the arbitration burst is assumed to be 3. Also, it is assumed that the write resource 942 among the device resources 940 is exhausted and unavailable.

The instruction fetch logic 910 may select a target submission queue SQ1 from among the plurality of submission queues SQ1 , SQ2 , and SQ3 and fetch instructions W0 , W1 , and R0 from the submission queue SQ1 . Since the write resource 942 is not available, the command preprocessing logic 920 may put the write commands W0 and W1 into the pending write command queue 962 . Also, since the read resource 941 and the shared resource 943 are available, the command preprocessing logic 920 instructs the command processing logic 930 to execute the read command R0, and the command processing logic 930 Read command (R0) can be executed.

The instruction fetch logic 910 may select the next target submit queue SQ2 and fetch instructions R1, W2, and W3 from submit queue SQ2. The command pre-processing logic 920 instructs the command processing logic 930 to execute the read command R1, and the command processing logic 930 may execute the read command R1. Also, since the write resource 942 is not available, the command preprocessing logic 920 may put the write commands W2 and W3 into the pending write command queue 962 .

The instruction fetch logic 910 may select the next target submit queue SQ3 and fetch instructions W4, W5, and R2 from submit queue SQ3. Since the write resource 942 is not available, the command preprocessing logic 920 puts the write commands W4 and W5 into the pending write command queue 962 and sends the read command R2 to the command processing logic 930. You can instruct what to do.

When write resources 942 become available, command preprocessing logic 920 fetches write commands W0-W5 from pending write command queue 962 and write commands W0 to command processing logic 930. -W5) can be instructed to run.

11 is a flowchart illustrating an operation of a device controller of a storage device according to another embodiment.

Referring to FIG. 11 , when there are available submission queues (S1130), the device controller may select a target submission queue from the available submission queues (S1135). If there is no usable submission queue (S1130), the device controller may end the operation. When a command exists in the target submission queue (S1140), the device controller may pick the next command from the target submission queue (S1145). The device controller may pick a command from the target submission queue and maintain the head pointer without moving (S1145).

The device controller may determine the execution possibility of the peak command based on the information including the state of the device resource (S1150). If there is an executable command among the peaked commands (S1150), the device controller may fetch the corresponding command and put it into a command processing pipeline (or command processing queue) to execute the command (S1155). The device controller may fetch a command by moving a head pointer in the target submission queue (S1155). If there is a non-executable command among the fetched commands (S1150), the device controller may put the non-executable command into the pending command queue (S1160). In some embodiments, the device controller may put an unexecutable command into a pending command queue and fetch the corresponding command from a submission queue (S1160). The device controller may fetch a command by moving a head pointer in the target submission queue (S1160).

The device controller may check whether the next command exists in the target submission queue (S1140). When the next command exists in the target submission queue (S1140), the device controller may repeat the operations described with reference to S1145 to S1160.

If there is no command in the target submission queue (S1140), the device controller may select the next target submission queue from available submission queues (S1130 and S1135), and repeat the operations described with reference to S1140 to S1160.

In some embodiments, in order to process the pending command queue, the device controller may check whether a command exists in the pending command queue (S1110). When no command exists in the pending command queue (S1110), the device controller may select a target submission queue from available submission queues (S1130 and S1135), and repeat the operations described with reference to S1140 to S1160.

When a command exists in the pending command queue (S1110), the device controller may determine whether the command in the pending command queue can be executed (S1120). In some embodiments, the device controller may determine whether the command of the pending command queue can be executed based on the state of the device resource and the I/O type of the pending command queue (S1120). For example, the device controller may determine that a command in the pending read command queue can be executed if shared and read resources are available, and a command in the pending write command queue can be executed if shared and write resources are available. can If the command of the pending command queue can be executed, the device controller can fetch and execute the command of the pending command queue (S1125).

When the command of the pending command queue cannot be executed (S1120), the device controller may select a target submission queue from available submission queues (S1130 and S1135), and repeat the operations described with reference to S1140 to S1160.

FIG. 12 is a diagram illustrating a device controller of a storage device according to another embodiment, and FIG. 13 is a diagram illustrating an example of an operation of the device controller illustrated in FIG. 12 .

Referring to FIG. 12 , the device controller 1200 may include an instruction fetch logic 1210, an instruction pre-processing logic 1220, a command processing logic 1230, and a device resource 1240.

In some embodiments, the device controller 1200 further includes a memory buffer 1250, and the memory buffer 1250 may include a plurality of submission queues 1251, 1252, ..., 125n. In some embodiments, a plurality of submission queues 1251 - 125n may be formed in a host memory (eg, 112 of FIG. 1 ) of the host device.

The instruction fetch logic 1210 may pick an instruction from the submit queue 125i. When peaking an instruction from submit queue 125i, the instruction fetch logic 1210 may not move the head pointer of submit queue 125i. In some embodiments, the command fetch logic 1210 may select a target submit queue 125i from the plurality of submit queues 125i-125n and pick a command from the selected submit queue 125i.

Command preprocessing logic 1220 may determine the feasibility of the peak command based on the state of device resources 1240 . In some embodiments, device resources 1240 may include read resources 1241 for processing read commands and write resources 1242 for processing write commands. The device resource 1240 may further include a shared resource 1243 shared by a read command and a write command.

When the command preprocessing logic 1220 determines that the peaked command is executable, it may instruct the command processing logic 1230 to fetch the peaked command and execute the fetched command. Instruction fetch logic 1210 may fetch an instruction from submit queue 125i by moving the head pointer of submit queue 125i. The command processing logic 1230 may allocate device resources 1240 to the fetched command and execute the fetched command. In some embodiments, if it determines that the peaked instruction is not executable, the instruction preprocessing logic 1220 instructs the instruction fetch logic 1210 to push the non-executable instruction back to the submit queue 125i. can do. In some embodiments, instruction fetch logic 1210 may manipulate the head pointer of submit queue 125i to pack non-executable instructions in submit queue 125i. Accordingly, out of order command processing may be performed in the submission queue 125i.

In some embodiments, instruction fetch logic 1210 may sequentially peak instructions from head to tail of submit queue 125i, and instruction preprocessing logic 1220 may determine whether the peaked instruction is executable. If it is determined that some of the peaked commands are executable and some of the others are not, the command preprocessing logic 1220 instructs the command processing logic 1230 to execute the executable commands, and rejects the non-executable commands. You can pack again in the submit queue 125i. If the commands that the command fetch logic 1210 has peaked in the submit queue 125i include a read command and a write command, and the read resource 1241 is available but the write resource 1242 is exhausted, the command processing logic 1230 ) can execute the read command. The instruction fetch logic 1210 may move the head pointer of the submission queue 125i by the number of fetched read instructions, and may pack write instructions from the head entry indicated by the moved head pointer.

In some embodiments, when submit queue 125i is formed in host memory 112, command fetch logic 1210 requests write access to submit queue 125i from the host device, and after receiving write access from the host device, The commands in the submit queue 125i may be packed.

In some embodiments, the command preprocessing logic 1220 may place the command-packed submit queue 125i in a wait-for-resource state, as described with reference to FIGS. 3-7. In some embodiments, command preprocessing logic 1220 may indicate resource information that packed submit queue 125i awaits. The resource information may include, for example, at least one of the type of standby resource or the amount of standby resource.

As shown in FIG. 13, for example, a write command (W0, W1), a read command (R0), a write command (W2), a read command (R1), and a write command (W3) are sequentially sent to the submission queue (SQ). Assume that the command is entered. Also, it is assumed that the write resource 1242 among the device resources 1240 is exhausted and unavailable.

The instruction fetch logic 1210 sequentially picks instructions from the submission queue SQ, and since the read resource 1241 and the shared resource 1243 are available, read instructions R0 and R1 can be fetched. The command processing logic 1230 may allocate resources and execute the fetched read commands R0 and R1. Also, since the instruction fetch logic 1210 has fetched two read instructions (R0 and R1), it moves the head pointer of the submit queue (SQ) from h to (h-2), and the head pointer (h-2) is Write commands (W0, W1, W2, W3) may be packed again from the entry of the indicated submission queue (SQ).

In some embodiments, the command preprocessing logic 1220 may monitor the state of the device resources 1240 and see if the resources of the submit queue 125i where the commands are packed back become available. If the resource is made available, command preprocessing logic 1220 may designate submit queue 125i as an available submit queue. Accordingly, as described above, an operation of determining whether a command is executable by peaking a command in the submission queue 125i may be performed. In some embodiments, when resources become available, command preprocessing logic 1220 may preferentially process submit queue 125i in which commands are repacked over other submit queues. For example, command preprocessing logic 1220 may add submit queue 125i with the command repacked to the head of the list of available submit queues.

In some embodiments, command preprocessing logic 1220, after processing the command in submission queue 125i, selects the next target submission queue 125j from the plurality of submission queues 1251-125n, and selects the selected submission queue 125j. ) and repeat the process of determining whether the peaked command is executable.

14 is a flowchart illustrating an operation of a device controller of a storage device according to another embodiment.

Referring to FIG. 14 , when there is an available submission queue (S1430), the device controller may select a target submission queue from the available submission queues (S1435). If there is no usable submission queue (S1430), the device controller may end the operation. If a command exists in the target submission queue (S1440), the device controller may pick the next command from the target submission queue (S1445). The device controller may pick a command from the target submission queue and maintain the head pointer without moving (S1445).

The device controller may determine the possibility of executing the peak command based on the information including the state of the device resource (S1450). If it is determined that the peaked command is not executable (S1450), the device controller may check again whether the next command exists in the target submission queue (S1440). When it is determined that the peak command is executable (S1450), the device controller fetches the command, puts it into a command processing pipeline (or command processing queue), and executes the command (S1455). Next, the device controller may check again whether the next command exists in the target submission queue (S1440).

After peaking to the tail of the target submission queue (S1440), the device controller may check whether there is a command that is not executable in the target submission queue (S1460). If there is no non-executable command, the device controller may select a next target submission queue from available submission queues (S1430 and S1435). If the non-executable command exists, the device controller may pack the non-executable command in the target submission queue (S1465). The device controller may move the head pointer of the target submission queue by the number of fetched instructions, and may pack non-executable instructions from the head entry indicated by the moved head pointer. In some embodiments, the device controller may mark the packed submission queue as a resource-waiting submission queue. Next, the device controller may select the next target submission queue from available submission queues (S1430 and S1435), and repeat the operations described with reference to S1440 to S1465.

In some embodiments, in order to preferentially process the packed submission queue, the device controller may check whether the packed submission queue exists (S1410). In some embodiments, the device controller may check whether a submission queue in a resource standby state exists (S1410). If the packed submission queue does not exist (S1410), the device controller may select a submission queue from available submission queues (S1430 and S1435), and repeat the operations described with reference to S1440 to S1465.

If a packed submission queue exists (S1410), the device controller may select a submission queue from among the packed submission queues (S1415). The device controller may determine whether the selected submission queue can be processed based on the state of the device resource (S1420). In some embodiments, the device controller may determine whether the selected submission queue can be processed based on the state of the device resource and information on the resource in which the selected submission queue waits (S1420). For example, if resources corresponding to the type and amount of waiting resources are available in the device resource, the device controller may determine that the selected submission queue can be processed. If the selected submission queue cannot be processed, the device controller may check whether a packed submission queue additionally exists (S1410).

If the selected submission queue can be processed, the device controller can add the selected submission queue to the list of available submission queues (S1425). In some embodiments, the device controller may add to the head of a list of available submission queues such that the selected submission queue may be selected first according to the arbitration mechanism. If the selected submission queue cannot be processed, the device controller checks whether there are additional packed submission queues (S1410), and repeats the operation described with reference to S1415 to S1425 or the operation described with reference to S1430 to S1465. can

15 is an example block diagram illustrating a computer system according to one embodiment.

Referring to FIG. 15 , a computing device 1500 includes a processor 1510, a memory 1520, a memory controller 1530, a storage device 1540, a communication interface 1550, and a bus 1560. The computing device 1500 may further include other general-purpose components.

The processor 1510 controls the overall operation of each component of the computing device 1500 . The processor 1510 may be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), and a graphic processing unit (GPU).

The memory 1520 stores various data and commands. Memory controller 1530 controls the transfer of data or commands to and from memory 1520 . In some embodiments, the memory controller 1530 may be provided as a separate chip from the processor 1510 . In some embodiments, the memory controller 1530 may be provided as an internal component of the processor 1510 .

The storage device 1540 non-temporarily stores programs and data. In some embodiments, the storage device 1540 may be implemented as the storage device described with reference to FIGS. 1 to 14 . The communication interface 1550 supports wired and wireless Internet communication of the computing device 1500 . Also, the communication interface 1550 may support various communication methods other than Internet communication. The bus 1560 provides a communication function between components of the computing device 1500 . The bus 1560 may include at least one type of bus according to a communication protocol between components.

In some embodiments, each logic or combination of two or more logics described with reference to FIGS. 1-14 may be a digital circuit, programmable or non-programmable logic device or array, application specific integrated circuit (ASIC) ) and the like can be implemented.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims are also included in the scope of the present invention. that fall within the scope of the right.

Claims (20)

As a device controller of a storage device including a non-volatile memory,
device resource,
instruction fetch logic that peeks a first command from a first submit queue among a plurality of submit queues and fetches the first command in response to determining that the first command is executable;
instruction pre-processing logic to determine whether the first instruction peaked in the instruction fetch logic is executable based on the state of the device resource; and
In response to determining that the first command is executable, command processing logic to allocate device resources to the first command fetched by the command fetch logic and execute the first command;
the command fetch logic picks a second command from a second submit queue of the plurality of submit queues;
The command pre-processing logic determines whether the second command is executable based on the state of the device resource, and in response to determining that the second command is not executable, sets the second submit queue to wait for the device resource. state
device controller. In paragraph 1,
and wherein the instruction fetch logic moves the head pointer of the first submission queue to fetch the first instruction at a peak of the first instruction, without moving the head pointer of the first submission queue. delete In paragraph 1,
and wherein the command fetch logic drops the second command rather than fetch it in response to determining that the second command is not executable. In paragraph 1,
The command pre-processing logic determines whether the second submission queue designated as the waiting state can be processed based on the state of the device resource;
In response to determining that the second submit queue is processable, the command fetch logic picks the second command from the second submit queue, and the command preprocessing logic determines whether the second command is executable.
device controller. In paragraph 5,
wherein the command pre-processing logic determines that the second submission queue is processable when a resource in which the second command waits is available among the device resources. In paragraph 6,
wherein the command pre-processing logic preferentially processes the second submission queue over the remaining submission queues of the plurality of submission queues. As a device controller of a storage device including a non-volatile memory,
device resource,
instruction fetch logic that picks a first command and a second command from a first submit queue among the plurality of submit queues;
instruction preprocessing logic to determine whether the first instruction and the second instruction peaked in the instruction fetch logic are executable based on the state of the device resource;
command processing logic, and
contains a queue of pending commands;
In response to the instruction pre-processing logic determining that the first instruction is executable and the second instruction not executable, the instruction fetch logic fetches the first instruction and the second instruction, wherein the instruction pre-processing logic storing the second command in the pending command queue;
In response to determining that the first command is executable, the command processing logic allocates device resources to the first command fetched by the instruction fetch logic and executes the first command.
device controller. In paragraph 8,
the command preprocessing logic determines whether a third command stored in the pending command queue is executable based on the state of the device resource;
In response to determining that the third command in the pending command queue is executable, the command processing logic executes the third command in the pending command queue.
device controller. In paragraph 9,
and the command pre-processing logic preferentially processes the pending command queue over the plurality of submission queues. As a device controller of a storage device including a non-volatile memory,
device resource,
instruction fetch logic that picks a first command and a second command from a first submit queue among the plurality of submit queues;
instruction preprocessing logic for determining whether the first instruction and the second instruction peaked in the instruction fetch logic are executable based on the state of the device resource; and
Contains command processing logic;
In response to the command preprocessing logic determining that the first command is executable and the second command is not executable, the command fetch logic fetches the first command from the first submit queue, and the second command Packing in the first submission queue;
In response to determining that the first command is executable, the command processing logic allocates device resources to the first command fetched by the instruction fetch logic and executes the first command.
device controller. In paragraph 11,
wherein the instruction fetch logic moves a head pointer of the first submit queue by the number of the first instructions, and packs the second instruction from an entry to which the head pointer is moved. In paragraph 11,
the command preprocessing logic determines whether the packed first submit queue is processable based on the state of the device resource;
In response to determining that the first submit queue is processable, the command fetch logic picks the second command from the first submit queue, and the command preprocessing logic determines whether the second command is executable.
device controller. In paragraph 13,
If a resource for waiting the second command is available among the device resources, the command pre-processing logic prioritizes processing the first submission queue over other submission queues among the plurality of submission queues. In paragraph 1,
wherein the command pre-processing logic determines that the first command is executable when a resource for executing the first command is available among the device resources, and fetches the first command. In paragraph 15,
The device resource includes a read resource dedicated to a read command, a write resource dedicated to a write command, and a shared resource shared by the read command and the write command,
The command pre-processing logic determines that a resource for executing the first command is available when a resource corresponding to the input/output type of the first command and the shared resource among the read resource and the write resource are available, fetching the first instruction
device controller. In clause 15,
the device resource includes a plurality of types of resources used to execute the first command;
The command pre-processing logic determines that resources for executing the first command are not available when some types of resources among the plurality of types of resources are not available.
device controller. In paragraph 15,
and the command pre-processing logic does not allocate the device resource to the first command if a resource for executing the first command is not available among the device resources. non-volatile memory; and
Controls access to the non-volatile memory, retrieves a first command from a first submission queue of a plurality of submission queues without moving a head pointer of the first submission queue, and retrieves the first command based on a state of a device resource. a device controller that determines whether the command is executable and moves the head pointer of the first submission queue in response to determining that the first command is executable;
The device controller fetches a second command from a second submission queue of the plurality of submission queues without moving the head pointer of the second submission queue, and determines whether the second command is executable based on the state of the device resource. and, in response to determining that the second command is not executable, designating the second submit queue in a standby state to wait for the device resource.
storage device. A method executed by a storage device comprising a non-volatile memory, comprising:
picking a first command from a first submission queue of the plurality of submission queues;
determining whether the first command is executable based on a state of device resources;
fetching the first command in response to determining that the first command is executable;
in response to determining that the first command is executable, allocating device resources to the first command and executing a second command;
picking a second command from a second submission queue of the plurality of submission queues;
determining whether the second command is executable based on the state of the device resource; and
designating the second submit queue in a standby state to wait for the device resource in response to determining that the second command is not executable;
How to include.

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