KR102557751B1 - Single polarity dynamic logic circuit - Google Patents

Abstract

A single polarity dynamic logic circuit according to an embodiment includes a first stage receiving a first clock signal, a second clock signal, and an input signal, a second stage receiving the second clock signal, the third clock signal, and an output signal of the first stage, and a third stage receiving the third clock signal, the first clock signal, and the output signal of the second stage, wherein the first clock signal, the second clock signal, and the third clock signal are 3 minutes It may be a phase signal including phase signals of different ranges.

Description

Single polarity dynamic logic circuit {Single polarity dynamic logic circuit}

The present invention relates to a single-polarity dynamic logic circuit, and more particularly, to a technique capable of solving a voltage racing problem generated at an output terminal of a dynamic logic circuit by differentiating the type of signal input to the dynamic logic circuit.

As the demand for high-speed operation performance of mobile CPUs gradually increases, the importance of logic gates employed to perform logic operations within the CPU is gradually increasing.

A logic circuit is generally implemented using both a P-channel metal oxide semiconductor (PMOS) and an N-channel metal oxide semiconductor (NMOS) in a complementary metal-oxide semiconductor (CMOS). When a logic circuit is implemented using a single polarity using only NMOS or PMOS, it is generally implemented as a static logic circuit, which is also referred to as a static logic circuit.

Specifically, a static logic circuit is a circuit that can perform a static operation like a normal bipolar IC gate in a MOS gate. In a typical circuit design method using a static logic gate, a stable circuit with high noise resistance can be implemented, and static timing analysis (STA) can also be performed relatively easily. However, there are disadvantages in that the number of inputs that can be received in one stage is limited to several or less, and the overall operation speed is slowed down due to the increase in the number of stacks in the circuit.

In addition, in implementing a static logic circuit, in the case of implementing a uni-polar logic circuit using only NMOS or PMOS, static current is generated because the pull-up transistor is a diode-connection, the dynamic range of the current is narrow, and the circuit area is large.

In order to solve these disadvantages, a dynamic logic circuit has been proposed. A dynamic logic circuit is a circuit that uses logic itself as a medium, in which the logic itself can be modified and applied whenever necessary as a parameter, rather than specifying the flow of data as a single one. It is generally implemented to perform a sampling operation using a clock using the gate capacitance inherent in the MOS device.

On the other hand, among circuit design methods using dynamic logic gates, dynamic logic gates in the form of domino gates, which are commonly used to improve operating speed, are vulnerable to leakage or input noise. When an existing structure is used to implement a domino gate, the voltage at the output stage cannot remain high in a section where it must remain high, and a racing phenomenon occurs, resulting in complex logic gating. Therefore, a digital logic circuit capable of performing logic gating at high speed is required.

Republic of Korea Patent Publication No. 10-2015-0083769 - Low-power toggle latch-based flip-flop circuit including integrated clock gating logic (published on July 20, 2015) Republic of Korea Patent Publication No. 10-2015-0016908 - Flip-flop circuit for zero-delay bypass multiplexer insertion and its operation method (published on Feb. 13, 2015)

A single polarity dynamic logic circuit according to an embodiment is an invention designed to solve the above-described problems, and in designing a digital logic circuit, a single polarity dynamic logic circuit in which the voltage of the output terminal can be stably output as designed. Its purpose is to provide.

More specifically, the single-polarity dynamic logic circuit according to an embodiment, unlike the prior art, in configuring a clock signal, adds a clock signal that can serve as a hold phase as an input signal, so that the operation of the previous stage does not reach the operation of the next stage. Its purpose is to provide a logic circuit that solves the problem of racing of the output stage voltage generated in the single-polarity dynamic logic circuit according to the prior art.

A single polarity dynamic logic circuit according to an embodiment includes a first stage receiving a first clock signal, a second clock signal, and an input signal, a second stage receiving the second clock signal, the third clock signal, and an output signal of the first stage, and a third stage receiving the third clock signal, the first clock signal, and the output signal of the second stage, wherein the first clock signal, the second clock signal, and the third clock signal are 3 minutes It may be a phase signal including phase signals of different ranges.

A fourth stage receiving the first clock signal, the second clock signal, and the output signal of the third stage may be further included.

The phase range of the first clock signal includes a range of 0 degrees to 120 degrees,

The phase range of the second clock signal may include a range of 120 degrees to 240 degrees, and the phase range of the third clock signal may include a range of 240 degrees to 360 degrees.

When the first stage is in an evaluation phase, the second stage may be in a pre-charge phase, and the third stage may be in a hold phase.

When the phase signal of the first stage is in a hold phase, the second stage is in an evaluation phase, and the third stage is in a pre-charge phase. It may be in a phase.

When the first stage is in a pre-charge phase, the second stage may be in a hold phase, and the third stage may be in an evaluation phase.

The first stage includes a first transistor that pre-charges a first dynamic node in response to the first clock signal, the second stage includes a second transistor that pre-charges a second dynamic node in response to the second clock signal, the third stage includes a third transistor that pre-charges a third dynamic node in response to the third clock signal, and the fourth stage includes , a fourth transistor for precharging a fourth dynamic node in response to the first clock signal.

The first stage includes a fifth transistor that performs an evaluation operation or a hold operation in response to the second clock signal, the second stage includes a sixth transistor that performs an evaluation operation or a hold operation in response to the third clock signal, and the third stage includes a seventh transistor that performs an evaluation operation or a hold operation in response to the first clock signal , The fourth stage may perform an evaluation operation or a hold operation in response to the second clock signal.

The first stage may include a ninth transistor that receives an input signal including input data, the second stage may include a tenth transistor that receives an output signal of the first stage, the third stage may include an eleventh transistor that receives an output signal of the second stage, and the fourth stage may include a twelfth transistor that receives an output signal of the third stage.

Each of the first stage, the second stage, the third stage, and the fourth stage may be implemented as an inverter.

A single polarity dynamic logic circuit according to another embodiment includes a first stage receiving a first PC signal, a first EV signal and an input signal, a second stage receiving a second PC signal, a second EV signal and an output signal of the first stage, a third stage receiving a third PC signal, a third EV signal and an output signal of the second stage, and a fourth stage receiving a fourth PC signal, a fourth EV signal and an output signal of the third stage, and The 1 EV signal may have opposite phases to each other, the 2 PC signal and the 2 EV signal may have opposite phases to each other, the 3 PC signal and the 3 EV signal may have opposite phases to each other, and the 4 PC signal and the 4 EV signal may have opposite phases to each other.

The 2PC signal to the 4PC signal may have signals sequentially delayed by a preset phase based on the 1PC signal, and the 2EV signal to 4EV signals may have signals sequentially delayed by a preset phase based on the 1PC signal.

A single polarity dynamic logic circuit according to another embodiment includes a first stage receiving a first clock signal, a second clock signal, and an input signal, a second stage receiving the second clock signal, the third clock signal, and the output signal of the first stage, a third stage receiving the third clock signal, the first clock signal, and the output signal of the second stage, and a stage receiving the first clock signal, the second clock signal, and the output signal of the third stage. The first clock signal, the second clock signal, and the third clock signal may include 4 stages, wherein the first stage includes a first inverter and a second inverter connected in parallel, and the fourth stage is implemented as a third inverter.

The second stage may be implemented with NAND gates and the third stage may be implemented with NOR gates, or the second stage may be implemented with NOR gates and the third stage may be implemented with NOR gates.

The second stage may be implemented with a first NAND gate and the third stage may be implemented with a second NAND gate, or the second stage may be implemented with a first NOR gate and the third stage may be implemented with a second NOR gate.

In the single-polarity dynamic logic circuit according to an embodiment, since the third clock signal, which can serve as a hold unlike in the prior art, is additionally utilized as an input signal, the problem of each stage performing an operation in the same phase can be prevented, and the circuit can be stably driven.

And, accordingly, the calculation result of the [N-1] stage does not affect the calculation result of the [N] stage, so there is an effect of preventing the racing problem of the output stage voltage, which inevitably occurred in the single polarity dynamic logic circuit according to the prior art.

1(a) is a circuit diagram showing components of a single polarity dynamic logic circuit according to an embodiment of the present invention, and FIG. 1(b) is a diagram showing waveforms of clock signals input to a single polarity dynamic logic circuit according to an embodiment of the present invention.
2 is a diagram illustrating several embodiments of clock signals that may be input to the single polarity dynamic logic circuit of the present invention.
3 is a diagram for explaining an operation flow of a single polarity dynamic logic circuit according to an embodiment of the present invention.
Figure 4 (a) is a diagram showing output waveforms when a single polarity dynamic logic circuit is implemented based on a first clock signal, a second clock signal and an input signal according to the prior art, and FIG.
5 is a circuit diagram illustrating components of a single polarity dynamic logic circuit according to another embodiment.
FIG. 6 is a diagram illustrating waveforms of signals input to the single-polarity dynamic logic circuit of FIG. 5 .
7 and 8 are diagrams showing a circuit diagram of a single-polarity dynamic logic circuit implemented using a NAND gate according to another embodiment of the present invention, an operation process accordingly, and measurement experiment results.
9 and 10 are diagrams showing a circuit diagram of a single polarity dynamic logic circuit implemented using a NOR gate according to another embodiment of the present invention, and calculation processes and measurement experiment results accordingly.
11 and 12 are diagrams showing a circuit diagram of a single polarity dynamic logic circuit implemented by sequentially using a NAND gate and a NOR gate according to another embodiment of the present invention, and an operation process and measurement experiment results accordingly.
13 and 14 are diagrams showing a circuit diagram of a single-polarity dynamic logic circuit implemented by sequentially using a NOR gate and a NAND gate according to another embodiment of the present invention, and calculation processes and measurement experiment results accordingly.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings. In adding reference numerals to the components of each drawing, it should be noted that the same components have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing an embodiment of the present invention, if it is determined that a detailed description of a related known configuration or function hinders understanding of the embodiment of the present invention, the detailed description thereof will be omitted. In addition, embodiments of the present invention will be described below, but the technical idea of the present invention is not limited or limited thereto and can be modified and implemented in various ways by those skilled in the art.

In addition, terms used in this specification are used to describe embodiments, and are not intended to limit and/or limit the disclosed invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

In this specification, terms such as "comprise", "comprise" or "have" are intended to specify that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but does not preclude the existence or addition of one or more other features or numbers, steps, operations, components, parts, or combinations thereof.

In addition, throughout the specification, when a part is said to be “connected” to another part, this includes not only the case where it is “directly connected” but also the case where it is “indirectly connected” with another element interposed therebetween, and terms including ordinal numbers such as “first” and “second” used herein may be used to describe various components, but the components are not limited by these terms.

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention.

1(a) is a circuit diagram showing components of a single polarity dynamic logic circuit according to an embodiment of the present invention, and FIG. 1(b) is a diagram showing waveforms of clock signals input to a single polarity dynamic logic circuit according to an embodiment of the present invention. 2 is a diagram showing several embodiments of clock signals that can be input to the single polarity dynamic logic circuit of the present invention, FIG. 3 is a diagram for explaining the operation flow of the single polarity dynamic logic circuit according to an embodiment of the present invention, FIG. Accordingly, it is a diagram showing output waveforms when a single polarity dynamic logic circuit is implemented based on the first clock signal, the second clock signal, the third clock signal, and the input signal.

Referring to FIG. 1 , a single polarity dynamic logic circuit 100 according to an embodiment may include four stages connected in parallel in a cascode form. Specifically, a first stage 10 receiving a first clock signal CK1, a second clock signal CK2, and an input signal IN, a second stage 10 receiving a second clock signal CK2, a third clock signal CK3, and an output signal of the first stage 10. It may include a third stage 30 that receives the second stage 20, the third clock signal CK3, the first clock signal CK1, and the output signals of the second stage 20, and the fourth stage 40 that receives the first clock signal CK1, the second clock signal CK2, and the output signals of the third stage 30, and outputs a final output voltage. As an embodiment, in the single polarity dynamic logic circuit 100 shown in FIG. 1, the first stage 10 is a first inverter, the second stage 20 is a second inverter, the third stage 30 is a third inverter, and the fourth stage 40 can be implemented as a fourth inverter.

Specifically, the first stage 10 includes a first transistor M1 that pre-charges the first dynamic node O1 in response to the first clock signal CK1, a second transistor M2 that performs an evaluation operation or a phase hold operation in response to the second clock signal CK2, and a third transistor that receives a data input signal IN including input data. (M3), and the first transistor (M1), the second transistor (M2) and the third transistor (M3) may be sequentially connected in series as shown in the figure.

The second stage 20 may include a fourth transistor M4 precharging the second dynamic node O2 in response to the second clock signal CK2, a fifth transistor M5 performing an evaluation operation or a hold phase operation in response to the third clock signal CK3, and a sixth transistor M6 receiving the output signal of the first stage 10 as an input signal. The transistor M4, the fifth transistor M5, and the sixth transistor M6 may be sequentially connected in series as shown in the drawing.

The third stage 30 may include a seventh transistor M7 that precharges the third dynamic node O3 in response to the third clock signal CK3, an eighth transistor M8 that performs an evaluation operation or a hold phase operation in response to the first clock signal CK1, and a ninth transistor M9 that receives the output signal of the second stage 20 as an input signal. The transistor M7, the eighth transistor M8, and the ninth transistor M9 may be sequentially connected in series as shown in the drawing.

The fourth stage 40 uses the output signals of the tenth transistor M10 precharging the fourth dynamic node O4 corresponding to the output node of the single polarity dynamic logic circuit 100 in response to the first clock signal CK1, the eleventh transistor M11 performing an evaluation operation or hold phase operation in response to the second clock signal CK2, and the third stage 30 as input signals. It may include a twelfth transistor M12 receiving an input to , and the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 may be sequentially connected in series as shown in the figure.

For convenience of description below, positions where the first transistor (M1), fourth transistor (M4), seventh transistor (M7), and tenth transistor (M10) are disposed are referred to as an upper layer, and positions where the second transistor (M2), fifth transistor (M5), eighth transistor (M8), and eleventh transistor (M11) are disposed are referred to as a middle layer and a third transistor (M3). , The position where the sixth transistor M6, the ninth transistor M9, and the twelfth transistor M12 are disposed is referred to as a lower layer and will be described.

The first transistor (M1), the fourth transistor (M4), the seventh transistor (M7), and the tenth transistor (M10) on the upper layer of each stage are transistors serving as pull-up transistors in each stage, and can pre-charge the voltage of the output node for each stage. That is, the first transistor M1 may pre-charge the first dynamometer node O1 corresponding to the output node of the first stage 10 in response to the first clock signal CK1 input to the first transistor M1.

The second transistor (M2), the fifth transistor (M5), the eighth transistor (M8), and the eleventh transistor (M11) in the middle layer of each stage are transistors serving as pull-down transistors in each stage, and may perform an evaluation or a phase hold operation based on a signal input for each stage.

The third transistor (M3), sixth transistor (M6), ninth transistor (M9), and twelfth transistor (M12) in the lower layer of each stage are input transistors that receive input signals. The third transistor (M3) receives the data input signal (IN) input to the single polarity dynamic logic circuit (100), and the sixth transistor (M6) receives the signal output from the first stage (10). is input as the input signal of the second stage 20, the ninth transistor M9 receives the signal output from the second stage 20 as the input signal of the third stage 30, and the twelfth transistor M12 receives the signal output from the third stage 30 as the input signal of the fourth stage 40.

Based on FIG. 1, the second transistor (M2), the fifth transistor (M5), the eighth transistor (M8), and the eleventh transistor (M11) performing an evaluation or hold operation are shown as being in the middle layer of each stage, but in an embodiment of the present invention, the second transistor (M2), the fifth transistor (M5), and the eighth transistor (M 8) and the 11th transistor M11 may be disposed on the lower layer of each stage, and the third transistor M3, sixth transistor M6, ninth transistor M9, and twelfth transistor M12 receiving input data may be disposed on the middle layer of each stage.

A total of four signals including an input signal and three clock signals having different phase ranges may be input to the single polarity dynamic logic circuit 100 .

Specifically, signals input to the single-polarity dynamic logic circuit 100 may include a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a data input signal IN, and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 may have different phase signal ranges by dividing the phase of 360 degrees into three. That is, as shown in (b) of FIG. 1 , the clock signal may be generated such that the phase range of the first clock signal CK1 includes a range of 0 degrees to 120 degrees, the phase range of the second clock signal CK2 includes a range of 120 degrees to 240 degrees, and the phase range of the third clock signal CK3 includes a range of 240 degrees to 360 degrees.

The embodiment of the present invention is not limited to signals equally divided into three as shown in (b) of FIG. 1, and signals that are divided into three without overlapping ranges may correspond to the embodiment of the present invention. That is, as shown in (a) of FIG. 2, the clock signal can be generated such that the phase range of the first clock signal CK1 includes the range of 0 degrees to 90 degrees, the phase range of the second clock signal CK2 includes the range of 90 degrees to 270 degrees, and the phase range of the third clock signal includes the range of 270 degrees to 360 degrees.

In addition, the present invention can implement an input signal using four clock signals CK1 to CK2. In the case of implementing the present invention using four clock signals, as shown in (a) of FIG. For example, the phase range of the first clock signal CK1 includes a range of 0 degrees to 90 degrees, the phase range of the second clock signal CK2 includes a range of 90 degrees to 180 degrees, the phase range of the third clock signal CK3 includes a range of 180 degrees to 270 degrees, and the phase range of the fourth clock signal CK4 includes a range of 270 degrees to 360 degrees. You can.

Referring to FIG. 1, the output voltage of the first stage 10 is described. When the first stage 10 is in the pre-charge phase stage, the first transistor M1 serving as a pre-charge is turned on, the first clock signal CK1 is input to the first transistor M1, and the second transistor M2 performing an evaluation or hold phase operation is turned off, so that the first stage ( The output voltage of 10) is output as High. When the first stage 10 is in the pre-charge phase stage, virtually no signal is input to the second transistor M2 in the middle layer of the first stage 10 because the second clock signal CK2 has a phase of 0.

On the other hand, when the first stage 10 is in the evaluation phase stage, the first transistor M1 is turned off, and the second transistor M2 performing the evaluation operation is turned on. As a result, the output voltage of the first stage 10 becomes low. When the first stage 10 is in the evaluation phase stage, since the first clock signal CK1 input to the first transistor M1 in the upper layer of the first stage 10 has a phase of 0, virtually no signal is input.

On the other hand, when the first stage 10 has a hold phase step, the hold phase step means a step in which input signals are temporarily held when other stages perform a pre-autonomous step or an evaluation phase step, respectively. Specifically, when the third clock signal CK3 serving as the hold phase has a specific phase other than 0, the first and second clock signals CK1 and CK2 having a phase range different from that of the third clock signal CK3 have phases of 0, so in the case of the first stage 10, both the first transistor M1 serving as a pre-charge and the second transistor M2 serving as an evaluation turns OFF. That is, in the stage performing the hold phase step, the transistor in the lower layer receives only the signal output from the previous stage stage as an input signal.

In addition, since the operating principle of the pre-charge phase step, evaluation phase step, and hold step described above is equally applied to the second stage 20, the third stage 30, and the fourth stage 40, each stage can sequentially perform the pre-charge phase step, the evaluation phase step, and the hold phase step.

Therefore, as shown in FIG. 3, when the first stage 10 is in the evaluation phase, the second stage 20 is in the pre-charge phase, the third stage 30 is in the hold phase, and the fourth stage 40 may be in the evaluation phase.

In this way, when the phase signal of the first stage 10 is in the hold phase stage, the second stage 20 is in the evaluation phase stage, the third stage 30 is in the pre-charge phase stage, and the fourth stage 40 can be in the hold phase stage. In addition, when the first stage 10 is in the pre-charge phase stage, the second stage 20 is in the hold phase stage, the third stage 30 is in the evaluation phase stage, and the fourth stage 40 may be in the pre-charge phase stage.

That is, in the single polarity circuit 100 according to the present invention, unlike the input signal of the conventional single polarity circuit, three clock signals having different phase ranges are input to each stage. When the first stage 10 is in the evaluation phase stage, the second stage 20 is in the pre-charge phase stage and the third stage 30 is located in the hold phase stage. Therefore, it is possible to prevent the phase of the third stage 30 from being in the same phase as the phase of the second stage 20, and through this, the calculation result of the [N-1] stage stage operates independently from the calculation result of the stage [N], thereby solving the racing problem at the output stage of the prior art.

Comparing these drawings, FIG. 4 (a) is a diagram showing output waveforms when a single polarity dynamic logic circuit is implemented based on a first clock signal, a second clock signal, and an input signal according to the prior art, and FIG.

Referring to the graph of (a) of FIG. 4, when the signal of the input terminal is implemented in a cascade structure in which a single polarity dynamic logic circuit is continuously connected according to the prior art, the output of the fourth stage should output the same high level as this, but while the output of the third stage changes from high to low, the output of the fourth stage is high as shown in (a) of FIG. cannot be maintained, and a racing phenomenon that falls to low occurs.

However, in the case of the single polarity dynamic logic circuit 100 according to the present invention, unlike the prior art, since the third clock signal CK3 capable of temporarily holding the phase is used as an input signal, the phase of the third stage 30 can be prevented from being in the same phase as the phase of the second stage 20, and through this, the operation result of the stage [N-1] stage does not affect the operation result of the stage [N] stage. Accordingly, as shown in (b) of FIG. 4 , it can be seen that the output of the fourth stage 40 remains high when the input signal is input as high.

5 is a circuit diagram illustrating components of a single polarity dynamic logic circuit according to another embodiment, and FIG. 6 is a diagram showing waveforms of signals input to the single polarity dynamic logic circuit according to FIG. 5 .

Referring to FIG. 5 , the single-polarity dynamic logic circuit 100 according to an embodiment may include four stages connected in parallel in a cascode form, and specifically, a first stage 10 receiving a first PC signal PC1, a first EV signal EV1, and an input signal IN, and a second stage receiving the second PC signal PC2, the second EV signal EV2, and the output signal of the first stage 10 ( 20), the 3rd stage 30 receiving the 3rd PC signal (PC3), the 3rd EV signal (EV3) and the output signal of the 2nd stage 20, the 4th PC signal (PC4), the 4th EV signal (EV4) and the output signal of the 3rd stage 30. It may include a fourth stage 40 that receives and outputs a final output voltage. In FIG. 5, the PC signal is a signal that causes the input transistor to pre-charge. It is a signal that means , and the EV signal means a signal that causes the input transistor to perform evaluation.

Specifically, the first stage 10 may include a first transistor M1 that pre-charges the first dynamic node O1 in response to the first PC signal PC1, a second transistor M2 that performs an evaluation operation in response to the first EV signal EV1, and a third transistor M3 that receives a data input signal IN including input data. As shown in FIG. 5 , the transistor M1 , the second transistor M2 , and the third transistor M3 may be sequentially connected in series.

The second stage 20 may include a fourth transistor M4 precharging the second dynamic node O2 in response to the second PC signal PC2, a fifth transistor M5 performing an evaluation operation in response to the second EV signal EV2, and a sixth transistor M6 receiving the output signal of the first stage 10 as an input signal, and the fourth transistor M4 , the fifth transistor M5 and the sixth transistor M6 may be sequentially connected in series as shown in FIG. 5 .

The third stage 30 may include a seventh transistor M7 that precharges the third dynamic node O3 in response to the third PC signal PC3, an eighth transistor M8 that performs an evaluation operation in response to the third EV signal EV3, and a ninth transistor M9 that receives the output signal of the second stage 20 as an input signal, and the seventh transistor M7 , the eighth transistor M8 and the ninth transistor M9 may be sequentially connected in series as shown in FIG. 5 .

The fourth stage 40 may include a tenth transistor M10 that precharges the fourth dynamic node O4 corresponding to the output node in response to the fourth PC signal PC4, an eleventh transistor M11 that performs an evaluation operation in response to the fourth EV signal EV4, and a twelfth transistor M12 that receives the output signal of the third stage 30 as an input signal. , the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 may be sequentially connected in series as shown in FIG. The principle of operation of the single-polarity dynamic logic circuit 100 according to FIG. 5 is the same as that described above, and will be omitted, and differences in input signals will be described in detail.

The first PC signal (PC1), the second PC signal (PC2), the third PC signal (PC3), and the fourth PC signal (PC4) input to the upper layer of the single polarity dynamic logic circuit 100 according to FIG. 5 are phase signals sequentially delayed by a preset phase (d) as shown in (a) of FIG.

The first EV signal EV1, the second EV signal EV2, the third EV signal EV3, and the fourth EV signal EV4 may be phase signals sequentially delayed by a predetermined phase d, as shown in FIG.

As described above, the preset phase means a delay phase that does not cause a racing phenomenon at the output terminal of the single polarity logic circuit according to the related art. When the sequentially delayed signal is used as an input signal, the output result at point O1 can be obtained before the second PC signal PC2 and the second EV signal EV2 arrive. Since the outputs of the points O2 and O3 are also output before the third PC signal (PC3), the third EV signal (EV3), the fourth PC signal (PC4), and the fourth EV signal (EV4) are input signals, the single-polarity dynamic logic circuit 100 according to the present invention has the advantage that the racing phenomenon that occurs in the prior art does not occur.

7 and 8 are diagrams showing a circuit diagram of a single-polarity dynamic logic circuit implemented using a NAND gate according to another embodiment of the present invention, an operation process accordingly, and measurement experiment results.

Referring to FIGS. 7 and 8 , the single-polarity dynamic logic circuit 100 according to FIG. 7 may receive input signals of three clock signals CK1, CK2, and CK3 and a data input signal IN as described above. Specifically, as shown in the drawings, the first stage 10 may be implemented by connecting a first inverter and a second inverter in a cascode form, and the second stage 20 may include a first NAND gate. , the third stage 30 can be implemented with a second NAND gate, and the fourth stage 40 can be implemented with a third inverter. Accordingly, the number of transistors included in each stage and the arrangement position can be designed as shown in the drawing.

When the single-polarity dynamic logic circuit 100 is implemented as shown in (a) of FIG. 7, when a logical operation is performed for each stage, each operation can be performed as shown in (b) of FIG. 7, and as shown in FIG.

9 and 10 are diagrams showing a circuit diagram of a single polarity dynamic logic circuit implemented using a NOR gate according to another embodiment of the present invention, and calculation processes and measurement experiment results accordingly.

9 and 10, the single polarity dynamic logic circuit 100 according to FIG. 9 can receive input signals of three clock signals CK1, CK2, and CK3 and a data input signal IN as described above. Specifically, as shown in the drawings, the first stage 10 can be implemented by connecting the first inverter and the second inverter in a cascode form, and the second stage 20 has a first NOR gate , the third stage 30 can be implemented with a 2NOR gate, and the fourth stage 40 can be implemented with a third inverter. Accordingly, the number and arrangement of transistors included in each stage can be designed as shown in the drawing.

When the single-polarity dynamic logic circuit 100 is implemented as shown in (a) of FIG. 9, when a logical operation is performed for each stage, each operation can be performed as shown in (b) of FIG. 9, and as shown in FIG.

11 and 12 are diagrams showing a circuit diagram of a single polarity dynamic logic circuit implemented by sequentially using a NAND gate and a NOR gate according to another embodiment of the present invention, and an operation process and measurement experiment results accordingly.

11 and 12, the single-polarity dynamic logic circuit 100 according to FIG. 11 may receive input signals of three clock signals CK1, CK2, and CK3 and a data input signal IN as described above. Specifically, as shown in the drawings, the first stage 10 may be implemented by connecting a first inverter and a second inverter in a cascode form, and the second stage 20 may be implemented by connecting a 1N It can be implemented as an AND gate, the third stage 30 as a 1NOR gate, and the fourth stage 40 as a third inverter. Accordingly, the number and arrangement of transistors included in each stage can be designed as shown in the figure.

When the single polarity dynamic logic circuit 100 is implemented as shown in FIG. 11 (a), when a logic operation is performed for each stage, each operation can be performed as shown in FIG. 11 (b). As shown in FIG.

13 and 14 are diagrams showing a circuit diagram of a single-polarity dynamic logic circuit implemented by sequentially using a NOR gate and a NAND gate according to another embodiment of the present invention, and calculation processes and measurement experiment results accordingly.

13 and 14, the single-polarity dynamic logic circuit 100 according to FIG. 13 may receive input signals of three clock signals CK1, CK2, and CK3 and a data input signal IN as described above. Specifically, as shown in the drawings, the first stage 10 may be implemented by connecting the first inverter and the second inverter in a cascode form, and the second stage 20 may be implemented by connecting a 1N An OR gate, the third stage 30 can be implemented with a first NAND gate, and the fourth stage 40 can be implemented with a third inverter. Accordingly, the number and arrangement of transistors included in each stage can be designed as shown in the figure.

When the single polarity dynamic logic circuit 100 is implemented as shown in (a) of FIG. 13, when a logical operation is performed for each stage, each operation can be performed as shown in (b) of FIG. 13, and as shown in FIG.

So far, the components and operation principle of the single polarity dynamic logic circuit according to the present invention have been looked at in detail through the drawings.

In the single polarity dynamic logic circuit according to an embodiment, since the third clock signal, which can serve as a hold unlike in the prior art, is additionally utilized as an input signal, the problem of each stage performing an operation in the same phase can be prevented. Accordingly, the calculation result of the [N-1] stage does not affect the calculation result of the [N] stage, so that the racing problem of the output stage voltage, which inevitably occurred in the single-polarity dynamic logic circuit according to the prior art, can be prevented.

The devices described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general purpose or special purpose computers, such as, for example, a processor, controller, arithmetic logic unit (ALU), digital signal processor, microcomputer, field programmable array (FPA), programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. A processing device may run an operating system (OS) and one or more software applications running on the operating system. A processing device may also access, store, manipulate, process, and generate data in response to execution of software. For convenience of understanding, there are cases in which one processing device is used, but those skilled in the art will recognize that the processing device may include a plurality of processing elements and/or multiple types of processing elements. For example, a processing device may include a plurality of processors or a processor and a controller. Other processing configurations are also possible, such as parallel processors.

Software may include a computer program, code, instructions, or a combination of one or more of these, and may configure a processing device to operate as desired, or may independently or collectively direct a processing device. The software and/or data may be embodied in any tangible machine, component, physical device, virtual equipment, computer storage medium or device to be interpreted by, or to provide instructions or data to, a processing device. Software may be distributed on networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer readable media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program commands recorded on the medium may be specially designed and configured for the embodiment or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program instructions such as ROM, RAM, and flash memory. Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes such as those produced by a compiler.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, even if the described techniques are performed in an order different from the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form from the described method, or replaced or substituted by other components or equivalents, appropriate results can be achieved. Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

100: single polarity dynamic logic circuit
10 : 1st stage
20: 2nd stage
30: 3rd stage
40: 4th stage

Claims (15)

a first stage receiving a first clock signal, a second clock signal, and an input signal;
a second stage receiving the second and third clock signals and the output signal of the first stage;
a third stage receiving the third clock signal, the first clock signal, and the output signal of the second stage; and
A fourth stage receiving the first clock signal, the second clock signal, and the output signal of the third stage;
The first clock signal, the second clock signal, and the third clock signal are divided into three and each include a different range phase signal,
Single polarity dynamic logic circuit. delete According to claim 1,
The phase range of the first clock signal includes a range of 0 degrees to 120 degrees,
The phase range of the second clock signal includes a range of 120 degrees to 240 degrees,
The phase range of the third clock signal includes a range of 240 degrees to 360 degrees,
Single polarity dynamic logic circuit. According to claim 3,
When the first stage is in an evaluation phase, the second stage is in a pre-charge phase, and the third stage is in a hold phase,
Single polarity dynamic logic circuit. According to claim 3,
When the phase signal of the first stage is in a hold phase, the second stage is in an evaluation phase, and the third stage is in a pre-charge phase,
Single polarity dynamic logic circuit. According to claim 3,
When the first stage is in a pre-charge phase, the second stage is in a hold phase, and the third stage is in an evaluation phase,
Single polarity dynamic logic circuit. According to claim 1,
The first stage includes a first transistor pre-charging a first dynamic node in response to the first clock signal;
The second stage includes a second transistor precharging a second dynamic node in response to the second clock signal;
The third stage includes a third transistor precharging a third dynamic node in response to the third clock signal;
The fourth stage includes a fourth transistor precharging a fourth dynamic node in response to the first clock signal.
Single polarity dynamic logic circuit. According to claim 7,
The first stage includes a fifth transistor that performs an evaluation operation or a hold operation in response to the second clock signal;
The second stage includes a sixth transistor that performs an evaluation operation or a hold operation in response to the third clock signal,
The third stage includes a seventh transistor that performs an evaluation operation or a hold operation in response to the first clock signal;
The fourth stage includes an eighth transistor that performs an evaluation operation or a hold operation in response to the second clock signal.
Single polarity dynamic logic circuit. According to claim 1,
The first stage includes a ninth transistor receiving an input signal including input data;
The second stage includes a tenth transistor receiving the output signal of the first stage;
The third stage includes an eleventh transistor receiving the output signal of the second stage;
The fourth stage includes a twelfth transistor that receives the output signal of the third stage.
Single polarity dynamic logic circuit. According to claim 1,
The first stage, the second stage, the third stage, and the fourth stage are implemented as inverters, respectively.
Single polarity dynamic logic circuit. A first stage receiving a first PC signal, a first EV signal and an input signal;
a second stage that receives a second PC signal, a second EV signal, and an output signal of the first stage;
a third stage receiving a third PC signal, a third EV signal, and an output signal of the second stage;
A fourth stage that receives the fourth PC signal, the fourth EV signal, and the output signal of the third stage;
The 1PC signal and the 1EV signal have opposite phases to each other,
The 2 PC signal and the 2 EV signal have opposite phases to each other,
The 3PC signal and the 3EV signal have opposite phases to each other,
The 4 PC signal and the 4 EV signal have opposite phases to each other,
Single polarity dynamic logic circuit. According to claim 11,
The 2nd PC signal to the 4th PC signal have signals sequentially delayed by a preset phase based on the 1PC signal,
The 2 EV signal to the 4 EV signal have signals sequentially delayed by a preset phase based on the 1 PC signal,
Single polarity dynamic logic circuit. a first stage receiving a first clock signal, a second clock signal, and an input signal;
a second stage receiving the second and third clock signals and the output signal of the first stage;
a third stage receiving the third clock signal, the first clock signal, and the output signal of the second stage; and
A fourth stage receiving the first clock signal, the second clock signal, and the output signal of the third stage;
The first stage has a first inverter and a second inverter connected in parallel,
The fourth stage is implemented as a third inverter,
The first clock signal, the second clock signal, and the third clock signal are divided into three to include phase signals of different ranges, respectively;
Single polarity dynamic logic circuit. According to claim 13,
The second stage is implemented with NAND gates and the third stage is implemented with NOR gates;
The second stage is implemented with a NOR gate, and the third stage is implemented with a NOR gate.
Single polarity dynamic logic circuit. According to claim 14,
The second stage is implemented with a first NAND gate and the third stage is implemented with a second NAND gate;
The second stage is implemented with a first NOR gate, and the third stage is implemented with a second NOR gate.
Single polarity dynamic logic circuit.