KR102457270B1 - Method of manufactruring piezoelectric thin film and device using the same - Google Patents

Abstract

The present disclosure provides a method for manufacturing a piezoelectric thin film made of Sc _x Al _{1 - x} N, the method comprising: forming a sacrificial layer for removing the deposition substrate on the deposition substrate; And, it relates to a method of manufacturing a piezoelectric thin film comprising; forming a Sc _x Al _{1 - x} N piezoelectric thin film of a wurzite structure on the sacrificial layer.

Description

Method of manufacturing a piezoelectric thin film and a device using the thin film

The present disclosure generally relates to a piezoelectric thin film and a device using the thin film, and more particularly, to a method for manufacturing a Sc _x Al _{1 - x} N piezoelectric thin film and a device using the thin film. Piezoelectric thin films are used in a variety of resonators, including high-quality high-frequency filters, energy harvesters, ultrasonic transducers, and sensors for bio & IoT. resonators) applications, etc. Recently, these thin films have been used as acoustic resonators (eg, surface acoustic wave resonators, BAW resonators) in filters used in portable electronic devices such as smart phones. It is attracting attention as a high-sensitivity sensor for its role and bio and IoT applications. Although the use of the piezoelectric thin film has been exemplified above, the use of the thin film is not limited thereto.

Herein, background information related to the present disclosure is provided, and they do not necessarily mean prior art (This section provides background information related to the present disclosure which is not necessarily prior art).

According to the document Nano Energy 51 (2018) 146-161, “AlN piezoelectric thin films for energy harvesting and acoustic devices”, AlN piezoelectric thin films have high longitudinal acoustic wave velocity (approximately 11,000 m/s), high high thermal stability (melting point; 2100°C, piezoelectric property retention temperature; 1150°C), wide energy bandgap (6.2eV), and excellent piezoelectric and dielectric properties Because of its unique properties, it is used in high-quality high-frequency filters, energy harvesters, ultrasonic transducers, and sensors for bio & IoT applications. It is currently being used explosively as a variety of resonator application products including In general, as a method of forming an AlN piezoelectric thin film material (thin film synthesis), PVD (physical vapor deposition; typically sputtering), which is poly-crystal deposition at a temperature of about 400 ° C., and single crystal at a temperature of about 1000 ° C. CVD (chemical vapor deposition; typically MOCVD, HVPE) is known as epitaxial single crystal growth. At present, due to the film formation (deposition, growth) process of AlN piezoelectric thin film and the device design in consideration of this film formation process, the insulating layer (typically SiO ₂ ) and/or the metal layer including the electrode function are sequentially on the high-resistance Si film-forming substrate, or After forming a multi-layered thin film (typically Mo, Ti, Pt, W, Al), design a device through polycrystalline AlN deposition at a temperature around 400°C, or add a subsequent heat treatment process if necessary to fabricate a designed device is currently doing. However, as will be described in detail later in FIG. 15, due to physical process limitations, the AlN piezoelectric thin film deposited with an optimized process on the insulating layer and/or the metal thin film at a temperature around 400° C. has a textured poly-crystal microstructure ( Compared to AlN piezoelectric thin films of high purity epitaxial single crystal microstructure deposited at a high temperature around 1000°C with microstructure), physical properties including piezoelectricity-related properties are not excellent. As a result, various AlN piezoelectric thin film devices designed They have limitations in terms of performance and application expansion. In other words, in the prior art, the crystal quality (crystallinity and polarity) in the AlN piezoelectric thin film and the device using the same can be deposited on the single or multi-layer thin film of the insulating layer and/or the metal layer formed before the AlN film formation, and the deposition film formation temperature and surface material state It has been difficult to construct an AlN piezoelectric thin film from a material of high purity single crystal because it is limited by physical factors such as. Several methods have been proposed to overcome this limitation and to obtain a high-purity single-crystal AlN piezoelectric thin film and fabricate a device. Direct growth film formation on an epitaxial synthesis substrate (Sapphire, SiC) or deposition on a silicon (Si) single crystal film formation substrate at the highest possible temperature with a sputtering device, followed by wafer bonding ( Methods for completing a device through an AlN piezoelectric thin film transfer technology to a device substrate through wafer-bonding and film-forming substrate lift-off have been proposed.

1 is a view showing devices using a piezoelectric thin film disclosed in US Patent Publication No. US2015-0033520, and in FIG. 1 (a), an example of an FBAR (20; Film Bulk Acoustic Resonator) is presented, and FIG. SMR (20'; Solidly Mounted Resonator) is presented. FBAR and SMR belong to BAW resonators. The FBAR 20 includes a pair of electrodes 22 and 24 , a piezoelectric thin film 26 placed between the pair of electrodes 22 and 24 , and a device substrate 30 . A pair of electrodes 22 and 24 and a piezoelectric thin film 26 are suspended in a cavity 28 formed in the device substrate 30 . The SMR 20' includes a pair of electrodes 22' and 24', a piezoelectric thin film 26' interposed between the pair of electrodes 22' and 24', and a device substrate 30'. Unlike the FBAR 20 , a Bragg reflector 27 ′ having a multilayer structure is provided instead of a reflector in the cavity 28 .

2 to 4 are views showing an AlN piezoelectric thin film and a method of manufacturing a device using the same as presented in US Patent Publication No. US2015-0033520, first, a single crystal AlN piezoelectric thin film is grown on a sapphire (Al ₂ O ₃ ) film-forming substrate. (Fig. 2(a)). At this time, unlike the conventional formation of a SiO ₂ film and an electrode made of Mo on a Si film substrate and then forming an AlN piezoelectric thin film through sputtering, which is PVD (Physical Vapor Deposition), HVPE or CVD (Chemical Vapor Deposition) MOVCD is used. to form a high-quality, high-purity, single-crystal AlN piezoelectric thin film. Next, a contact electrode is formed (Fig. 2(b). In the case of manufacturing SMR, a Bragg reflector (SiO ₂ /W) reflector is first formed on a separately provided semiconductor device substrate (Fig. 3(c)). The AlN piezoelectric thin film structure 40 and the Bragg reflector reflector structure 42 are wafer-bonded (Fig. 3(d)). Next, a sapphire film is formed from the bonded structure 44 through Laser Lift Off (LLO). The substrate is separated (Fig. 3(e)). Finally, an upper electrode is formed on the structure 46 from which the sapphire deposition substrate is separated (Fig. 3(f)). In the case of manufacturing the FBAR, first a separately prepared semiconductor device An air cavity is formed in the substrate (Fig. 4(c)) Next, the AlN piezoelectric thin film structure 40 and the cavity structure 52 are combined (Fig. 4(d). Next, the laser from the bonded structure 54) The sapphire deposition substrate is separated through lift-off (LLO) (Fig. 4(e)) Finally, an upper electrode is formed in the structure 56 from which the sapphire deposition substrate is separated (Fig. 4(f)).

Compared to a polycrystalline AlN piezoelectric thin film deposited through a sputtering device on a silicon oxide (SiO ₂ ) and/or metal (electrode) material on a conventional Si deposition substrate, MOCVD growth deposition on a sapphire deposition substrate The single-crystalline AlN piezoelectric thin film greatly improves the performance and quality of the resonator. However, an AlN piezoelectric thin film having optical properties of a short wavelength of 200 nm when converted to a wavelength of 6.2 eV energy bandgap is directly grown on a sapphire film-forming substrate, and then it is directly grown on the currently commercially available ArF (193 nm) & KrF (248 nm), etc. It is by no means easy to isolate using the excimer laser light energy source of For this reason, in order to separate the two material layers using a laser light energy source, strong absorption of the laser light energy source at the interface and a thermo-chemical decomposition reaction through conversion into thermal energy are performed. The process of separating a specific deposited thin film having a function from the deposition substrate through this mechanism is called “laser lift off (LLO)”. The starting point of the laser lift-off (LLO) mechanism is that a sacrificial ayer composed of a suitable material that can absorb the laser light energy source and convert it into a thermal energy source must be present between the optically transparent deposition substrate and the specific deposited thin film. . A suitable condition for this sacrificial ayer material is an optically transparent semiconductor having an energy bandgap of a wavelength sufficiently larger than the wavelength of the laser irradiated and incident through the back surface of the optically transparent sapphire film formation substrate, and at the same time, an optical energy source. An amorphous, polycrystalline (amorphous or polycrystalline), or a material region having a multi-layer microstructure that can absorb as much as possible is absolutely required. The method overlooked and described this point.

5 is a view showing an example of a method for manufacturing an AlN piezoelectric thin film presented in US Patent Publication No. US2006-0145785, a sapphire deposition substrate 200, a buffer layer 210 grown on the sapphire deposition substrate 200; e.g.: GaN), an AlN piezoelectric thin film 220 formed on the buffer layer 210 , and a bonding metal 230 (eg, Au) formed on the AlN piezoelectric thin film 220 are presented. Gallium nitride (GaN) constituting the buffer layer 210 is a material having an energy bandgap of 3.4 eV (at the time of wavelength conversion, 364 nm) and at the same time has an amorphous microstructure formed as a low-temperature growth film. The GaN buffer layer 210 has the advantage of facilitating the separation of the optically transparent sapphire deposition substrate 200 and the AlN piezoelectric thin film 220 because it can sufficiently serve as a sacrificial layer, but the GaN buffer layer ( 210) and the AlN piezoelectric thin film 220, there is a significant difference in properties of lattice constant and thermal expansion coefficient, so a high-purity single crystal MOCVD-grown to a certain critical thickness (approximately 100 nm) that can be used as a functional piezoelectric thin film such as a resonator In order to secure the AlN piezoelectric thin film 220, it is by no means easy with known processes and technologies to date.

6 is a view showing an example of a method for manufacturing an AlN piezoelectric thin film presented in Solid-State Electronics 54 (2010) 1041-1046, the manufacturing method is as shown in FIG. 6(a), (001) silicon film formation Forming a sputter-deposited AlN piezoelectric thin film 62 directly on the substrate 61, as shown in FIG. 6(b), forming a lower electrode 63 on the AlN piezoelectric thin film 62; As shown in 6(c), forming an acoustic mirror 64 formed on the lower electrode 63, as shown in FIG. 6(d), a wafer on the acoustic wave mirror 64 Forming a bonded carrier wafer 65, as shown in FIG. 6(e), removing the (100) silicon deposition substrate 61 by wet etching, and FIG. 6(f) As shown in Fig. , it includes the step of forming the upper electrode 66 on the AlN piezoelectric thin film 62 from which the (100) silicon deposition substrate 61 is finally removed, and through this, the SMR BAW structure resonator is manufactured. According to this method, a structure in which SiO ₂ and/or metal (electrode) is formed on a silicon deposition substrate and then an AlN piezoelectric thin film is formed (eg, “Optimization of sputter deposition Process for piezoelectric AlN ultra-thin Films”, Semester Project, Advanced NEMS group, Autumn Semester 2017, Roman Welz, January 23, 2018, SECTION MICROTECHNIQUE), a separate additional process (CMP; chemical-mechanical polishing) for quality improvement is unnecessary and has a uniform thickness. It is possible to obtain a piezoelectric thin film and at the same time has the advantage of excluding the native oxide formed on the surface of the electrode (metal), which has a great influence on the quality of the piezoelectric thin film. It has been pointed out that

In addition, there is a method of growing a high-purity AlN piezoelectric thin film on a SiC film-forming substrate, but the SiC film-forming substrate is expensive, and after growing a high-purity AlN thin film on a SiC film-forming substrate, SiC film formation through chemical wet etching in the known AlN piezoelectric thin film resonator manufacturing process Since the substrate is removed, it cannot be reused, so it is not considered because it cannot solve the problem of high cost and cost of the AlN piezoelectric thin film resonator.

This will be described at the end of 'Specific Contents for Implementation of the Invention'.

Herein, a general summary of the present disclosure is provided, which should not be construed as limiting the scope of the present disclosure (This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).

According to one aspect according to the present disclosure (According to one aspect of the present disclosure), in the method of manufacturing a piezoelectric thin film of Sc _x Al _{1 - x} N, forming a sacrificial layer for removing the deposition substrate on the deposition substrate step; And, forming a Sc _x Al _{1 - x} N piezoelectric thin film of a wurzite structure on the sacrificial layer; a method of manufacturing a piezoelectric thin film comprising a.

This will be described at the end of 'Specific Contents for Implementation of the Invention'.

1 is a view showing devices using a piezoelectric thin film presented in US Patent Publication No. US2015-0033520,
2 to 4 are views showing an AlN piezoelectric thin film presented in US Patent Publication No. US2015-0033520 and a method of manufacturing a device using the same;
5 is a view showing an example of a method for manufacturing an AlN piezoelectric thin film presented in US Patent Publication No. US2006-0145785;
6 is a view showing an example of a method for manufacturing an AlN piezoelectric thin film presented in Solid-State Electronics 54 (2010) 1041-1046;
7 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film according to the present disclosure, and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure; A drawing showing an example,
8 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film according to the present disclosure, and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure; A drawing showing another example,
9 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; A drawing showing another example,
10 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; A drawing showing another example,
11 to 13 are views showing an example of a method of manufacturing a resonator using the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure;
14 and 15 are views showing another example of a method of manufacturing a resonator using the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure;
16 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; A drawing showing another example,
17 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; A drawing showing another example,
18 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; A drawing showing another example,
19 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; A drawing showing another example,
20 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film according to the present disclosure, and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure. A drawing showing another example,
21 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; A drawing showing another example,
22 and 23 are views showing another example of a method of manufacturing a resonator using the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure;
24 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure;
25 is a graph showing the physical properties of Sc _x Al _{1 - x} N and Sc _x Ga _{1 - x} N;
26 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure;
27 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure;
28 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure;
29 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure;
30 is a view illustrating a method for manufacturing a piezoelectric thin film according to the present disclosure and another example of a piezoelectric thin film structure;

Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings (The present disclosure will now be described in detail with reference to the accompanying drawing(s)).

7 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film according to the present disclosure, and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure; As a view showing an example, the structure includes a sapphire film-forming substrate 1, a first semiconductor layer 2, a sacrificial layer 3, and an Al _x Ga _{1 -x} N (0.5≤x≤1) piezoelectric thin film 4 . include

8 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film according to the present disclosure, and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure; As another example, the structure includes a sapphire film-forming substrate 1, a first semiconductor layer 2, a sacrificial layer 3, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4) and, additionally, a second semiconductor layer 5 between the sacrificial layer 3 and the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 .

9 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; As another example, the structure includes a sapphire film-forming substrate 1, a first semiconductor layer 2, a sacrificial layer 3, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4) However, the order of formation of the first semiconductor layer 2 and the sacrificial layer 3 is changed from that of the structure shown in FIG. 7 .

10 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; As a view showing another example, the structure is a sapphire film-forming substrate 1, a first semiconductor layer 2, a sacrificial layer 3, Al _x Ga _{1 -x} N (0.5≤x≤1) piezoelectric thin film 4 And although the second semiconductor layer 5 is included, the formation order of the first semiconductor layer 2 and the sacrificial layer 3 is changed from the structure shown in FIG. 8 .

For example, a C-plane sapphire deposition substrate may be used, and the Group III nitride formed thereon may have a polarity (metallic or gas) surface or semi-polarity (metallic polarity and nitrogen) depending on the growth pretreatment conditions. If it is possible to have a surface with mixed gas polarities), it is possible to consider the use of a sapphire deposition substrate that is not on the C-plane or is not the C-plane. In addition to the flat deposition substrate, the use of a nano-sized patterned sapphire substrate (PSS) may be considered.

7 and 8, the first semiconductor layer 2 is made of Al _y Ga _{1 - y} N (0.5≤y≤1) grown and deposited at a high temperature (1000° C. or higher) rather than at a low temperature, followed by It serves to ensure the crystal quality (crystallinity and polarity) of the grown Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 . Therefore, it is distinguished from a conventional layer called a buffer layer that is grown and formed at a temperature lower than an appropriate growth temperature. The first semiconductor layer 2 may be grown and deposited by CVD (eg, MOCVD, HVPE, ALD). The upper and lower limits of the thickness of the first semiconductor layer 2 of Al _y Ga _{1 - y} N (0.5≤y≤1) are not particularly limited, but preferably Al _x Ga _{1 - x} N (0.5≤x≤1) ) The thickness of the piezoelectric thin film 4 is set to 100 nm-20 μm to be advantageous for a stress control function to maintain the thickness uniformity. For example, at a temperature of 1000-1400 ℃ and a pressure of 100-200 torr, a growth film can be formed, and an atmosphere consisting of ammonia (NH ₃ ) and nitrogen (N ₂ ) containing a large amount of hydrogen (H ₂ ) (relatively) NH ₃ content is greater than N ₂ ) or ammonia (NH ₃ ) and nitrogen (N ₂ ) in an atmosphere composed of 100% Al for AlN, Al/(Al+Ga) for Al-rich AlGaN When the value is set to 50% or more, a growth film can be formed. Preferably, as a pretreatment, before growth of the first semiconductor layer 2 of Al _y Ga _{1 - y} N (0.5≤y≤1) at the appropriate growth temperature, Al MOCVD source gas (eg, at 900-1000° C. for 10 sec) : TMAl) inside the chamber, forming an AlN buffer layer with a thickness of 20 nm or less, and then growing and forming a film at appropriate growth conditions of 1000-1400° C. and 100-200 torr, ensuring high-quality crystallinity and reducing dislocation density (reduction in Dislocation density), crack generation and propagation suppression (suppression of generation & propagation) intentionally in the adjacent region of the sapphire deposition substrate 1 and the first semiconductor layer of Al _y Ga _{1 - y} N (0.5≤y≤1) (2) It is advantageous to form a plurality of air-voids therein.

In the examples shown in FIGS. 9 and 10 , the first semiconductor layer 2 is preferably made of Al _y Ga _{1 - y} N (0.5≤y≤1) of 100 nm or less, followed by Al _x Ga ₁ to be grown and deposited _{- x} N (0.5≤x≤1) It serves to ensure the crystallinity and polarity of the piezoelectric thin film (4). The first semiconductor layer 2 may be deposited by PVD (eg, sputtering, PLD), and at this time, it is important to supply a certain amount of oxygen (eg, O ₂ /(N ₂ +O ₂ ) value of 3% or less), , serving as nanoscale AlN or Al-rich AlGaN seeds. The sputtering deposition of Al _y Ga _{1 - y} N (0.5≤y≤1) in an atmosphere containing a small amount of O ₂ is relatively small island-shaped Al _y Ga _{1 - y} N (0.5≤y≤1). ) to form crystals and CVD (eg, MOCVD, HVPE, ALD) growth at the appropriate growth temperature to improve the surface flatness of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 and the inside of the thin film It plays an important seed role in securing high-quality crystallinity and polarity by reducing the dislocation density of The thickness of the first semiconductor layer 2 is preferably 100 nm or less, more preferably Al _x Ga _{1 - x} N (0.5≤x≤1) 1 nm- which is more advantageous for suppressing crack generation and propagation of the piezoelectric thin film 4 30 nm. For example, the temperature and pressure of 300-500 ℃ can be deposited into a film at a pressure of 5*10 ^-3 mbar, nitrogen (N ₂ ) containing a large amount of argon (Ar) and oxygen (O ₂ ) An atmosphere composed of (Relatively higher N ₂ content than O ₂ ; Ar 40sccm, N2 110sccm, O2 4sccm) can be used. The quality of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film (4) formed as a growth film was examined through the X-ray (0002) rocking curve, which is one of the quality measurement indicators, and 0.04- It showed a value of 0.06°. This shows that the quality of the thin film is greatly improved compared to 1.2-2.5°, which is the value of the current commercial structure (Si film substrate/SiO ₂ /metal electrode/AlN).

The first semiconductor layer 2 shown in FIGS. 7 and 8 and the first semiconductor layer 2 shown in FIGS. 9 and 10 are made of Al _y Ga _{1 - y} N (0.5≤y≤1), and are subsequently grown It is common in that it serves to ensure crystallinity and polarity of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 to be formed.

The sacrificial layer 3 is formed of Al _x Ga _{1 - x} N (0.5≤x≤1) sapphire prior to forming the piezoelectric thin film 4 to facilitate separation of the sapphire deposition substrate 1 during laser lift-off (LLO). It is an optically transparent semiconductor having an energy bandgap of a wavelength sufficiently larger than the wavelength of the laser irradiated through the back surface of the deposition substrate 1, and at the same time, an amorphous or polycrystalline semiconductor capable of absorbing as much light energy source as possible. Polycrystalline, or regions of material with a multi-layer microstructure are preferred, for example multi-layered Al _x1 Ga _{1 - x1} N/Al _x2 Ga _{1 - x2} N (x ₂ <x ₁ ≤1, 0≤x ₂ <0.5), single-layer Ga-rich AlGaN (Ga/(Ga+Al) value of 50% or more) and GaN. The sacrificial layer 3 may be grown and formed by CVD (eg, MOCVD, HVPE, ALD), and absorbs laser energy during laser lift-off to form a sapphire film-forming substrate 1 side and Al _x Ga _{1 - x} N ( 0.5≤x≤1) serves to separate the piezoelectric thin film 4 side. In general, Al _z Ga _{1 - z} N energy bandgap, E(z)=3.43+1.44z+1.33z ² (eV), confirmed from theory and experiment, if Al ₀ with 50% Al composition _{. 5} Ga _0.5 N has an energy bandgap of 4.48 eV _. It is an equation that converts the energy bandgap (eV) value of a semiconductor (including an insulator) into a wavelength that is an optical characteristic, λ(nm) = 1240/E(z). If the wavelength is converted through this equation, a value of 277 nm can be obtained. Therefore, a single layer of Al _z Ga _1-z N and GaN material having an Al composition of less than 50%, or a sacrificial layer 3 having a multi-layer microstructure composed of these, is produced through a relatively generalized high-power short-wavelength laser light source (248 nm or more). easy to remove The thickness of the sacrificial layer 3 may be, for example, 100 nm or less, preferably Al _x Ga _{1 - x} N (0.5≤x≤1) 1 nm-30 nm which is more advantageous for suppressing crack generation and propagation of the piezoelectric thin film 4 do it with In the case of Al _z Ga _{1 - z} N having an Al composition of less than 50%, it is possible to grow at 900-1200° C. and 100-200 torr conditions, and in the case of GaN, it is possible to grow at 600-1100° C. and 100-200 torr conditions. After growth of the sacrificial layer 3 on the sapphire deposition substrate 1, Al _x Ga _{1 - x} N (0.5≤x≤1) sputtering AlN thin film serving as a seed before growth and deposition of the piezoelectric thin film 4 As a pre-sputtering treatment, a small amount of Ar (planarization and cleaning through surface etching), a small amount of oxygen (O ₂ ) and a large amount of nitrogen (N ₂ ) gas containing a small amount of oxygen (O 2 ) are used to stabilize the surface of the sacrificial layer 3 in the chamber. including the step of making Al _x Ga _{1 - x} N (0.5≤x≤1) The piezoelectric thin film 4 may be grown and formed by CVD (eg, MOCVD, HVPE, ALD), and is formed as a single crystal thin film. The thickness may vary depending on the final device, for example, when used in the FBAR shown in FIG. thickness is determined. Al _x Ga _1-x N (0.5≤x≤1) A case in which the piezoelectric thin film 4 includes Ga may be considered, and accordingly, the first semiconductor layer 2 , the sacrificial layer 3 and the second semiconductor layer The Ga composition of (5) may be different.

The second semiconductor layer 5 shown in FIG. 8 is, for example, before the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is formed by CVD (eg, MOCVD, HVPE, ALD). It can be deposited as a growth film in a step process, as a single layer of Al _a Ga _{1 - a} N (0.5<a≤1) or as Al _b1 Ga _{1 - b1} N/Al _b2 Ga _{1 - b2} N (b ₁ ≠ b ₂ ). It has a multi-layer structure (the content of Al is preferably 50% or more as the whole multi-layer structure), but the Al content is higher than that of the overall sacrificial layer 3, so Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film (4) and the Ga-rich sacrificial layer (3) serves to resolve the stress (stress) difference between the layer (3). The second semiconductor layer 5 may have a structure in which the Al content increases from the sacrificial layer 3 toward the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 and is gradated upward. of course there is In the case of the example shown in FIG. 10 , the first semiconductor layer 2 is positioned between the second semiconductor layer 5 and the sacrificial layer 3 , but since the thickness of the first semiconductor layer 2 is not thick, the By providing the second semiconductor layer 5 as in the example, the stress between the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 and the sacrificial layer 3 having a high Ga content ) plays a role in dissolving the car. In addition, the second semiconductor layer 5 plays an important role in determining the thickness uniformity of the entire wafer when the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 is grown and formed. A process of adding Si or/and Mg dopants may be added to control wafer strain. The thickness of the second semiconductor layer 5 may be, for example, 100 nm or less, preferably Al _x Ga _{1 - x} N (0.5≤x≤1), which is more advantageous for suppressing crack generation and propagation of the piezoelectric thin film 4 . 1nm-30nm.

11 to 13 are diagrams illustrating an example of a method of manufacturing a resonator using the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure. Here, the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure was applied to the resonator, but the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film was formed from the sapphire film substrate After removing Al _x Ga _1-x N (0.5≤x≤1), any device or device that can use the piezoelectric thin film can be expanded and applied without limitation. Of course, the method shown in FIGS. 3 and 4 can be used, and of course, it can also be applied to a SAW resonator in addition to the BAW resonator. Hereinafter, the structure shown in FIG. 7 will be described. 11, first, Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 having a metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) face ) on the first electrode (6; for example, Mo, W, Ta, Pt, Ir, Ru, Rh, Re, Au, Cu, Al, Invar, or an alloy thereof) is formed. Next, on the first electrode 6 , the first passivation layer 7 (eg, Mo, W, Ta, Pt, Ti, TiW, TaN, TiN, SiO ₂ , Al ₂ O ₃ , SiC, SiCN, SiN _x , AlN) , Polyimide, BCB, SU-8, SOG, etc.). Next, a first bonding layer 8 (eg, SnIn, AuSn, AgIn, PdIn, NiSn, CuSn, Cu to Cu, Au to Au, Epoxy, SU-8, BCB) is formed on the first passivation layer 7 . . A temporary substrate 9 (eg, sapphire, AlN, glass) is wafer-bonded to the first bonding layer 8 . Next, the sapphire film-forming substrate 1 is separated through laser lift-off (LLO). In this process, a metal droplet removal process, a trimming process for accurate thickness adjustment, etc. may be accompanied. The surface of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 after separation of the sapphire film-forming substrate 1, metal droplet removal, trimming process, etc. is a surface with nitrogen gas polarity (N-polarity) (face). Then, as shown in FIG. 12 , the second electrode ₁₄ (eg, _{Mo ,} W, Ta, Pt, _Ir , Ru, Rh, Re, Au, Cu, Al, Invar, and their alloys) and a Bragg reflector (10; for example, SiO ₂ /W) having a multilayer structure are formed. Preferably, after the deposition process of the second electrode 14 and the Bragg reflector 10 reflector, a second protective film 11 (eg, Mo, W, Ta, Pt, Ti, TiW, TaN, etc.) on the Bragg reflector 10 reflector is formed. TiN, SiO ₂ , Al ₂ O ₃ , SiC, SiCN, SiN _x , AlN, Polyimide, BCB, SU-8, SOG, etc.). Next, a second bonding layer 12 (eg, SnIn, AuSn, AgIn, PdIn, NiSn, CuSn, Cu to Cu, Au to Au, Epoxy, SU-8, BCB, etc.) is formed on the second passivation layer 11 . . Then, as shown in FIG. 12 , the device substrate 13 (eg, Si, GaAs, AlN, Mo, Cu, W, MoCu, CuW, Invar, Laminate) is bonded to the second bonding layer 12 and eutectic bonding; The wafer is bonded by a method such as brazing. Although not shown, an electrical insulator material layer (protective layer) and a wafer bonding layer are sequentially formed on the device substrate 13 prior to wafer bonding. Finally, the temporary substrate 9 is separated and removed through thermal processing, laser irradiation, and chemical and physical energy source supply, and then the first bonding layer 8 and the first protective film 7 are removed. The examples shown in Figs. 8 to 10 may be similarly applied. At this time, the second semiconductor layer 5 is also removed. By using two wafer bonding processes, the metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) face of the Al _x Ga _{1 -x} N (0.5≤x≤1) piezoelectric thin film 4 is formed. It can be used as the upper surface of the device, and through this, it has a surface chemically and structurally stable such as corrosion resistance, and thus has an advantage in terms of post-processing and quality of the final device.

14 and 15 are views showing another example of a method of manufacturing a resonator using the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure, and FIGS. Unlike the method presented in 13, a temporary substrate 9 is not used. First, as shown in FIG. 14 , a second electrode 14 (eg, Mo, W, Ta, Pt, Ir, Ru, Rh, Re, Au, Cu, Al, Invar, or an alloy thereof) and a multilayer structure After forming the Bragg reflector 10 reflector, the second protective film 11 , and the second bonding layer 12 of the device substrate 13 , wafer bonding is performed, and then the sapphire film formation substrate 1 is removed. Finally, as shown in FIG. 15 , the first electrode 6 is formed.

The difference between the method shown in FIGS. 11 to 13 and the resonator element manufactured by the method shown in FIGS. 14 and 15 depends on the position where the second electrode 14 including the Bragg reflector 10 is formed and the number of wafer bonding times. Al _x Ga _{1 - x} N (0.5≤x≤1) The surface polarity of the piezoelectric thin film 4 is determined. The method shown in FIGS. 11 to 13 is manufactured through two wafer bonding processes, and the second electrode 14 including the Bragg reflector 10 reflector is Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric A second electrode 14 including a Bragg reflector 10 reflector in the case of the method presented in FIGS. 14 to 15, which is placed on the nitrogen gas polarity face of the thin film 4, while undergoing one wafer bonding process. This Al _x Ga _1-x N (0.5≤x≤1) is located on the metallic polarity surface (Al-polarity or Al-polarity & Ga-polarity mixed face) of the piezoelectric thin film 4 . For reference, in the case of a resonator device made of a polycrystalline AlN piezoelectric thin film formed through sputtering on a conventional Si film-forming substrate, there is a limit to adjusting the surface polarity and polarity ratio. The polarity position of the two electrodes 14 cannot be defined.

16 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; As another example, the structure includes a sapphire deposition substrate 1 , a sacrificial layer 23a , and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 . The sacrificial layer 23a is a single layer Al _c Ga _{1 - c} N (0≤c≤0.5) or a multilayer Al _c1 Ga _{1 - c1} N/Al _c2 Ga ₁ grown and deposited by CVD (MOCVD, ALD, MBE, etc.) _- It may consist of a group III nitride of _c2 N (c ₂ < c ₁ ≤ 1, 0 ≤ c ₂ < 0.5). Al _x Ga _{1 - x} N (0.5≤x≤1) The piezoelectric thin film 4 is deposited by PVD (eg sputtering, PLD) on the sacrificial layer 23a at a temperature of 0.3Tm (melting point of the piezoelectric thin film material) or higher. and high quality is ensured.

17 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; As another example, the structure is sequentially on the sapphire deposition substrate 1, the sacrificial layer 23a, the second semiconductor layer 5, and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film (4) is included. It is distinguished from the structure shown in FIG. 17 in that the second semiconductor layer 5 is added, and the second semiconductor layer 5 functions like the second semiconductor layer 5 shown in FIG. 8 , and the sacrificial layer 23a ), it is formed by CVD, but it is made of Group III nitride having a different composition (Al _a Ga _{1 - a} N (0.5<a≤1)), so Al _x Ga _{1 - x} N having a uniform thickness by controlling the stress (0.5≤x≤1) It serves to promote the piezoelectric thin film 4 to be secured.

18 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film according to the present disclosure, and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure. As another example, the structure includes a sapphire deposition substrate 1 , a sacrificial layer 23b , and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 . A single layer of ZnO, ITO, or a multilayer oxide structure (ZnO/ITO, ZnO/SiO ₂ , ITO/SiO ₂ ) including at least one of which the sacrificial layer 23b is deposited with PVD (eg, L sputtering, PLD) ), it is distinguished from the structure shown in FIG. 16 in that it is made of an oxide. Al _x Ga _{1 - x} N (0.5≤x≤1) The piezoelectric thin film 4 is deposited on the sacrificial layer 23b with PVD (eg, sputtering, PLD, etc.) at a temperature of 0.3Tm (melting point of the piezoelectric thin film material) or higher The film is formed to ensure high quality.

19 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; As a view showing another example, the structure is sequentially on the sapphire deposition substrate 1 on the sacrificial layer 23b, oxygen (O ₂ ) inflow prevention layer (O), and Al _x Ga _{1 - x} N (0.5≤x≤1) ) a piezoelectric thin film 4 . It is distinguished from the structure shown in FIG. 18 in that an oxygen (O ₂ ) inflow prevention layer (O) is added, and the oxygen (O ₂ ) inflow prevention layer (O) is an AlN or AlNO material containing a small amount of oxygen on the sacrificial layer 23b. By deposition and forming the same PVD (eg L sputtering, PLD) as the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 that is deposited and subsequently deposited, oxygen inflow from the sacrificial layer 23b is prevented. It serves to promote the high-purity Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 by preventing it.

In the examples shown in FIGS. 16 and 17 , the sacrificial layer 23a is a monolayer Al _c Ga _{1 - c} N formed by single crystal growth deposition by CVD (MOCVD, HVPE, ALD, MBE) at a high temperature (900° C. or higher) rather than a low temperature. (0≤c≤0.5) or multi-layered Al _c1 Ga _{1 - c1} N/Al _c2 Ga _{1 - c2} N (c ₂ <c ₁ ≤ 1, 0≤c ₂ <0.5) group 3 nitride, , followed by Al _x Ga _{1 - x} N (0.5≤x≤1) crystal quality (crystallinity and polarity) ) to ensure Therefore, the sacrificial layer 23a is distinguished from the conventional buffer layer grown at a temperature lower than the appropriate growth temperature, and serves as the first semiconductor layer 2 and the sacrificial layer 3 shown in FIGS. 7 to 10 . The difference is that they are performed at the same time. The upper and lower limits of the thickness of the sacrificial layer 23a are not particularly limited, but preferably Al _x Ga _1-x N (0.5≤x≤1) stress for maintaining the thickness uniformity of the piezoelectric thin film 4 . It is set to 50nm-3㎛ to be advantageous for the stress control function. For example, it may be grown at a temperature of 900-1100° C. and a pressure of 100-600 torr. More preferably, as in the example shown in FIG. 17, the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 positioned between the sacrificial layer 23a and the Al _x Ga ₁ followed by deposition. _{- x} N (0.5≤x≤1) A second semiconductor layer 5 is provided to improve crystallinity and thickness uniformity of the piezoelectric thin film 4 . The second semiconductor layer 5 is formed as a single crystal growth film by the same CVD (MOCVD, HVPE, ALD, MBE, etc.) as the sacrificial layer 23a, wherein Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film ( It is preferable to consist of a group III nitride having the same or similar composition to 4). In addition, the sacrificial layer 23a and the second semiconductor layer 5 are of high quality (crystallinity and polarity) and uniform thickness when the Al _y Ga _{1 - y} N (0.5 ≤ y ≤ 1) piezoelectric thin film 4 is deposited. It is preferable to control the film-forming substrate to maintain a curvature as possible as possible in a zero (flatness) state.

In the examples shown in FIGS. 18 and 19 , the sacrificial layer 23b is a single layer of ZnO formed by deposition having crystallinity (polycrystalline or single crystal) with PVD (eg, sputtering, PLD) at high temperature (400° C. or higher) rather than low temperature. and ITO, or a multilayer oxide structure including at least one of them (ZnO/ITO, ZnO/SiO ₂ , ITO/SiO ₂ ). The upper and lower limits of the thickness of the single sacrificial layer 23b are not particularly limited, but preferably Al _x Ga _{1 - x} N (0.5≤x≤1) to maintain the thickness uniformity of the piezoelectric thin film 4 . It is set to 50nm-3㎛ to be advantageous for the stress control function. The sacrificial layer 23b may be deposited by PVD (eg, sputtering, PLD), and the deposition substrate temperature during film formation is 750° C., and the process pressure consisting of argon (Ar) and oxygen (O ₂ ) gas is 10-20 mTorr, and , the amount of oxygen compared to argon is relatively small, and it is preferable to configure it within at least 50%. More preferably, as in the example shown in FIG. 18 , the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 is positioned between the sacrificial layer 23b and the Al _x Ga ₁ subsequently deposited. _{- x} N (0.5≤x≤1) To improve the crystallinity and thickness uniformity of the piezoelectric thin film 4, an oxygen (O ₂ ) inflow prevention layer (O) is provided. The oxygen (O ₂ ) inflow prevention layer (O) is deposited on the sacrificial layer 23b with AlN or an AlNO material containing a small amount of oxygen, followed by deposition Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric A high-purity Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 is formed by depositing the same PVD (eg, sputtering, PLD) as the thin film 4 to prevent oxygen inflow from the sacrificial layer 23b. It serves as a facilitator to obtain In particular, when AlNO (Al _y Ga _{1 - y} N (0.5≤y≤1) sputtering deposition in an atmosphere containing a small amount of O ₂ ) is applied as an oxygen (O ₂ ) inflow prevention layer (O), a certain amount (eg, O ₂ / (N ₂ +O ₂ ) value of 3% or less) oxygen supply is important, and serves as a seed to secure high-purity Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 . The sputtering deposition of Al _y Ga _1-y N (0.5 ≤ y ≤ 1) in an atmosphere containing a small amount of O ₂ is relatively small island-shaped Al _y Ga _{1 - y} N (0.5 ≤ y ≤ 1). Improvement of the surface flatness of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 and It plays a crucial role in securing high-quality crystallinity and polarity by reducing dislocation density. The thickness of the oxygen inflow prevention layer (O) composed of AlN or AlNO is preferably 100 nm or less, and more preferably Al _x Ga _1-x N (0.5 ≤ x ≤ 1) to suppress crack generation and propagation of the piezoelectric thin film 4 It is set as 1 nm-30 nm which is more advantageous. For example, a temperature and pressure of 300-500 °C can be deposited at a pressure of 5*10 ^{- 3} mbar.

The crystalline quality of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 structure manufactured according to the method shown in FIGS. 16 to 19 is in common the half width at half maximum of the X-ray rocking curve. It aims to have this small value (target value: 0.1° or less), and with respect to polar quality, in the case of FIGS. 16 and 17, the sacrificial layer 23a and the second semiconductor layer 5, FIG. 18 and 19, there is an advantage that can be freely adjusted according to the surface state of the sacrificial layer 23b and the oxygen inflow prevention layer (O).

It goes without saying that the method of manufacturing the resonator shown in FIGS. 11 to 15 can be directly applied to the structure shown in FIGS. 16 to 19 .

16 to 19 , the sacrificial layers 23a and 23b are formed on the optically transparent film-forming substrate 1 through the ① Laser Lift-Off (LLO) process. Al _x Ga _{1 - x} N (0.5≤x≤1) ) located between the film-forming substrate 1 and the high-purity piezoelectric thin film 4 to separate the piezoelectric thin film 4, ② having an energy bandgap (generally 200 nm or more) to function as a sacrificial layer for the laser, ③ It may be composed of a Group III nitride formed by CVD, a Group II or III oxide (eg, ZnO, In ₂ O ₃ , Ga ₂ O ₃ , ITO) formed by PVD, ④ Al _x Ga _{1 - x} N (0.5≤ x≤1) To enable high-temperature film formation of the piezoelectric thin film, it must be a material with thermal stability above 0.3Tm (660℃), ⑤ Al _x Ga _{1 - x} N (0.5≤) having a hexagonal crystal structure (HCP) x≤1) a material having the same or similar crystal structure as the piezoelectric thin film 4, and ⑥ Al _x Ga _{1 - x} N (0.5≤x≤1) surface roughness to enable the formation of the piezoelectric thin film 4 ) is a ceramic (nitride, oxide) material capable of 10 nm or less, and ⑦ Al _x Ga _{1 - x} N (0.5≤x≤1) Surface condition from which various contaminants are removed so that the piezoelectric thin film 4 can be formed It is preferably a material of

The sacrificial layer 23a may be grown as a high-temperature single-crystal layer (single-layer or multi-layer structure) having a conventional structure including a buffer layer formed by growth at a low temperature.

If necessary, Al _x Ga _{1 - x} N (0.5≤x≤1) sacrificial layers 23a and 23b to secure a single crystal piezoelectric thin film having a tilted c-axis crystal plane before the pressure welding thin film 4 is formed It is also possible to perform photo-lithographic etch patterning processing on the surface of

After deposition of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 , crystallinity and polarity may be improved through an additional on-post annealing process, post-annealing.

As described above, when an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 having a uniform thickness is particularly required, Al _x Ga _{1 - x} N (0.5≤x≤1) The structure shown in Fig. 16 (sapphire deposition substrate 1 - sacrificial layer 23a) laid under the piezoelectric thin film 4, the structure shown in Fig. 17 (sapphire deposition substrate 1 - sacrificial layer 23a - second semiconductor) layer 5), the structure shown in FIG. 18 (sapphire deposition substrate 1 - sacrificial layer 23b) and the structure shown in FIG. 19 (sapphire deposition substrate 1 - sacrificial layer 23b - oxygen (O ₂ ) It is important for the inflow prevention layer (O) to maintain as flatness as possible at the deposition temperature of the Al _x Ga _{1 - x} N (0.5 ≤ x ≤ 1) piezoelectric thin film 4, and the present disclosure provides such a flatness. It provides a foundation to sustain. For example, the sapphire deposition substrate 1 having the sacrificial layer 23a grown by CVD has a convex shape at room temperature. It has a concave shape downward through the state. This behavior is affected by the difference in the coefficient of thermal expansion between the sapphire deposition substrate 1 and the sacrificial layer 23a, and therefore Al _x Ga _1-x N ( 0.5≤x≤1) The vapor deposition of the piezoelectric thin film 4 becomes possible. This principle may be directly applied to the design of the second semiconductor layer 5 , the design of the sacrificial layer 23b , and the design of the oxygen (O ₂ ) inflow prevention layer (O).

20 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film according to the present disclosure, and an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure. As another example, the structure includes a silicon deposition substrate 1 , a stress control layer 23c , and an Al _x Ga _{1 -x} N (0.5≤x≤1) piezoelectric thin film 4 .

Compared with the structure shown in Fig. 16, the stress control layer 23c is grown and deposited by CVD like the sacrificial layer 23a, and the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 is PVD It is the same in that it is deposited by deposition, but that silicon, not sapphire, is used as the deposition substrate 1, and the stress control layer 23c is formed on the silicon deposition substrate 1 rather than by Laser Lift Off (LLO). ) is different in that it is removed together in a process that is removed through etching. Since the silicon deposition substrate 1 has a lattice constant and a coefficient of thermal expansion different from those of the sapphire deposition substrate 1, the stress control layer 23c formed thereon and the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric The film formation conditions of the thin film 4 were set so that cracks do not occur in the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric It is important to control so that the thin film 4 is formed with a uniform thickness. As the silicon deposition substrate 1, for example, an 8 inch Si(111) substrate may be used. Therefore, the stress control layer 23c does not have a restriction that the sacrificial layer 23a must have in order to be laser lift off (LLO), and high quality Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric It is possible to concentrate only on the formation of the thin film 4 .

The stress control layer 23c is a monolayer Al _g Ga _{1 - g} N (0≤g≤1) or a multilayer Al _h1 Ga _{1 - h1} N/ Al _h2 Ga _{1 - h2} N (h ₂ < h ₁ ≤ 1, 0 ≤ h ₂ ≤ 1) may be formed of a group III nitride. The stress control layer 23c prevents and alleviates wafer curvature and cracks caused by a difference in physical properties (lattice constant and thermal expansion coefficient) at a growth temperature with the silicon film-forming substrate 1, etc. Its main role is the stress control function. Above all, in the initial stage of forming the stress control layer 23c, on the surface of the silicon (Si) material of the silicon deposition substrate 1, silicon (Si), group 3 (Al, Ga), group 5 (N) elements and chemical It is important to minimize the formation of intermetallic compounds (Si-Al-(Ga)) and/or silicon nitride (Si(Al,Ga)Nx) through the reaction. Al _x Ga _{1 - x} N (0.5≤x≤1) The piezoelectric thin film 4 is deposited on the sacrificial layer 23c by PVD (eg, sputtering, PLD) at a temperature of 0.3Tm (melting point of the piezoelectric thin film material) or higher. and high quality can be ensured.

The stress control layer 23c may be formed at a temperature of 500° C. or higher, and the upper and lower limits of the thickness are not particularly limited, but preferably Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 It is set to 50nm-3㎛ to be advantageous for the stress control function to maintain the thickness uniformity. For example, the growth film may be formed at a temperature of 500-1100° C. and a pressure of 100-600 torr.

21 is a method for manufacturing an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure; As another example, the structure is sequentially on the silicon deposition substrate 1, the stress control layer 23c, the surface polarity control layer (C), and Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric It includes a thin film (4). It is distinguished from the structure shown in FIG. 20 in that a surface polarity control layer (C) is added, and the surface polarity control layer (C) is formed by CVD (eg, MOCVD, HVPE, ALD, MBE) like the stress control layer 23c. Single or multilayer Al _m1 Ga _{1 - m1} N/Al _m2 Ga _{1 - m2} N _{( m 2} < _{m 1 )} ≤1, 0≤m ₂ ≤1) may be made of a group 3 nitride, Al _x Ga _{1 - x} N (0.5≤x≤1) The surface of the piezoelectric thin film 4 has a single polarity (metallic polarity or nitrogen gas) In addition to the main function of having a polarity), it serves to promote the minimization of crystal defects and control of stress to secure the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 having a uniform thickness. . Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 is deposited on the stress control layer 23c by PVD (eg sputtering, PLD) at a temperature of 0.3Tm (melting point of the piezoelectric thin film material) or higher It is formed into a film to ensure high quality. Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film having a metallic polarity surface through the surface polarity control layer (C) is PVD (eg sputtering, PLD) Al _x Ga _{1 - x} N ( 0.5≤x≤1) Before depositing the piezoelectric thin film 4, the surface polarity control layer (C) is grown and formed by CVD (eg, MOCVD, HVPE, ALD, MBE), and then with a predetermined amount of oxygen (ratio). It can be obtained by plasma treatment (plasma treatment) of the surface of the surface polarity control layer (C). On the other hand, as a method for manufacturing an Al _x Ga _{1 -x} N (0.5≤x≤1) piezoelectric thin film having a nitrogen gas polarity surface through the surface polarity control layer (C), PVD (eg sputtering, PLD) is used as a piezoelectric thin film (4 ), the surface polarity control layer (C) is grown by CVD (MOCVD, HVPE, ALD, MBE) prior to deposition, and magnesium (Mg) is excessively added (doped) to form an Al having a nitrogen gas polarity surface. _x Ga _1-x N (0.5≤x≤1) piezoelectric thin films can be obtained (SCIENTIFIC REPORT, Intentional polarity conversion of AlN epitaxial layers by oxygen, published online: 20 September 2018). Plasma treatment on the surface of the stress control layer 23c or excessive addition (doping) of magnesium (Mg) in the process of growth film formation of Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film ( It is also possible to adjust the polarity of 4).

The surface polarity control layer (C) may be grown and formed at the same constant temperature (500° C. or higher) as the stress control layer 23c, and has a thickness of 0.5 μm or less, Al _x Ga _1-x N at a pressure of 100-600 torr. (0.5≤x≤1) It is preferable to form a group III nitride having the same or similar composition to that of the piezoelectric thin film 4 . In addition, the stress control layer 23c and the surface polarity control layer C are of high quality (crystallinity and polarity) and uniform thickness when the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited. It is desirable to control the film-forming substrate curvature to maintain a zero (flatness) state as much as possible.

The bending state of the film-forming substrate 1 is the film-forming conditions (temperature, pressure) of the thin films 23c, C, 4 to be formed (deposition, growth) thereon, and the silicon-forming base film 1 and the films 23c, C, 4 to be formed. ) is affected by the thermal expansion coefficient (coefficient of thermal expansion is a function of temperature) and the lattice constant, and it is preferable to maintain a zero state, but at least make it an upward convex state, and a downward convex state ( It is important not to be in a concave state, and Since the degree of warpage can be measured during film formation, the film formation conditions (temperature, pressure) and the composition of AlGaN to be formed during film formation can be determined in a state where the warpage of the silicon film substrate 1 is zero or convex, and even after the final film formation. It is important to control it so that it is in a state of being. Considering the thermal expansion coefficient of the silicon film-forming substrate 1 and the thermal expansion coefficient of AlGaN, it is not easy to perform such adjustment only by CVD, and PVD alone forms a high-quality stress control layer 23c, and a high temperature (0.3Tm (660) ℃)), it is not easy to form the Al _x Ga _1-x N (0.5≤y≤1) piezoelectric thin film 4 . According to the present disclosure, the stress control layer 23c and the surface polarity control layer C are grown and formed by CVD, and the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 is deposited and formed by PVD, Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 with excellent crystallinity and polarity is provided despite the use of a silicon film-forming substrate 1 with a large difference in lattice constant and thermal expansion coefficient be able to do

For example, 1) Al _x Ga _{1 - x} N (0.5≤x≤1) When the piezoelectric thin film 4 is deposited with AlN at a temperature of 800°C by PVD (eg, sputtering, PLD), the stress control layer (23c) is 500 nm thick Al ₀ , at a temperature of 500-900° C. and a pressure of 100-600 Torr by CVD (eg, MOCVD) _{. 9 Ga 0.1 N} may be formed. 2) In addition, the surface polarity control layer (C) is CVD (eg, MOCVD) at a temperature of 500-1100 ℃, a pressure of 100-600 Torr, 100nm thick Al _{0 .} When formed of ₉ Ga 0.1 N, Al _x Ga _{1 - x} N ( _0.5≤x≤1 ) piezoelectric thin film ₄ is formed of AlN at a temperature of 800°C by PVD (eg sputtering, PLD) and , the stress control layer 23c is formed by CVD (eg, MOCVD) at a temperature of 500-900° C. and a pressure of 100-600 Torr, 500 nm thick Al _{0 . 8 Ga 0.2 N} may be formed. At this time, the minimum (zero) film formation under the process conditions (temperature and pressure) of growing and forming the stress control layer 23c and/or the surface polarity control layer C by CVD (eg, MOCVD) on the silicon deposition substrate 1 . At the same time, maintaining the warpage of the substrate 1 is of paramount importance, and at the same time, silicon deposition substrate at room temperature (25° C.) after completion of growth of the stress control layer 23c and/or the surface polarity control layer C by CVD (eg MOCVD). (1) It is important to control the warpage to maintain a zero or convex state. In order to have the crystal quality and uniform thickness of the AlN piezoelectric thin film 4 that is subsequently deposited by PVD (eg, sputtering) on the stress control layer 23c and/or the surface polarity control layer C, the above-described film formation It may be possible by controlling the conditions and the behavior of the silicon deposition substrate 1 according to the warpage in a recognized state.

The crystalline quality of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 structure manufactured according to the method shown in FIGS. 20 to 21 is commonly X-ray Rocking Curve (XRC) ) has the advantage of having a full width at half maximum of 0.1° or less, and the polar quality can be freely adjusted according to the surface state of the stress control layer 23c and/or the surface polarity control layer C.

The stress control layer 23c and the surface polarity control layer C are composed of a group III nitride formed by ① CVD (MOCVD, HVPE, ALD, MBE), ② Al _x Ga _{1 - x} N (0.5≤x≤1) To enable high-temperature deposition of the piezoelectric thin film 4, it must be a material having thermal stability at 0.3Tm (660°C) or higher, and ③ Al _x Ga _{1 - x} N (0.5≤ x≤1) a material having the same or similar crystal structure as the piezoelectric thin film 4, and ④ Al _x Ga _{1 - x} N (0.5≤x≤1) surface roughness to enable deposition of the piezoelectric thin film 4 roughness) is a ceramic (nitride) material capable of 10 nm or less, and ⑤ Al _x Ga _{1 - x} N (0.5≤x≤1) Surface state from which various contaminants are removed to enable deposition of the piezoelectric thin film 4 It is preferably a material of

If necessary, a stress control layer 23c to secure a single crystal piezoelectric thin film having a tilted c-axis crystal plane before deposition of Al _x Ga _{1 - x} N (0.5≤x≤1) pressure welding thin film 4 And/or it is also possible to perform a photo-lithographic etch patterning process on the surface of the surface polarity control layer (C).

Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 deposited on the silicon film substrate 1 by deposition subsequent to the stress control layer 23c and/or the surface polarity control layer C Unlike the conventional piezoelectric thin film deposited by PVD (eg sputtering, PLD) at low temperature (around 400℃)), higher quality is achieved with a high-temperature single-crystal crystal structure deposited at 0.3Tm (660℃) or higher. have

After deposition of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4, it is also possible to further improve crystallinity and polarity through post-annealing, which is an additional high-temperature subsequent heat treatment process. .

It is preferable to preferentially grow and form an AlGaN thin film in which the gallium (Ga) component is minimized along with temperature control of the stress control layer 23c from a temperature of 500° C. or higher to a low/medium/high temperature, which is a material of the deposition substrate 1 This is to prevent a melt-back phenomenon by suppressing a reaction between silicon (Si) and gallium (Ga), which relatively easily forms an intermetallic compound.

An intermediate layer having a superlattice structure may be introduced between the stress control layer 23c and the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 to suppress crystal defects.

Al _x Ga _{1 - x} N (0.5≤x≤1) While increasing the Al content during deposition of the piezoelectric thin film 4, the deposition temperature of PVD can be increased, which suppresses tensile stress This is to prevent microcracks in the piezoelectric thin film 4 .

The method for manufacturing the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 structure using the silicon film-forming substrate 1 may be used as it is in the methods shown in FIGS. 11 to 15 . However, the silicon (Si) deposition substrate 1, the stress control layer 23c, and the surface polarity control layer C are not laser lift off (LLO), but wet etch and well-known. It is different in that it is removed through a parallel dry etch. In this process, a trimming process for accurate thickness adjustment may be accompanied.

22 and 23 are views showing another example of a method of manufacturing a resonator using an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure, a silicon film-forming substrate ( 1), a stress control layer 23c and a surface polarity control layer 3 are provided, but by adding (doping) magnesium (Mg) to the surface polarity control layer 3, Al _x Ga _{1 - x} N (0.5 ≤x≤1) After the piezoelectric thin film 4 is formed to have a nitrogen gas polarity surface, the second electrode 14, the Bragg reflector 10 reflector, the second protective film 11, the second bonding layer 12 and A device substrate 13 is formed, and the silicon film-forming substrate 1, the stress control layer 23c, and the surface polarity control layer 3 are combined with an Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 . After removal from the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 structure forming the first electrode 6 is presented. Through this, as in FIGS. 11 to 13, the metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface is formed without using two wafer bonding processes, that is, through one wafer bonding process. It is possible to provide a structure of the Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric thin film 4 used as the upper surface of the device.

In the resonator-based device manufactured according to the present disclosure, the position at which the second electrode 14 including the Bragg reflector 10 is formed is formed on the silicon (Si) deposition substrate 1 Al _x Ga _{1 - x} N (0.5≤x≤1) Al _x Ga _{1 -x} N (0.5≤x≤1) depending on the number of wafer bonding in the process of polarity control of the piezoelectric thin film and subsequent device processing The surface polarity can be freely selected on the piezoelectric thin film 4 . The method shown in FIGS. 11 to 13 is manufactured through two wafer bonding processes, and the second electrode 14 including the Bragg reflector 10 reflector is Al _x Ga _{1 - x} N (0.5≤x≤1) piezoelectric The second electrode 14 including the Bragg reflector 10 reflector is placed on the nitrogen gas polarity face of the thin film 4 and also in the case of the method shown in FIGS. 22 and 23 that undergoes a single wafer bonding process. ) Al _x Ga _{1 - x} N (0.5≤x≤1) is equally positioned on the nitrogen gas polarity face of the piezoelectric thin film 4 (N-polarity face). For reference, in the case of a resonator device made of a polycrystalline AlN piezoelectric thin film formed through PVD (eg, sputtering, PLD) directly at low temperature on a conventional Si film-forming substrate, there is a limit to controlling the surface polarity and polarity ratio Since there is a Bragg reflector 10, the polarity position of the second electrode 14 including the reflector cannot be defined. Due to this, irrespective of the positive/negative crystallinity, the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) resonator performance improvement is due to the difficulty in manufacturing a mixed polarity and polarity-controlled device. It has limitations.

24 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure, wherein the structure is a sapphire film-forming substrate 1, a GaN sacrificial layer 3, and Sc _x Al _{1 - x} N piezoelectric thin film (4). Referring to FIG. 5 , a piezoelectric thin film structure including a sapphire deposition substrate 200 , a sapphire deposition substrate 200 , a GaN buffer layer 210 and an AlN piezoelectric thin film 220 has been mentioned, and a GaN buffer layer 210 . Silver has the advantage of facilitating separation of the optically transparent sapphire deposition substrate 200 and the AlN piezoelectric thin film 220 because it can sufficiently serve as a sacrificial layer, but the GaN buffer layer 210 and the AlN piezoelectric thin film Since there is a significant difference in physical properties of lattice constant and thermal expansion coefficient between 220, a high-purity single crystal AlN piezoelectric thin film 220 grown by MOCVD to a certain critical thickness (approximately 100 nm) that can be used as a functional piezoelectric thin film such as a resonator. It has been pointed out that it is by no means easy with known processes and technologies to secure

As shown in Fig. 25 (a), by using Sc _x Al _{1 - x} N instead of Al _x Ga _{1 - x} N (0.5≤x≤1) as the piezoelectric thin film 4, the GaN sacrificial layer 3 and (Source: ScGaN and ScAlN: emerging nitride materials; Journal of Materials Chemistry A, Issue 17, 2014). In addition, it can be seen that the bandgap energy of Sc _x Al _{1 - x} N is larger than that of Al _x Ga _{1 - x} N at the same lattice constant value, and thus the separation of the GaN sacrificial layer 3 in the LLO process is reduced. By providing a basis for using the Al _x Ga _{1 - x} N sacrificial layer 3 instead of the GaN sacrificial layer 3 and using the Al _x Ga _{1 - x} N sacrificial layer 3 , It is possible to reduce the difference between the lattice constant and the thermal expansion coefficient between the sacrificial layer 3 and the piezoelectric thin film 4 . From the viewpoint of the quality of the thin film, it is preferable to use the GaN sacrificial layer 3 rather than the Al _x Ga _1-x N sacrificial layer 3 . When the x value of Sc of Sc _x Al _{1 - x} N is around 0.18, it has the same lattice constant value as that of GaN.

In addition, as shown in Fig. 25(b), the theoretical value of Critical thicknesses for strain relaxation by dislocation glide is limited in the case of Sc _x Al _{1 - x} N (x=0.18)/GaN It can be seen that there is no, and therefore, the Sc _x Al _{1 - x} N piezoelectric thin film 4 on the GaN sacrificial layer 3 can be formed to a thickness of 100 nm or more, which is the critical thickness of the piezoelectric thin film 4 when used in a resonator, etc. (Source: ScGaN and ScAlN: emerging nitride materials; Journal of Materials Chemistry A, Issue 17, 2014).

On the other hand, in the case of Sc _x Al _{1 - x} N, it is known to have a better piezoelectric modulus d33 and spontaneous polarization coefficient compared to AlN, for example, Sc _{0 . 43} Al _{0 .} In the case of ₅₇ N, it is known to have a factor of three enhancement in piezoelectric modulus d33 and spontaneous polarization coefficient 5 times (Source: Epitaxial ScAlN grown by molecular beam epitaxy on GaN and SiC substrates; APPLIED PHYSICS LETTERS 110, 162104 (2017) )).

In the present disclosure, the upper limit of the _x value of the Sc _x Al _{1 -x} N piezoelectric thin film 4 is a value in which Sc _x Al _{1 - x} N has the same lattice structure as Al _x G _{1 -x} N. , which is usually known as x = 0.56.

Instead of the sapphire deposition substrate 1, a silicon deposition substrate 1 may be used, wherein the sacrificial layer 3 also serves as a stress control layer 23c, as shown with reference to FIG.

As shown in FIG. 16 , the sacrificial layer 3 is a single layer of Al _c Ga _{1 - c} N (0≤c≤0.5) or a multi-layered Al _c1 Ga _{1 - c1} formed by growth and deposition by CVD (MOCVD, ALD, MBE, etc.). N/Al _c2 Ga _{1 - c2} N (c ₂ <c ₁ ≤1, 0≤c ₂ <0.5) may be formed of a group III nitride. For example, the growth film may be formed at a temperature of 500-1100° C. and a pressure of 100-600 torr. When the silicon deposition substrate 1 is used, the sacrificial layer 3 is a single layer Al _g Ga _{1 - g} N (0≤ g≤1) or multi-layered Group III nitride of Al _h1 Ga _{1 - h1} N/Al _h2 Ga _{1 - h2} N (h ₂ < h ₁ ≤ 1, 0≤ h ₂ ≤ 1). The sacrificial layer 3 prevents and alleviates wafer curvature and cracks caused by the difference in physical properties (lattice constant and coefficient of thermal expansion) at the growth temperature with the silicon deposition substrate 1 . Stress control function is the main role. Above all, in the initial stage of forming the sacrificial layer 3, a chemical reaction with silicon (Si) and group 3 (Al, Ga) and 5 group (N) elements on the surface of the silicon (Si) material of the silicon deposition substrate 1 It is important to minimize the formation of intermetallic compounds (Si-Al-(Ga)) and/or silicon nitride (Si(Al,Ga)Nx).

In order to form a Sc _x Al _{1 - x} N piezoelectric thin film 4 on the sacrificial layer 3 using the MOCVD growth method, a scandium (Sc) source is sufficiently injected into the MOCVD chamber. At the same time, a chemical reaction must be actively performed, and for this purpose, an accelerating device having high vapor pressure is required. At the same time, it is preferable to use a solid-state source with better injection efficiency than a metal-organic source for this purpose and to heat the source injection path at a high temperature within the range of 100-200°C. . In particular, the scandium solid source uses a Cp ₃ Sc or MeCp ₃ Sc precursor. For example, in the case of MOCVD, in order to form a Sc _x Al _{1 - x} N piezoelectric thin film 4 on the sacrificial layer 3 using the MOCVD growth method, a growth temperature of 900-1200° C., a growth pressure of 10-100 mbar, Group 5/3 element source injection ratio (V/III Ratio) 1000-5000, and carrier gas such as hydrogen (H ₂ ) or nitrogen (N ₂ ) are maintained at 10-40 slm level to grow 50-500 nm It is also desirable to perform Growth Rate. In the case of MBE, high-quality Sc _x Al _{1 - x} on the sacrificial layer 3 at a growth rate of 150-300 nm/h under the growth temperature of 600-1000 ° C and the group 5/3 element injection ratio (V/III Ratio) 0.7-1.5 conditions. It is preferable to grow and form the N piezoelectric thin film 4 . As another example, in the case of sputter, a high-quality Sc _x Al _{1 - x} N piezoelectric thin film (4) through pulsed DC or RF sputtering on the sacrificial layer (3) formed by MOCVD or MBE growth method on the growth substrate (1) It is preferable to grow and form a film. In particular, in the case of pulsed DC sputtering, aluminum (Al) and scandium (Sc) metal targets having a purity of 99.99% or more are prepared, argon (Ar) and nitrogen (N2) mixed gas and 60-90% nitrogen partial pressure A high-quality Sc _x Al _1-x N piezoelectric thin film 4 is grown and formed in an atmosphere of (N2 Partial Pressure). The scandium composition (x) in the high-quality Sc _x Al _1-x N piezoelectric thin film 4 is controlled by adjusting the DC power ratio applied to the Al & Sc target. Factors affecting quality, such as internal residual stress, crystalline quality, crystallographic orientation, microstructure, and surface polarity of a conventionally formed piezoelectric thin film ), the target-to _- substrate distance, N2 Partial Pressure, and the growth substrate temperature (Processing Temperature), It is preferable to grow and form the _1-x N piezoelectric thin film 4 .

26 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure, wherein the structure is different from the example shown in FIG. 24 , the second semiconductor as shown in FIG. 17 . A layer (5) is added. Unlike the example shown in FIG. 17 , the second semiconductor layer 5 is not made of AlGaN, but is made of Sc _y Al _{1 - y} N, and the GaN sacrificial layer 3 and the Sc _x Al _{1 - x} N piezoelectric thin film ( 4) It plays a role in buffering the stress between Basically, since the lattice constant values of the GaN sacrificial layer 3 and the Sc _x Al _{1 - x} N piezoelectric thin film 4 are designed to be the same or similar, the second semiconductor layer 5 made of Sc _y Al _{1 - y} N The y value can also be set (eg 0.18±0.8) in consideration of this. The thickness of the second semiconductor layer 5 is formed thin (eg, 100 nm or less), and the lattice constant and the bandgap energy are determined according to the y value of the Sc composition, and thus the lower layer sacrificial The layer (3) is closely related to the thermo-mechanical deformation with the upper layer Sc _x Al _1-x N piezoelectric thin film (4).

On the other hand, in the examples shown in FIGS. 24 and 26 , instead of the GaN sacrificial layer 3 , a single-layer Al _x3 Ga _{1 - x3} N sacrificial layer 3 may be used, and as shown in FIG. 25( a ) , taking into account the lattice constants of the deposition substrate 1 and the Sc _x Al _{1 - x} N piezoelectric thin film 4, x ₃ values less than 0.5 are used. In addition, a multi-layered Al _x4 Ga _{1 - x4} N/Al _x5 Ga _{1 - x5} N (x ₄ <x ₅ ≤1, 0≤x ₄ <0.5) sacrificial layer 3 may be used, and the multi-layered Al _x4 Ga _{1 - x4} N/Al _x5 Ga _{1 - x5} N (x ₄ <x ₅ ≤ 1, 0≤x ₄ <0.5) The Al content of the entire sacrificial layer 3 should be maintained at less than 0.5. Through this, the lattice constant of the sacrificial layer 3 can be adjusted to a larger value than that of GaN, and thus the lattice constant and bandgap energy of the Sc _x Al _{1 - x} N piezoelectric thin film 4 can be changed accordingly. have The composition of the second semiconductor layer 5 may also be adjusted accordingly. Single layer Al _x3 Ga _{1 - x3} N or multilayer Al _x4 Ga _{1 -x4} N/Al _x5 Ga _1-x5 N (x ₄ <x ₅ ≤1, 0≤x ₄ <0.5) Using the sacrificial layer (3) By doing so, the Sc composition of the Sc _x Al _{1 - x} N piezoelectric thin film 4 can be increased, and the piezoelectric performance can be improved.

27 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure, and a seed layer (3a) on the sacrificial layer 3 in addition to the structure shown in FIG. 24; ) is provided.

28 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure, and a seed layer (3a) on the sacrificial layer 3 in addition to the structure shown in FIG. 26; ) is provided.

The seed layer (3a) is on the sacrificial layer (3) made of a GaN-based nitride, the Sc _x Al _{1 - x} N piezoelectric thin film 4 and Sc _y Al _{1 - y} N of the second semiconductor layer 5 of the film formation serves to help The seed layer (3a) may be made of Al _x6 Ga _{1 - x6} N (0.5≤x ₆ ), and the thickness is preferably 5 nm or less. When the seed layer (3a) is introduced, the sacrificial layer (3a) can be used in addition to GaN and AlGaN (Al)GaInN, the lattice constant is Al _x3 Ga _{1 - x3} N (x ₃ = 0.5) when is formed to remain less than the value. Al _x6 Ga _{1 - x6} N (0.5≤x ₆ ) While the Sc _x Al _{1 - x} N piezoelectric thin film 4 is refined through the seed layer 3a, the Al composition value of the sacrificial layer 3 is set to 0.5 or less. It is possible to facilitate laser lift-off (LLO).

29 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure, and instead of the GaN-based nitride sacrificial layer 3 shown in FIG. 24, Sc _z Al _{1 -} A _z N sacrificial layer 3 is introduced. Sc _z Al _{1 -z} N Sc composition ( _z ) of the sacrificial layer 3 is designed in consideration of the Sc composition (x) of the Sc _x Al _{1 - x} N piezoelectric thin film 4, the removal of the deposition substrate (1) For , it may be designed to have a value smaller than the composition (x). By adding Sc to the sacrificial layer 3, as shown in Fig. 25(a), the lattice constant of the sacrificial layer 3 can be moved to a larger side than that of GaN, and the second semiconductor having a large lattice constant thereon It becomes possible to provide a basis for forming the layer 5 or the Sc _x Al _1-x N piezoelectric thin film 4 .

30 is a view showing another example of a method for manufacturing a piezoelectric thin film and a piezoelectric thin film structure according to the present disclosure. Instead of the GaN-based nitride sacrificial layer 3 shown in FIG. 26, Sc _z Al _{1 -} A _z N sacrificial layer 3 is introduced, the second semiconductor layer 5 can serve as a stress relief layer and/or a seed layer (see FIG. 28 ), and thus Sc _y Al _{1 - y} N or Al _x6 Ga _{1 - x6} N (0.5≤x ₆ ). However, unlike the example shown in FIG. 28 , there is no particular limitation on the thickness.

On the other hand, when the Sc _z Al _{1 -z} N sacrificial layer 3 is used, when the Sc composition ( _x ) of the Sc _x Al _{1 - x} N piezoelectric thin film 4 is 0, that is, the AlN piezoelectric thin film 4 is formed into a film. Of course you can. Therefore, the Sc composition (x) of the Sc _x Al _{1 - x} N piezoelectric thin film 4 according to the present disclosure may have a value from x = 0 to a value having a wurzite structure (theoretically x = 0.56).

Hereinafter, various embodiments of the present disclosure will be described.

(1) A method of manufacturing a piezoelectric thin film made of Sc _x Al _{1 - x} N, the method comprising: forming a sacrificial layer for removing the deposition substrate on the deposition substrate; And, forming a Sc _x Al _{1 - x} N piezoelectric thin film of a wurzite structure on the sacrificial layer; Method of manufacturing a piezoelectric thin film comprising a.

(2) forming a stress relief layer between the sacrificial layer and the Sc _x Al _{1 - x} N piezoelectric thin film; Method of manufacturing a piezoelectric thin film further comprising a.

(3) forming a seed layer of Al _x6 Ga _{1 - x6} N (0.5≤x ₆ ) on the sacrificial layer; Method of manufacturing a piezoelectric thin film further comprising a.

(4) The sacrificial layer is a method of manufacturing a piezoelectric thin film composed of Al _x3 Ga _{1 - x3} N (0≤x ₃ <0.5) or Sc _z Al _{1 -z} N ( _z≤0.56 ).

(5) A method of manufacturing a piezoelectric thin film in which the sacrificial layer is made of GaN.

(6) The stress relief layer is Sc _y Al _{1 - y} N (y≤0.56) method of manufacturing a piezoelectric thin film.

(7) separating the film-forming substrate from the Sc _x Al _{1 - x} N piezoelectric thin film; Method of manufacturing a piezoelectric thin film further comprising.

According to the present disclosure, there is provided a method for manufacturing a piezoelectric thin film in which a difference in lattice constant between a sacrificial layer and a piezoelectric thin film is reduced, and a device using the thin film.

Film formation substrate (1), sacrificial layer (3), piezoelectric thin film (4), second semiconductor layer (5)

Claims (8)

In the method of manufacturing a piezoelectric thin film of Sc _x Al _1-x N (0≤x≤0.56),
forming a sacrificial layer for removing the deposition substrate on the deposition substrate; and,
Including; forming a Sc _x Al _1-x N (0≤x≤0.56) piezoelectric thin film of wurzite structure on the sacrificial layer;
Forming a stress relief layer between the sacrificial layer and the Sc _x Al _1-x N (0≤x≤0.56) piezoelectric thin film; further comprising,
Separating the deposition substrate from the Sc _x Al _1-x N (0≤x≤0.56) piezoelectric thin film through the LLO process; further comprising,
The stress relief layer is made of Sc _y Al _1-y N, and the y value of Sc is 0.56 or less in consideration of the lattice constant value of the sacrificial layer and Sc _x Al _1-x N (0≤x≤0.56) piezoelectric thin film. However, the method of manufacturing a piezoelectric thin film, which is set to have a bandgap energy greater than that of the sacrificial layer. delete delete The method according to claim 1,
Forming a seed layer of Al _x6 Ga _1-x6 N (0.5≤x ₆ ) on the sacrificial layer; Method of manufacturing a piezoelectric thin film further comprising a. The method according to claim 1,
The sacrificial layer is a method of manufacturing a piezoelectric thin film made of Al _x3 Ga _1-x3 N (0≤x ₃ <0.5) or Sc _z Al _1-z N (z≤0.56). delete delete delete

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