KR102454388B1 - Transistor array and Display Device - Google Patents

Abstract

The present invention provides a transistor array including N (N is an integer greater than or equal to 2) transistors disposed adjacent to each other. The N transistors all have gate electrodes connected in common and share one channel provided as one active layer.

Description

Transistor array and display device using same

The present invention relates to a transistor array and a display device using the same.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of various types of display devices such as an electroluminescent display device, a liquid crystal display device, and a plasma display device is increasing.

The display device includes a display panel including a plurality of sub-pixels, a driving unit for driving the display panel, and a power supply unit for supplying power to the display panel. The driver includes a scan driver that supplies a scan signal (or a gate signal) to the display panel and a data driver that supplies a data signal to the display panel.

In some display devices, when a scan signal and a data signal are supplied to the transistor array included in the sub-pixels, light is emitted or emitted from the selected sub-pixel to display an image.

Among the display devices described above, the electroluminescent display device implements sub-pixels based on a light emitting diode, a transistor, and a capacitor, and a compensation circuit including a plurality of transistors is required for device compensation.

However, when the compensation circuit is implemented according to the conventionally proposed method, there are structural disadvantages that are disadvantageous in terms of high resolution and high integration as well as a decrease in the space efficiency of device arrangement, so improvement is required.

The present invention for solving the problems of the above-mentioned background art provides a space by more efficiently configuring and arranging a switching transistor occupying a large area in a circuit, and utilizing the space for the arrangement of other structures to provide a space efficiency of device arrangement of course, it is to provide advantageous advantages for high resolution and high integration.

As a means of solving the above problems, the present invention provides a transistor array including N (N is an integer greater than or equal to 2) transistors disposed adjacent to each other. The N transistors all have gate electrodes connected in common and share one channel provided as one active layer.

In another aspect, the present invention provides an electroluminescent display device including sub-pixels including N (N is an integer greater than or equal to 2) transistors disposed adjacent to each other and a display panel displaying an image based on the sub-pixels. The N transistors all have gate electrodes connected in common and share one channel provided as one active layer.

According to the present invention, it is possible to more efficiently configure and arrange a switching transistor occupying a large area in a compensation circuit of a sub-pixel to provide a space, and utilize the space for arrangement of other structures to increase the space efficiency of device arrangement, of course. There is an effect of providing advantageous advantages for high resolution and high integration.

1 is a schematic block diagram of an organic light emitting display device;
2 is an exemplary diagram schematically illustrating a cross-section of a display panel;
3 is a schematic circuit configuration diagram of a sub-pixel;
4 is an exemplary diagram illustrating a connection structure of transistors proposed in the prior art;
Figure 5 is a cross-sectional view of Figure 4 (b).
6 is a view for explaining the structure of the first transistor shown in FIG.
7 is an exemplary diagram illustrating a connection structure of transistors according to the first embodiment;
Fig. 8 is a cross-sectional view of Fig. 7(b).
9 is an exemplary diagram illustrating a connection structure of transistors according to a second embodiment.
10 is an exemplary circuit configuration diagram of sub-pixels having a compensation circuit;
11 is an exemplary view in which one of the sub-pixels of FIG. 10 is implemented according to the prior art;
12 is an exemplary view of one of the sub-pixels of FIG. 10 implemented according to the present invention;
13 is a view for explaining a comparison between the prior art and the present invention;

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

The electroluminescent display device described below may be implemented as a TV, an image player, a personal computer (PC), a home theater, a smart phone, a virtual reality device (VR), and the like. In addition, as an electroluminescent display device to be described below, an organic light emitting display device implemented based on an organic light emitting diode (light emitting device) will be described as an example. However, the electroluminescent display device described below may be implemented based on an inorganic light emitting diode.

Finally, the thin film transistor of the electroluminescent display device described below can be named as a source electrode and a drain electrode or a drain electrode and a source electrode depending on the type (N-type or P-type) except for the gate electrode. In order not to do so, the first electrode and the second electrode will be described.

1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is an exemplary diagram schematically illustrating a cross-section of a display panel, and FIG. 3 is a schematic circuit configuration diagram of a sub-pixel.

1 , the organic light emitting display device includes an image processing unit 110 , a timing control unit 120 , a data driving unit 130 , a scan driving unit 140 , a display panel 150 , and a power supply unit 160 . Included.

The image processing unit 110 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processing unit 110 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description.

The timing controller 120 receives the data signal DATA from the image processing unit 110 as well as a driving signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130 based on the driving signal. to output

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 , converts it into a gamma reference voltage, and outputs it. . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an integrated circuit (IC).

The scan driver 140 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 140 outputs a scan signal through the scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or is formed in the display panel 150 in the form of a gate in panel.

The power supply unit 160 outputs a high potential voltage, a low potential voltage, and the like. The high potential voltage and low potential voltage output from the power supply unit 160 are supplied to the display panel 150 . The high potential voltage is supplied to the display panel 150 through the first power line VDD, and the low potential voltage is supplied to the display panel 150 through the second power line VSS.

The display panel 150 displays an image corresponding to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140 , and the power supplied from the power supply unit 160 . The display panel 150 includes sub-pixels SP that operate to display an image.

As shown in FIG. 2 , the display panel 150 includes a first substrate (or a thin film transistor substrate) 150a, a display area AA in which pixels P for displaying an image are disposed, and a non-displaying image. and a non-display area NA and a second substrate (protective substrate or protective film) 150b. The first substrate 150a and the second substrate 150b may be selected from a material having rigidity such as glass or a material having flexibility such as resin.

The pixels P may include sub-pixels arranged in the order of red (R), white (W), blue (B), and green (G) on the display area AA. However, the arrangement order of the sub-pixels may be variously changed depending on the light emitting material, the light emitting area, the configuration (or structure) of the compensation circuit, and the like.

Pixels P are defined as sub-pixels of red (R), white (W), blue (B) and green (G) as shown, or alternatively, red (R), green (G) and blue ( It can be defined as the sub-pixels of B). The sub-pixels may be implemented such that the color of the emitted light is determined according to the material of the light emitting layer positioned between the two electrodes or the material of the color filter that changes the light emitted from the light emitting layer. That is, the pixels P may be implemented in various forms according to the characteristics of the sub-pixels.

As shown in FIG. 3 , one sub-pixel includes a switching transistor T1 , a driving transistor DT, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode (OLED). Except for the organic light emitting diode (OLED), the switching transistor T1 , the driving transistor DT, the capacitor Cst, and the compensation circuit CC are included in the transistor array. In addition, the compensation circuit CC may be omitted depending on the implementation method of the sub-pixel.

The switching transistor T1 performs a switching operation so that the data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to the scan signal supplied through the first scan line GL1 . The driving transistor DT operates so that a driving current flows between the first power line VDD (high potential voltage) and the second power line VSS (low potential voltage) according to the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light according to a driving current formed by the driving transistor DR.

The compensation circuit CC is a circuit added in the sub-pixel to compensate for the threshold voltage of the driving transistor DR. In FIG. 3 , a sub-pixel having a 2T (Transistor) 1C (Capacitor) structure including a switching transistor T1 , a driving transistor DT, a capacitor Cst, and an organic light emitting diode (OLED) has been described as an example.

However, the structure may be changed to 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 8T1C, etc. according to the configuration of the compensation circuit CC. As such, the compensation circuit CC may be configured with one or more transistors, but may be configured in many different forms depending on a compensation method.

In FIG. 2 , the switching transistor T1 and the driving transistor DT are illustrated as an example of the N-type turned on by the positive voltage, but it may be selected as the P-type turned on by the negative voltage. Hereinafter, parts related to the present invention will be illustrated and described based on transistors included in the compensation circuit CC, but a P-type transistor will be taken as an example.

<Conventional>

FIG. 4 is an exemplary view showing a connection structure of transistors proposed in the prior art, FIG. 5 is a cross-sectional view of FIG. 4(b), and FIG. 6 is a view for explaining the structure of the first transistor shown in FIG.

As shown in FIG. 4 , an example of using two transistors M1 and M2 when implementing a compensation circuit has been conventionally proposed. The gate electrodes of the first and second transistors M1 and M2 are commonly connected to each other, and the drain electrode to the drain electrodes are commonly connected to each other.

In this structure, the two transistors M1 and M2 are simultaneously turned on by the voltage applied to the gate electrode. And, by the simultaneous turn-on operation of the two transistors M1 and M2, the A-th node (A), the B-th node (B), and the C-th node (C) are simultaneously electrically connected (conducted). At this time, that the three nodes (A ~ C) are connected means that the signal or voltage of the A-th node (A) is the C-th node (C), and the signal or the voltage of the B-th node (B) is the C-th node (C). It can be interpreted as , or that the signal or voltage of the C-th node (C) is branched into the A-th node (A) and the B-th node (B).

Conventionally, in order to implement the first and second transistors M1 and M2 connected as shown in FIG. 4A , one gate metal layer GATE is disposed thereon. However, in the conventionally proposed structure, as shown in FIG. 5 , the active layers ACT(M1) and ACT(M2) are formed for each region of the transistors to have separate channels.

5 and 6 , an active layer ACT is formed on the first substrate 150a, a gate insulating layer GI is formed on the active layer ACT, and a gate insulating layer GI is formed on the gate insulating layer GI. A gate metal layer GATE is formed. In FIG. 5 , ACT( M1 ) becomes an active layer of the first transistor M1 , and ACT( M2 ) becomes an active layer of the second transistor M2 .

The active layers ACT(M1) and ACT(M2) are selected from oxide materials. The active layers ACT(M1) and ACT(M2) selected as oxide materials undergo a metallization process, and the region (non-exposed region) protected by the gate metal layer GATE becomes the channel region CH, but the remaining exposed regions Silver becomes a metal layer that can act as an electrode, such as the source and drain electrode layers (SOURCE, DRAIN).

According to the experimental results, the conventionally proposed structure has the advantage that it can be applied to a compensation circuit requiring simultaneous driving because the gate electrodes of the first and second transistors M1 and M2 are commonly connected. However, in the conventionally proposed structure, the first and second transistors M1 and M2 are implemented so as to have separate channels, so space efficiency of device arrangement is lowered, and it has been shown to have structural disadvantages that are disadvantageous for high resolution and high integration.

Hereinafter, an embodiment of the present invention prepared through an experiment based on the prior art will be described as follows.

<Example>

7 is an exemplary view illustrating a connection structure of transistors according to the first embodiment, and FIG. 8 is a cross-sectional view of FIG. 7(b).

As shown in FIG. 7 , the first embodiment proposes an example of using three transistors M1 , M2 , and M3 when implementing the compensation circuit. The gate electrodes of the first to third transistors M1 to M3 are connected to each other, and the source and drain electrodes of the first to third transistors M1 to M3 are connected to the source electrode or drain electrode of the adjacent transistor. .

In this structure, the three transistors M1 to M3 are simultaneously turned on by the voltage applied to the gate electrode. And, by the simultaneous turn-on operation of the three transistors M1 to M3, the A-th node (A), the B-th node (B), and the C-th node (C) are electrically connected (conducted) at the same time. At this time, that the three nodes (A ~ C) are connected means that the signal or voltage of the A-th node (A) is the C-th node (C), and the signal or the voltage of the B-th node (B) is the C-th node (C). It can be interpreted as , or that the signal or voltage of the C-th node (C) is branched into the A-th node (A) and the B-th node (B).

Some of the above explanations are explained by adding formulas as follows.

TFT ON: Vg - Vs (the lowest voltage among the three node voltages = Vref) ＜ Vth -> Short-circuited all nodes A to C (A to C)

TFT OFF : Vg - Vs (highest voltage among the three node voltages) > Vth -> All nodes A to C (A to C) are open

In the first embodiment, one gate metal layer GATE is disposed on the first to third transistors M1 to M3 connected as shown in FIG. 7A . And, as shown in FIGS. 7(b) and 7(c), the first to third transistors M1 to M3 share one channel provided with one active layer ACT(M1) to ACT(M3). Here's how to do it:

Referring to FIG. 7(b), the A-th node (A) and the B-th node (B) are disposed to be spaced apart from each other in the vertical direction, and lower ends of both ends are connected. The C-th node (C) starts from the center of the point where the connection between the A-th node (A) and the B-th node (B) is made and protrudes in the vertical direction.

As a result, the A-th node (A) and the B-th node (B) have a shape (c) rotated 90 degrees to the left or a U-shape, and the C-th node (C) has a straight (1) shape or I has the shape of a The gate metal layer GATE is disposed in a horizontal direction along a connection point (or an end of each node) to which all of the A to Cth nodes A to C are connected.

According to the structure of FIG. 7(b), the first, third, and second transistors M1, M3, and M2 are horizontally arranged at the connection points to which the A to C-th nodes A to C are connected, and the transistors are in the order of M1, M3, and M2. are placed And the overall shape of the A to C-th nodes (A to C) has a shape similar to the capital letter Y.

Referring to FIG. 7(c), the A-th node (A) and the B-th node (B) are disposed to be spaced apart from each other in the vertical direction, and the lower ends of both ends are connected. The C-th node (C) starts from the left side (or the end of the A-th node) of the point where the connection between the A-th node (A) and the B-th node (B) is made and protrudes in the vertical direction.

As a result, the A-th node (A) and the B-th node (B) have a shape (c) rotated 90 degrees to the left or a U-shape, and the C-th node (C) has a straight (1) shape or I has the shape of a The gate metal layer GATE is disposed in a horizontal direction along a connection point to which all of the A to Cth nodes A to C are connected.

According to the structure of FIG. 7(c), the first, third and second transistors M1, M3, and M2 are disposed at the connection points to which the A to C-th nodes A to C are connected, the first and The third transistors M1 and M3 are disposed vertically (partial regions may overlap), and the second transistor M2 is disposed at the end of the B-th node B. As shown in FIG. And the overall shape of the A to C nodes (A to C) has a shape in which the lowercase letter y is symmetrically moved in the horizontal direction.

Conventionally, as shown in FIG. 5, an active layer is formed for each region of the transistors to have separate channels. However, in the first embodiment, unlike the prior art, one active layer is formed to be shared by all transistors, which will be described as follows.

8, an active layer ACT is formed on the first substrate 150a, a gate insulating layer GI is formed on the active layer ACT, and a gate metal layer (GI) is formed on the gate insulating layer GI. gate) is formed. In FIG. 8 , ACT(M1) is the active layer of the first transistor M1, ACT(M3) is the active layer of the third transistor M3, and ACT(M2) is the active layer of the second transistor M2. becomes the active layer.

The active layers ACT(M1), ACT(M3) and ACT(M2) are selected from oxide materials. The active layers ACT(M1), ACT(M3), and ACT(M2) selected as oxide materials undergo a metallization process, and the region (non-exposed region) protected by the gate metal layer GATE is the channel region CH. However, the remaining exposed region becomes a metal layer that can act as an electrode, such as the source and drain electrode layers.

According to the experimental results, in the structure of the first embodiment, the gate electrodes of the first to third transistors M1 to M3 are connected in common, so that the structure can be applied to a compensation circuit requiring simultaneous driving. In addition, in the structure of the first embodiment, since the first to third transistors M1 to M3 are implemented to share a unified channel, when a plurality of switching transistors are required, the space efficiency of device arrangement (since it occupies a small area) is increased. It has been shown to have structural advantages advantageous for high resolution and high integration.

<Second embodiment>

9 is an exemplary diagram illustrating a connection structure of transistors according to a second embodiment.

As shown in FIG. 9 , the second embodiment proposes an example of using N (N is an integer greater than or equal to 2) transistors when implementing the compensation circuit. In FIG. 9 , three transistors having all gate electrodes connected in common are taken as an example.

However, the third transistor M3 may be omitted, or two transistors like the first and second transistors may be positioned in place of the third transistor. However, in the following description, three transistors will be mainly described, but if necessary, a case implemented with two transistors will also be described.

The gate electrodes of the first to third transistors M1 to M3 are gate electrodes, the drain electrodes of the first and second transistors M1 and M2 adjacent to each other are drain electrodes, and the first and second transistors M1 adjacent to each other. , M2) is connected to the source electrode of the third transistor M3 spaced apart from them. However, in the case of using two transistors, the third transistor M3 is omitted and the drain electrodes of the first and second transistors M1 and M2 are directly connected to the C-th node C. As shown in FIG.

In this structure, the three transistors M1 to M3 are simultaneously turned on by the voltage applied to the gate electrode. And, by the simultaneous turn-on operation of the three transistors M1 to M3, the A-th node (A), the B-th node (B), and the C-th node (C) are electrically connected (conducted) at the same time. At this time, that the three nodes (A ~ C) are connected means that the signal or voltage of the A-th node (A) is the C-th node (C), and the signal or the voltage of the B-th node (B) is the C-th node (C). It can be interpreted as , or that the signal or voltage of the C-th node (C) is branched into the A-th node (A) and the B-th node (B).

Some of the above explanations are explained by adding formulas as follows.

TFT ON: Vg - Vs (the lowest voltage among the three node voltages = Vref) ＜ Vth -> Short-circuited all nodes A to C (A to C)

TFT OFF : Vg - Vs (highest voltage among the three node voltages) > Vth -> All nodes A to C (A to C) are open

In the second embodiment, one gate metal layer GATE is disposed on the first to third transistors M1 to M3 connected as shown in FIG. 9A . In addition, the first to third transistors M1 to M3 share one channel provided with one active layer ACT(M1) to ACT(M3) as shown in FIGS. 9(b) and 9(c). Here's how to do it:

Referring to FIG. 9( b ), the A-th node (A) and the B-th node (B) are disposed to be spaced apart from each other in the vertical direction, and the lower ends of both ends are connected. The C-th node (C) starts from the center of the point where the connection between the A-th node (A) and the B-th node (B) is made and protrudes in the vertical direction.

As a result, the A-th node (A) and the B-th node (B) have a shape (c) rotated 90 degrees to the left or a U-shape, and the C-th node (C) has a straight (1) shape or I has the shape of a The gate metal layer GATE is disposed in a horizontal direction along a connection point (or an end of each node) to which all of the A to Cth nodes A to C are connected.

According to the structure of FIG. 9(b), the first, third, and second transistors M1, M3, and M2 are horizontally arranged at the connection points to which the A to C-th nodes A to C are connected. are placed And the overall shape of the A to C-th nodes (A to C) has a shape similar to the capital letter Y. However, when two transistors are used, the third transistor M3 is omitted. Therefore, the first and second transistors M1 and M2 are arranged horizontally at the connection points where the A to Cth nodes A to C are connected.

Referring to FIG. 9(c), the A-th node (A) and the B-th node (B) are disposed to be spaced apart from each other in the vertical direction, and lower ends of both ends are connected. The C-th node (C) starts from the left side (or the end of the A-th node) of the point where the connection between the A-th node (A) and the B-th node (B) is made and protrudes in the vertical direction.

As a result, the A-th node (A) and the B-th node (B) have a shape (c) rotated 90 degrees to the left or a U-shape, and the C-th node (C) has a straight (1) shape or I has the shape of a The gate metal layer GATE is disposed in a horizontal direction along a connection point to which all of the A to Cth nodes A to C are connected.

According to the structure of FIG. 9(c), the first, third and second transistors M1, M3, and M2 are disposed at the connection points where the A to C-th nodes A to C are connected, the first and The third transistors M1 and M3 are disposed vertically (partial regions may overlap), and the second transistor M2 is disposed at the end of the B-th node B. As shown in FIG. And the overall shape of the A to C nodes (A to C) has a shape in which the lowercase letter y is symmetrically moved in the horizontal direction. However, when two transistors are used, the third transistor M3 is omitted. Therefore, the first and second transistors M1 and M2 are arranged horizontally at the connection points where the A to Cth nodes A to C are connected.

Conventionally, as shown in FIG. 5, an active layer is formed for each region of the transistors to have separate channels. However, in the second embodiment, as in the first embodiment, one active layer is formed so that all transistors share it. Since this description has already been described in the first embodiment described above, reference is made to the portion related to Fig. 8 of the first embodiment.

According to the experimental results, according to the structures of the first and second embodiments, the structure in which the gate electrodes are commonly connected and they share a unified channel was found to be applicable to at least two transistors.

In particular, the present invention can increase the space efficiency (since it occupies a small area) of device arrangement, as well as high resolution and high integration, when N (N is an integer greater than or equal to 2) transistors commonly connected to the gate electrode are used when implementing the compensation circuit. has been shown to have advantageous structural advantages.

Therefore, in the present invention, when two or M gate electrodes (M is an integer greater than or equal to 2) gate electrodes are commonly connected and transistors that require simultaneous driving are applied to a compensation circuit, two or N gate electrodes are used to share one integrated channel. By forming transistors (N is an integer greater than or equal to 2), space efficiency (since it occupies a small area) of device arrangement may be increased, and structural advantages may be advantageous for high integration.

Hereinafter, a case in which two transistors having a gate electrode connected in common are used in a specific compensation circuit in the second embodiment among the above-described embodiments, particularly in the second embodiment, will be described as an example.

10 is an exemplary circuit configuration diagram of sub-pixels having a compensation circuit, FIG. 11 is an exemplary implementation of one of the sub-pixels of FIG. 10 according to the prior art, and FIG. 12 is one of the sub-pixels of FIG. 10 according to the present invention It is an exemplary diagram implemented according to the present invention, and FIG. 13 is a diagram for explaining a comparison between the prior art and the present invention.

As shown in FIG. 10 , the N-th sub-pixel SPn and the N+1-th sub-pixel SPn+1 are configured with the same circuit. The N-th sub-pixel SPn enables its fourth node N4 to use the potential of the first node N1 of the N+1-th sub-pixel SPn+1 disposed adjacently. A description related to this is dealt with below.

The configuration and connection relationship of the circuit included in the N-th sub-pixel SPn will be described as follows. For the configuration and connection relationship of circuits included in the N+1th sub-pixel SPn+1, refer to the description of the N-th sub-pixel SPn.

The N-th sub-pixel SPn includes first to seventh transistors T1 to T7 , a driving transistor DT, a capacitor Cst, and an organic light emitting diode OLED. The N-th sub-pixel SPn includes an internal compensation circuit for automatically compensating for the threshold voltage of the driving transistor DT. Circuits included in the internal compensation circuit correspond to the second to seventh transistors T2 to T7. Among them, the second and sixth transistors T2 and T6 are implemented as double transistors instead of single transistors.

The first transistor T1 has a gate electrode connected to the N-th scan signal line Scan[n], a first electrode connected to the I-th data line DLi, and a second electrode connected to the first node N1. do. The capacitor Cst has one end connected to the first node N1 and the other end connected to the second node N2. The driving transistor DT has a gate electrode connected to the other end of the capacitor Cst, a first electrode connected to the first power line VDD, and a second electrode connected to the third node N3.

The second transistor T2 has a gate electrode connected to an N-th scan signal line Scan[n], a first electrode connected to a second node N2, and a second electrode connected to a third node N3. . The sixth transistor T6 has a gate electrode connected to an N-1 th scan signal line Scan[n-1], a first electrode connected to a first node N1, and a second electrode connected to a second node N2. electrodes are connected.

The third transistor T3 has a gate electrode connected to the Nth light emitting signal line EM[n], a first electrode connected to the first node N1, and a second electrode connected to the reference line VREF. The seventh transistor T7 has a gate electrode connected to an N-1 th scan signal line Scan[n-1], a first electrode connected to a first node N1, and a second electrode connected to a reference line VREF. this is connected

The fourth transistor T4 has a gate electrode connected to the Nth light emitting signal line EM[n], a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. . The fifth transistor T5 has a gate electrode connected to an Nth scan signal line Scan[n], a first electrode connected to a first node N1 of an N+1th sub-pixel SPn+1, and a first electrode connected to the fifth transistor T5. A second electrode is connected to the fourth node N4. The organic light emitting diode OLED has an anode electrode connected to the fourth node N4 and a cathode electrode connected to the second power line VSS.

The N-th sub-pixel SPn described above receives a voltage of about 7V to 9V from the first power line VDD, a voltage of about 0V from the second power line VSS, and about 1V to about 1V from the reference line VREF. A voltage of 2V may be applied, but is not limited thereto.

The N-th sub-pixel SPn described above operates in a flow of an initialization period, a sampling period, a sustain period, and a light emission period. The table shows changes in nodes and driving transistors for each section as follows.

reset period sampling period maintenance period luminescence period N1 VDD (or Vref) Vdata Vdata+Vkb Vref N2 (DTG) Vref VDD-|Vth| VDD-|Vth|+Vkb VDD-|Vth|-Vdata+Vref VDD (DTS) VDD VDD VDD VDD Vsg(DT) Vdata-Vref+|Vth|

Here, Vdata is a data voltage, VDD is a high potential voltage, Vref is a reference voltage, Vkb is a kickback voltage by turning off the first and second transistors T1 and T2, and Vth is a threshold voltage of the driving transistor.

The above-described N-th sub-pixel SPn may also arrange the fifth transistor T5 included therein in the N+1-th sub-pixel SPn+1 positioned at the next stage. The reason is that the fifth transistor T5 transfers the reference voltage charged in the first node N1 of the N+1-th sub-pixel SPn+1 to the fourth node N4 of the N-th sub-pixel SPn. This is because it can be turned on by the scan signal of the next stage (n+1) or the previous stage (n-1) rather than the current stage (n), because it has the autonomy of arrangement.

However, when the layout of the sub-pixel circuit shown in FIG. 10 is designed according to the prior art, the following problems are induced. However, in FIGS. 11 to 13 , the seventh transistor T7 of the N-th sub-pixel SPn and the fifth transistor T5 of the N-1 th sub-pixel SPn-1 receive the N-1th scan signal. A structure in which a gate electrode is commonly connected to the line Scan[n-1] will be described as an example. In addition, in the following FIGS. 11 to 13, portions not directly related to the present invention are omitted from the layout of the sub-pixel circuit.

As shown in FIG. 11 , a fifth transistor T5 for transferring a reference voltage to the fourth node of the N-1 th sub-pixel SPn-1 is included in the N-th sub-pixel SPn. The fifth transistor T5 of the N-th sub-pixel SPn-1 and the seventh transistor T7 of the N-th sub-pixel SPn are disposed adjacent to each other on the left and right. In addition, the seventh transistor T7 of the N-th sub-pixel SPn and the fifth transistor T5 of the N-1 th sub-pixel SPn-1 are connected to the N-1 th scan signal line Scan[n-1]. The gate electrode is connected in common.

The seventh transistor T7 of the N-th sub-pixel SPn and the fifth transistor T5 of the N-1 th sub-pixel SPn-1 are laid out according to the prior art, and have separate channels. As a result, the connection point between the seventh transistor T7 and the fifth transistor T5 is disposed to protrude downward of the N-1th scan signal line Scan[n-1], so that the seventh transistor T7 ) and the space occupied by the fifth transistor T5 increases.

On the other hand, if the layout of the sub-pixel circuit shown in FIG. 10 is designed according to the present invention, the problems occurring in the prior art can be solved as follows.

As shown in FIG. 12 , a fifth transistor T5 for transferring a reference voltage to the fourth node of the N-1 th sub-pixel SPn-1 is included in the N-th sub-pixel SPn. The fifth transistor T5 of the N-th sub-pixel SPn-1 and the seventh transistor T7 of the N-th sub-pixel SPn are disposed adjacent to each other on the left and right. In addition, the seventh transistor T7 of the N-th sub-pixel SPn and the fifth transistor T5 of the N-1 th sub-pixel SPn-1 are connected to the N-1 th scan signal line Scan[n-1]. A gate electrode is commonly connected to

The seventh transistor T7 of the N-th sub-pixel SPn and the fifth transistor T5 of the N-1 th sub-pixel SPn-1 are laid out according to the present invention (particularly, the second embodiment). , has a structure that shares an integrated channel. As a result, the connection point between the seventh transistor T7 and the fifth transistor T5 overlaps the N-1th scan signal line Scan[n-1], so that the seventh transistor T7 and the fifth transistor T5 are overlapped. The space occupied by the 5 transistor T5 is reduced. Since the N-1th scan signal line Scan[n-1] of the seventh transistor T7 and the fifth transistor T5 is formed of a gate metal layer, the gate metal layer overlaps with the active layer shared by these transistors. is laid out

Meanwhile, in FIGS. 11 and 12 , the CNT is a point connected to a lower electrode (eg, an anode electrode) of an organic light emitting diode (not shown).

The advantages of the present invention of FIG. 13(b) compared to the prior art of FIG. 13(a) will be described as follows.

First, in the present invention, it is possible to secure a corresponding space (reducing the minimum separation distance required for the TR process) by deleting the metallized active layer ACT from the fifth transistor T5. The sub-pixels are also adjacent to the left and right. Therefore, when the metallized active layer ACT is removed from the fifth transistor T5 , a space is formed in a portion adjacent to the reference line VREF and the I-th data line DLi. For this reason, the position of the gate electrode of the T2a transistor T2a may be disposed in the upper direction rather than the lower direction of the N-th scan signal line Scan[n].

Second, according to the present invention, a space can be secured in the lower direction of the N-th scan signal line Scan[n] by changing the position of the gate electrode of the T2a-th transistor T2a. The capacitor Cst of the sub-pixels requires more storage capacity as the resolution increases. Therefore, if the position of the gate electrode of the T2a th transistor T2a is changed, the capacitance of the capacitor Cst can be increased by about 30% compared to the prior art.

Third, according to the present invention, in addition to the above-described examples, it is possible to provide a design environment advantageous for high resolution and high integration by configuring at least two transistors capable of common connection of the gate electrode in various forms.

As described above, the present invention provides a space by more efficiently configuring and arranging a switching transistor occupying a large area in the compensation circuit of a sub-pixel, and utilizing the space for the arrangement of other structures to increase the space efficiency of device arrangement. Of course, there is an effect of providing advantageous advantages for high resolution and high integration.

In order to achieve the present invention, N transistors are formed on a first substrate, an active layer positioned on the first substrate and shared by the N transistors, a gate insulating layer positioned on the active layer, and a gate insulating layer It may include a gate metal layer positioned.

In order to achieve the present invention, the gate metal layer may overlap all of the active layers shared by the N transistors.

In order to achieve the present invention, the active layer may be selected from an oxide material, but is not limited thereto.

In order to achieve the present invention, one of the N transistors is a current-stage transistor that transfers a reference voltage supplied from the outside to the first reference voltage applying node of the N-th sub-pixel, and the other of the N transistors is the N-th transistor. It may be a front-end or rear-end transistor that transfers the reference voltage charged in the first node of the sub-pixel to the second reference voltage application node of the sub-pixel located at the front or rear end of the N-th sub-pixel.

In order to achieve the present invention, the first reference voltage applying node is a point (refer to N1) where the electrode of the transistor turned on by the scan signal in the N-th sub-pixel and one end of the capacitor are connected (see N1), and the second reference voltage applying node is It may be a point (refer to N4 ) where an electrode of a transistor turned on by a light emitting signal and an anode electrode of an organic light emitting diode are connected at the front or rear end of the N-th sub-pixel.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: data driver 140: scan driver
150: display panel 160: power supply
M1 to M3: first to third transistors
A to C: Nodes A to C
150a: first substrate ACT: active layer
GI: gate insulating layer GATE: gate metal layer

Claims (12)

delete delete delete delete sub-pixels including N (N is an integer greater than or equal to 2) transistors disposed adjacent to each other; and
a display panel displaying an image based on the sub-pixels;
The N transistors are
All gate electrodes are connected in common and share one channel provided as one active layer,
A first substrate, an active layer positioned on the first substrate and shared by the N transistors, a gate insulating layer positioned on the active layer, and a gate metal layer positioned on the gate insulating layer,
One of the N transistors is
It is a transistor of the current stage that transfers the reference voltage supplied from the outside to the first reference voltage applying node of the Nth sub-pixel,
Another one of the N transistors is
An electric field that is a front-end or rear-end transistor for transferring the reference voltage charged in the first reference voltage applying node of the N-th sub-pixel to the second reference voltage applying node of the sub-pixel located at the front or rear end of the N-th sub-pixel light-emitting display device. delete 6. The method of claim 5,
The gate metal layer is
An electroluminescent display device overlapping all of the active layer shared by the N transistors. 6. The method of claim 5,
The active layer is
An electroluminescent display device selected as an oxide material. delete 6. The method of claim 5,
The first reference voltage applying node is a point at which an electrode of a transistor turned on by a scan signal in the N-th sub-pixel and one end of a capacitor are connected,
The second reference voltage applying node is a point at which an electrode of a transistor turned on by a light emitting signal at a front end or a rear end of the Nth sub-pixel and the anode electrode of the organic light emitting diode are connected. 6. The method of claim 5,
The N transistors include three transistors,
The three transistors include an A-th node, a B-th node and a C-th node connected to electrodes to which a signal or voltage is applied,
The A-th node and the B-th node are vertically spaced apart from each other, and the lower ends of both ends are connected, and the C-th node protrudes vertically from the lower end where the A-th node and the B-th node are connected. An electroluminescent display device having 12. The method of claim 11,
The three transistors are
The A-th node and the B-th node have a U-shape, and the C-th node has an I-shape so as to exhibit a Y-shape when viewed in a plan view.

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