KR102401432B1 - Display device - Google Patents

Abstract

The display device of the present invention includes a first semiconductor layer provided on a substrate, a first insulating layer provided on the substrate to cover the first semiconductor layer, and a first semiconductor layer provided on the first insulating layer and An overlapping gate electrode, a second insulating layer provided on the first insulating layer to cover the gate electrode, and a second semiconductor provided on the second insulating layer to overlap the first semiconductor layer and the gate electrode include layers.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device having a polycrystalline silicon semiconductor and an oxide semiconductor.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. The display device field has rapidly changed to a thin, light, and large-area Flat Panel Display Device (FPD) that replaces a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED Display), and Electrophoretic Display. Device: ED), etc.

A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of liquid crystal using an electric field.

The organic light emitting diode display displays an image by adjusting the current of an organic light emitting diode (OLED) formed in each pixel according to data. The organic light emitting diode display is a self-luminous device that emits light by itself, and has advantages of fast response speed, luminous efficiency, luminance and viewing angle. The organic light emitting display device) is divided into a passive matrix type and an active matrix type.

An active matrix type display device includes a thin film transistor substrate in which thin film transistors are formed in pixels. In order to apply such a display device to a portable device, low power consumption is required. However, there is a limit to further reducing the power consumption of thin film transistor substrates currently being applied to mobile devices.

The present invention is an invention devised to solve the problems of the prior art, and an object of the present invention is to provide a display device capable of reducing power consumption.

The display device of the present invention includes a first semiconductor layer provided on a substrate, a first insulating layer provided on the substrate to cover the first semiconductor layer, and a first semiconductor layer provided on the first insulating layer and An overlapping gate electrode, a second insulating layer provided on the first insulating layer to cover the gate electrode, and a second semiconductor provided on the second insulating layer to overlap the first semiconductor layer and the gate electrode include layers.

The display device of the present invention includes a first semiconductor layer provided on a substrate, a first insulating layer provided on the first semiconductor layer, a gate electrode provided on the first insulating layer and overlapping the first semiconductor layer; a second insulating layer provided on the substrate to cover the gate electrode; and a second semiconductor layer provided on the second insulating layer and overlapping the first semiconductor layer and the gate electrode.

According to the present invention, low power consumption can be realized without lowering the aperture ratio of the display device by overlapping the first semiconductor layer and the second semiconductor layer.

1 is a cross-sectional view showing a vertical section of a thin film transistor substrate according to a first embodiment of the present invention.
FIG. 2 is a flowchart illustrating a manufacturing process of the thin film transistor substrate shown in FIG. 1;
3 is a cross-sectional view showing a vertical cross-section of a thin film transistor substrate according to a second embodiment of the present invention.
FIG. 4 is a flowchart illustrating a manufacturing process of the thin film transistor substrate shown in FIG. 3 ;
5 and 6 are equivalent circuit diagrams illustrating an example in which the first and second thin film transistors shown in FIG. 3 are applied as switch elements of a multiplexer;
7 is a waveform diagram showing input/output signals of the multiplexer shown in FIG. 5;
8 is a cross-sectional view showing a vertical section of a thin film transistor substrate according to a third embodiment of the present invention.
9 is a flowchart illustrating a manufacturing process of the thin film transistor substrate shown in FIG. 8;
10 is a cross-sectional view showing a vertical cross-section of a thin film transistor substrate according to a fourth embodiment of the present invention.
11 is a block diagram schematically showing the configuration of a display device according to an embodiment of the present invention;
12 is a plan view showing a thin film transistor substrate of a liquid crystal display;
13 is a cross-sectional view of the thin film transistor substrate shown in FIG. 12 taken along line II';
14 is a plan view illustrating the structure of one pixel in an organic light emitting diode display;
15 is a cross-sectional view illustrating a cross-sectional structure of the active matrix organic light emitting diode display taken along the cut line II-II' in FIG. 14;
16 is an enlarged plan view illustrating a schematic structure of an organic light emitting diode display;
17 is a cross-sectional view illustrating a cross-sectional structure of the organic light emitting diode display taken along the cut line III-III' in FIG. 16;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

The thin film transistor substrate of the present invention includes a thin film transistor having a polycrystalline semiconductor material and an oxide semiconductor material.

Polycrystalline semiconductor materials have high mobility (more than 100cm 2 /Vs), low energy consumption, and excellent reliability. good to do Since the oxide semiconductor material has a low off-current, it is suitable for a switching thin film transistor having a short on-time and a long off-time. In addition, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low-speed driving and/or low power consumption. As described above, according to the present invention, by forming thin film transistors having two different types of semiconductor materials on a thin film transistor substrate, power consumption can be significantly reduced compared to a conventional display device. In addition, according to the present invention, the power consumption of the display device can be reduced without lowering the aperture ratio of the pixel by vertically overlapping the semiconductor layers in the thin film transistor. A thin film transistor substrate exhibiting an optimal effect can be obtained.

When the semiconductor layer is formed of a polycrystalline semiconductor material, an impurity implantation process and a high-temperature heat treatment process are required. On the other hand, when the semiconductor layer is formed of an oxide semiconductor material, the process is performed at a relatively low temperature. Therefore, it is preferable to first form the polycrystalline semiconductor layer, which is subjected to the process under severe conditions, and then form the oxide semiconductor layer later.

Since the polycrystalline semiconductor material deteriorates properties when voids exist, a process of filling the voids with hydrogen through a hydrogenation process is required. The hydrogenation process is a heat treatment process for improving device characteristics by bonding hydrogen to a dangling bond of silicon (Si) existing at the interface between the gate insulating film and the polycrystalline semiconductor layer. On the other hand, in the oxide semiconductor material, since pores without covalent bonding can serve as carriers, a process for stabilizing the pores with pores is required. These two processes can be formed through a subsequent heat treatment process carried out at 350 ~ 380 ℃. In the present invention, the hydrogenation process of the polycrystalline semiconductor and the heat treatment process of the oxide semiconductor may be performed simultaneously or separately at a temperature of 350 to 380 °C.

In order to perform the hydrogenation process, the present invention interposes a nitride film containing a large amount of hydrogen particles on a polycrystalline semiconductor material. Since the nitride film contains a large amount of hydrogen in the material used for manufacturing, the layered nitride film itself also contains a significant amount of hydrogen. In a heat treatment process, hydrogen diffuses into the polycrystalline semiconductor material. As a result, the polycrystalline semiconductor layer can achieve stabilization. During the heat treatment process, hydrogens should not diffuse into the oxide semiconductor material. Therefore, it is preferable to interpose an oxide film between the nitride film and the oxide semiconductor material. After performing the heat treatment process, the oxide semiconductor material is not damaged by hydrogen, and device stabilization can be achieved.

The thin film transistor substrate of the present invention includes a first semiconductor layer formed on the substrate, a first insulating layer formed on the substrate to cover the first semiconductor layer, and a gate electrode formed on the first insulating layer and overlapping the first semiconductor layer , a second insulating layer formed on the first insulating layer to cover the gate electrode, and a second semiconductor layer formed on the second insulating layer and overlapping the first insulating layer and the gate electrode. The first semiconductor layer includes a polycrystalline silicon material and the second semiconductor layer includes an oxide semiconductor material. In embodiments, the first insulating layer is a gate insulating film, and the second insulating layer is an intermediate insulating film. The substrate may include a light blocking layer and a buffer layer.

A preferred embodiment of the present invention will be described with reference to FIG. 1 . 1 is a cross-sectional view showing a thin film transistor substrate according to a first embodiment of the present invention. Here, the present invention will be mainly described with a cross-sectional view that can clearly show the characteristics of the invention, and for convenience, a plan view structure is not shown in drawings.

Referring to FIG. 1 , a thin film transistor substrate according to an embodiment of the present invention includes first and second semiconductor layers A1 and A2 vertically overlapped with respect to a substrate SUB.

The thin film transistor may include a first semiconductor layer A1 , a second semiconductor layer A2 , a gate electrode GE, a source electrode SE, and a drain electrode DE. A source electrode and a drain electrode may be connected to each of the first and second semiconductor layers A1 and A2 . In this case, the first and second thin film transistors may have a vertically overlapping structure and may be connected to each other according to use.

The first semiconductor layer A1 includes a polycrystalline silicon material. The first semiconductor layer A1 may be formed of low temperature poly-silicon (LTPS). The LTPS transistor has advantages of high electron mobility and excellent reliability.

The second semiconductor layer A2 includes an oxide semiconductor material. The second semiconductor layer A2 is at least one of indium-gallium-zinc oxide (IGZO), indium-gallium oxide (IGO), and indium-zinc oxide (IZO). of an oxide semiconductor material. The oxide transistor has a low off-current. In the pixel of the organic light emitting diode display, when the oxide transistor is applied as a switch element of the pixel, it is possible to prevent a decrease in the gate-source potential of the driving thin film transistor due to leakage current. Since the oxide transistor has a low off-current, it is possible to reduce the storage capacitor (STG) capacity of the pixel as well as power consumption by minimizing the decay of the pixel voltage.

In the present invention, a first semiconductor layer A1 and a second semiconductor layer A2 are formed in a thin film transistor in order to realize the advantages of the LTPS transistor and the advantages of the oxide semiconductor in one thin film transistor. The first semiconductor layer A1 and the second semiconductor layer A2 are vertically aligned (z-axis) with the insulating layers GI, ILD1, ILD2 and the gate electrode GE interposed therebetween when viewed from the vertical cross-sectional structure of the thin film transistor. overlap

A buffer layer BUF is deposited on the entire surface of the substrate SUB. In some cases, the buffer layer BUF may be omitted. Alternatively, the buffer layer BUF may have a structure in which a plurality of thin film layers are stacked. Here, for convenience, it is described as a single layer. In addition, a light blocking layer LS may be formed between the buffer layer BUF and the substrate SUB, for example, under the thin film transistor. The light blocking layer LS is formed for the purpose of preventing external light from being introduced into the semiconductor layer of the thin film transistor formed thereon.

The buffer layer BUF may be formed of silicon oxide (SiO ₂ ). A first semiconductor layer A1 is formed on the buffer layer BUF. The first semiconductor layer A1 includes a channel region of the thin film transistor. The channel region is defined as a region where the gate electrode GE and the first semiconductor layer A1 overlap. An edge of the channel region is doped with impurities, and is defined as a source region SA and a drain region DA. The light blocking layer LS and the buffer layer BUF may be omitted. The substrate may be used in the sense of including a light blocking layer and a buffer layer.

The gate insulating layer GI may be formed on the buffer layer BUF using silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ). The gate insulating layer GI may be formed to a thickness of about 1,000 to 1,500 Å. When the gate insulating layer GI is formed of silicon nitride (SiN _x ), a large amount of hydrogen may be included in the gate insulating layer GI due to a manufacturing process. Since these hydrogens may diffuse out of the gate insulating layer GI in a subsequent process, it is preferable to form the gate insulating layer GI as an oxide layer such as silicon oxide (SiO ₂ ).

In the first semiconductor layer A1 including the polycrystalline silicon material, hydrogen diffusion has a positive effect. However, when the second semiconductor layer A2 made of an oxide semiconductor material is exposed to a large amount of hydrogen, it may cause a negative result in that electrical characteristics are deteriorated. In some cases, the gate insulating layer GI may be formed as thick as 2,000 Å to 4,000 Å. In this case, when the gate insulating layer GI is formed of silicon nitride (SiN _x ), the degree of hydrogen diffusion may be severe. Therefore, it is more preferable to use silicon oxide (SiO ₂ ) as the gate insulating layer GI.

A gate electrode GE is formed on the gate insulating layer GI. The gate electrode GE overlaps the first semiconductor layer A1 with the gate insulating layer GI interposed therebetween.

A first intermediate insulating layer ILD1 is deposited on the substrate SUB on which the gate electrode GE is formed. The first intermediate insulating layer ILD1 may be formed of a nitride layer such as silicon nitride (SiN _x ). The nitride film is deposited to perform hydrogenation of the first semiconductor layer A1 including polycrystalline silicon by diffusing hydrogen contained therein through a subsequent heat treatment process.

A second intermediate insulating layer IDL2 is deposited on the first intermediate insulating layer ILD1 . The second intermediate insulating layer ILD2 is preferably formed of an oxide layer such as silicon oxide (SiO ₂ ). Although the first semiconductor layer A1 including the polycrystalline silicon material may be stabilized by the hydrogenation process, the resistance of the second semiconductor layer A2 may be increased, resulting in negative consequences for the second semiconductor layer A2 . The oxide layer may block diffusion of hydrogen emitted from the nitride layer of the first intermediate insulating layer ILD1 into the second semiconductor layer A2 in a subsequent heat treatment process.

Hydrogen emitted from the nitride film is preferably diffused into the first semiconductor layer A1 disposed therebelow with the gate insulating film GI interposed therebetween. On the other hand, it is preferable to prevent the hydrogen emitted from the nitride film from diffusing into the second semiconductor layer A2 formed thereon. Accordingly, it is preferable that the nitride layer is stacked close to the first semiconductor layer A1 on the gate insulating layer GI, and the oxide layer SIO is stacked on the nitride layer. In consideration of the manufacturing process, the total thickness of the intermediate insulating layers ILD1 and ILD2 may have a thickness of 6,000 Å or less. In order for the hydrogen in the nitride film to diffuse to the first semiconductor layer A1 as much as possible while affecting the second semiconductor layer A2 as little as possible, the oxide film is preferably thicker than the gate insulating film GI. In particular, the oxide film is used to control the diffusion degree of hydrogen emitted from the nitride film, and the oxide film is preferably thicker than the nitride film.

The second semiconductor layer A2 is formed of an oxide semiconductor material on the second intermediate insulating layer ILD2. The second semiconductor layer A2 overlaps the first semiconductor layer A1 with the gate insulating layer GI, the gate electrode GE, and the intermediate insulating layers ILD1 and ILD2 interposed therebetween. Although omitted from the drawing, the second semiconductor layer A2 may be connected to at least one of the source electrode SE and the drain electrode DE, and may be connected to a separate source electrode and a drain electrode as shown in FIGS. 3, 8 and 10 . may be connected.

The source electrode SE is connected to the source region SA of the first semiconductor layer A1 through a first contact hole penetrating the second intermediate insulating layer ILD2, the first intermediate insulating layer ILD1, and the gate insulating layer GI. connected The drain electrode DE is connected to the drain region DA of the first semiconductor layer A1 through a second contact hole penetrating the second intermediate insulating layer ILD2, the first intermediate insulating layer ILD1, and the gate insulating layer GI. connected At least one of the source electrode SE and the drain electrode DE may be connected to the second semiconductor layer A2 . Separate source and drain electrodes may be connected to the second semiconductor layer A2 .

The first passivation layer PAS1 is formed on the second intermediate insulating layer ILD2 to cover the second semiconductor layer A2 , the source electrode SE, and the drain electrode DE. The planarization layer PAC is formed on the first passivation layer PAS1 . The planarization layer PAC is an organic passivation layer having a flat surface. The second passivation layer PAS2 is formed on the planarization layer PAC. In the case of the liquid crystal display (LCD), the common electrode COM may be formed on the planarization layer PAC, and the pixel electrode PXL may be formed on the second passivation layer PAS2 . The common electrode COM and the pixel electrode PXL may be formed of a transparent conductive material such as indium tin oxide (ITO). It should be noted that the thin film transistor illustrated in FIG. 1 is not limited to the liquid crystal display and may be applied to other displays.

A second semiconductor layer A2 including an oxide semiconductor material is formed on the first semiconductor layer A1 including a polycrystalline semiconductor material. Accordingly, by first forming the first semiconductor layer A1 formed at a relatively high temperature and then forming the second semiconductor layer A2 formed at a relatively low temperature later, the oxide semiconductor material is exposed to a high temperature state during the manufacturing process It has a structure that can avoid the situation.

Hereinafter, a method of manufacturing the thin film transistor substrate shown in FIG. 1 will be described with reference to FIG. 2 .

Referring to FIG. 2 , a light blocking layer LS is formed on a substrate SUB, and a buffer layer BUF is deposited thereon. The buffer layer BUF is deposited on the thin film transistor substrate to cover the light blocking layer LS ( S001 and S002 ). The light blocking layer LS may be formed of a metal such as copper (Cu) or molybdenum (Mo). The light blocking layer LS may be patterned by the first mask process and formed only under the thin film transistor. The mask process refers to a photolithography process including photomask alignment, exposure, development, and etching processes. The buffer layer BUF may be formed of silicon oxide (SiO ₂ ).

The present invention deposits amorphous silicon (a-Si) on the buffer layer (BUF) and sequentially performs a dehydrogenation process, an ion doping process, and a crystallization process to form a poly-silicon layer as the buffer layer (BUF). ) is formed on (S003 and S004). The dehydrogenation process is a heat treatment process for reducing the amount of hydrogen in the amorphous silicon (a-Si) in order to minimize damage to the surface of the amorphous silicon (a-Si) due to the outflow of hydrogen generated in the crystallization process. The ion doping process is a process of implanting a dopant capable of providing surplus electrons or holes capable of contributing to an electric current into the amorphous silicon (a-Si) layer. The crystallization process changes the amorphous silicon (a-Si) layer into a polycrystalline semiconductor silicon layer by irradiating it with a laser. The polysilicon layer is patterned by a second mask process to form a first semiconductor layer A1 ( S005 ).

In the present invention, a gate insulating layer GI is formed by depositing an insulating material such as silicon oxide (SiO ₂ ) on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed ( S006 ). A gate metal is deposited on the gate insulating layer GI. The gate metal is a metal such as copper (Cu) or molybdenum (Mo). Next, in the present invention, the gate electrode GE is formed by patterning the gate metal by a third mask process (S007). The gate electrode GE overlaps a portion of the first semiconductor layer A1 .

In the present invention, an N+ doping process, an ashing process, and a low density doping area (LDD) doping process are performed on the first semiconductor layer A1 disposed thereunder using the gate electrode GE as a mask. (S008). The N+ doping process is a process of forming an ohmic layer by doping the polysilicon layer with impurity ions. In the ashing process, the LDD region is defined by etching the photoresist covered on the gate electrode GE. The LDD doping process reduces the concentration of the ohmic layer in the source region SA and the drain region DA adjacent to the channel of the thin film transistor, thereby improving device characteristics such as reduction of off-state current. The LDD doping process may be different for P-MOS, N-MOS or CMOS.

In the present invention, a first intermediate insulating film ILD1 and a second intermediate insulating film ILD2 are continuously deposited on the surface of the substrate SUB on which the gate electrode GE is formed, and an activation process, a hydrogenation process, an oxide semiconductor deposition and patterning process, and an oxide A heat treatment process of the semiconductor is performed (S011 and S012). The first intermediate insulating layer ILD1 is formed of a nitride layer such as silicon nitride (SiN _x ). The second intermediate insulating layer ILD2 is formed of an oxide layer such as silicon oxide (SiO ₂ ). In the activation process, damage to the silicon crystal caused by the accelerated collision of ions by high voltage in the ion doping process is healed, and heat is applied to the first semiconductor layer A1 so that the impurity acts as a conductive material. The hydrogenation process improves device characteristics by bonding hydrogen to a dangling bond of silicon existing at the interface between the gate insulating layer AI and the first semiconductor layer A1. The oxide semiconductor is selected from oxide semiconductors such as indium-gallium-zinc oxide (IGZO), indium-gallium oxide (IGO) and indium-zinc oxide (IZO). The oxide semiconductor layer is patterned by a fourth mask process. The patterned second semiconductor layer A2 overlaps the gate electrode GE with the first and second intermediate insulating layers ILD1 and ILD2 interposed therebetween, and the intermediate insulating layers ILD1 and ILD2 and the gate electrode GE. and the first semiconductor layer A1 with the gate insulating layer GI interposed therebetween. In the heat treatment process of the oxide semiconductor, the properties of the device are improved by applying heat to the second semiconductor layer A2 made of the oxide semiconductor material.

In S011 and S012, the process sequence may be performed in the order of an activation process, a hydrogenation process, an oxide semiconductor deposition and patterning process, and an oxide semiconductor heat treatment process. The hydrogenation process and the heat treatment process of the oxide semiconductor can be performed simultaneously because the process temperature is in the range of 350 to 380 °C. In this case, in S011 and S012, the process sequence may be an activation process, an oxide semiconductor deposition and patterning process, and a hydrogenation & heat treatment process in the order.

In the present invention, a fifth mask process is performed to penetrate the first and second intermediate insulating layers ILD1 and ILD2 to expose the source region SA and the drain region DA of the first semiconductor layer A1 ( S013 ). . Next, according to the present invention, a source electrode SE and a drain electrode DE are formed by depositing a source-drain metal and patterning the metal by a sixth mask process. The source-drain metal may be copper (Cu), but is not limited thereto. The source electrode SE is connected to the source area SA of the first semiconductor layer A1 through a contact hole, and the drain electrode DE is connected to the drain area DA of the first semiconductor layer A1 through another contact hole. ) is connected to (S014).

The present invention improves the film characteristics of the back channel of the second semiconductor layer A2 damaged in the etching process of the source-drain metal through 02 plasma treatment, and then silicon oxide (SiO ₂ ) After deposition and photo-acryl coating, a transparent conductive material is deposited and patterned (S015 to S017). As a result, the first passivation layer PAS1 , the planarization layer PAC, and the common electrode COM are formed.

In the present invention, after depositing silicon oxide (SiO ₂ ) on the planarization layer (PAC), a transparent conductive material is deposited and patterned to form the second passivation layer (PAS2) and the pixel electrode (PXL) (S018 and S019)

3 is a view showing a vertical cross-section of a thin film transistor substrate according to a second embodiment of the present invention.

Referring to FIG. 3 , the thin film transistor substrate of the present invention includes first and second thin film transistors in which first and second semiconductor layers A1 and A2 are vertically (z-axis) overlapped.

The first thin film transistor includes a first semiconductor layer A1 , a gate electrode GE, a first source electrode SE1 , and a drain electrode DE. The second thin film transistor includes a second semiconductor layer A2 , a gate electrode GE, a second source electrode SE2 , and a drain electrode DE. The first source electrode SE1 is connected to the first semiconductor layer A1 , and the second source electrode SE2 is connected to the second semiconductor layer A2 . The drain electrode DE is connected to the first and second semiconductor layers A1 and A2 between the first semiconductor layer A1 and the second semiconductor layer A2 . Accordingly, in the first and second thin film transistors, the gate electrode GE and the drain electrode DE are shared and are not separated.

The first semiconductor layer A1 includes a polycrystalline silicon material. The second semiconductor layer A2 includes an oxide semiconductor material. The first semiconductor layer A1 and the second semiconductor layer A2 are vertically (z-axis) overlapped with the insulating layers GI and ILD and the gate electrode GE interposed therebetween when viewed from the vertical cross-sectional structure of the thin film transistor. .

A buffer layer BUF is deposited on the entire surface of the substrate SUB. In some cases, the buffer layer BUF may be omitted. Alternatively, the buffer layer BUF may have a structure in which a plurality of thin film layers are stacked. A light blocking layer (not shown) may be formed between the buffer layer BUF and the substrate SUB, for example, under the thin film transistor.

The buffer layer BUF may be formed of silicon oxide (SiO ₂ ). A first semiconductor layer A1 is formed on the buffer layer BUF. The first semiconductor layer A1 includes a channel region of the first thin film transistor. The channel region of the first thin film transistor is defined as a region where the gate electrode GE and the first semiconductor layer A1 overlap. An edge of the channel region is doped with impurities, and is defined as a source region SA and a drain region DA. The second semiconductor layer A2 includes a channel region of the second thin film transistor. The channel region of the second thin film transistor is defined as a region where the gate electrode GE and the second semiconductor layer A2 overlap. Both sides of the channel region are doped with impurities, and are defined as a source region and a drain region.

A gate insulating layer GI is deposited on the substrate SUB on which the first semiconductor layer A1 is formed. The gate insulating layer GI may be formed of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ), but it is more preferable to use silicon oxide (SiO ₂ ) in consideration of excessive diffusion of hydrogen. The gate insulating layer GI is collectively patterned with the gate electrode GE to be formed on the first semiconductor layer A1 in the same shape as the gate electrode GE.

A gate electrode GE is formed on the gate insulating layer GI. The gate insulating layer GI is patterned with the same photomask as the gate electrode GE to have the same shape as the gate electrode GE. Accordingly, the gate insulating layer GI is formed only under the gate electrode GE. The gate electrode GE overlaps the first semiconductor layer A1 with the gate insulating layer GI interposed therebetween.

An intermediate insulating layer ILD is deposited on the substrate SUB on which the gate electrode GE is formed. The intermediate insulating layer ILD may be formed as a single layer, but may be formed as an insulating layer of two or more layers in which a nitride layer and an oxide layer are stacked as in the above-described embodiment. Although the first semiconductor layer A1 including the polycrystalline silicon material may be stabilized by the hydrogenation process, the resistance of the second semiconductor layer A2 may be increased, resulting in negative consequences for the second semiconductor layer A2 . The oxide layer may block diffusion of hydrogen emitted from the nitride layer into the second semiconductor layer A2 in a subsequent heat treatment process. Accordingly, when the intermediate insulating film ILD is formed of two or more insulating films, it is preferable to form a nitride film on the first semiconductor layer A1 and an oxide film on the nitride film.

The second semiconductor layer A2 is formed of an oxide semiconductor material on the intermediate insulating layer ILD. The second semiconductor layer A2 overlaps the first semiconductor layer A1 with the gate insulating layer GI, the gate electrode GE, and the intermediate insulating layer ILD interposed therebetween. The second semiconductor layer A2 is connected to the second source electrode SE2 and the drain electrode DE.

The first source electrode SE1 , the second source electrode SE2 , and the drain electrode DE are formed on the intermediate insulating layer ILD. The second semiconductor layer A2 covers a portion of the second source electrode SE2 and a portion of the drain electrode DE. The upper portion of the drain electrode DE is connected to the second semiconductor layer A2, and the lower portion of the drain electrode DE is the drain region ( DA) is connected. The first source electrode SE1 is connected to the source region SA of the first semiconductor layer A1 through another contact hole penetrating the intermediate insulating layer ILD.

The passivation layer PAS covers the second semiconductor layer A2 , the source electrodes SE1 and SE2 , and the drain electrode DE. A transparent electrode ITO may be formed on the passivation layer PAS, but is not limited thereto. The transparent electrode ITO may connect the first source electrode SE1 and another element (not shown).

The first and second thin film transistors may be implemented as P-MOS, N-MOS, or CMOS depending on doped impurities. The first and second thin film transistors may be applied as a switch element or a driving element in a pixel, and may also be applied to a driving circuit for writing data into the pixel. The first thin film transistor may be implemented as a P-MOS transistor, and the second thin film transistor may be implemented as an N-MOS transistor. In this case, the first and second thin film transistors may be used as switch elements of the multiplexer as shown in FIGS. 5 to 7 .

Hereinafter, a method of manufacturing the thin film transistor substrate shown in FIG. 3 will be described with reference to FIG. 4 .

Referring to FIG. 4 , a light blocking layer (not shown) is formed on a substrate SUB, and a buffer layer BUF is deposited thereon. The buffer layer BUF is deposited on the thin film transistor substrate to cover the light blocking layer ( S101 and S102 ). The light blocking layer may be formed of a metal such as copper (Cu) or molybdenum (Mo). The light blocking layer may be patterned by the first mask process and formed only under the thin film transistor. The buffer layer BUF may be formed of silicon oxide (SiO ₂ ).

The present invention deposits amorphous silicon (a-Si) on the buffer layer (BUF) and sequentially performs a dehydrogenation process, an ion doping process, and a crystallization process to form a poly-silicon layer as the buffer layer (BUF). ) is formed on (S103 and S104). The polysilicon layer is patterned by a second mask process to form the first semiconductor layer A1 ( S105 ).

In the present invention, an insulating material such as silicon oxide (SiO ₂ ) is deposited on the substrate SUB on which the first semiconductor layer A1 is formed (S106). A gate metal is deposited on the insulating material layer. The gate metal is a metal such as copper (Cu) or molybdenum (Mo). Next, in the present invention, the gate insulating layer GI and the gate electrode GE are formed by collectively patterning the insulating material layer and the gate metal by a third mask process ( S106 and S107 ). The gate electrode GE overlaps a portion of the first semiconductor layer A1 with the gate insulating layer GI interposed therebetween.

In the present invention, an N+ doping process, an ashing process, and an LDD doping process are performed on the lower first semiconductor layer A1 using the gate electrode GE as a mask ( S108 ). Next, in the present invention, after depositing a nitride film of the intermediate insulating film ILD on the buffer layer BUF to cover the gate electrode GE, an activation process and a hydrogenation process are performed, and then an oxide film of the intermediate insulating film ILD is deposited. (S109).

In the present invention, a fourth mask process is performed to penetrate the intermediate insulating layer ILD to expose the source region SA and the drain region DA of the first semiconductor layer A1. Then, according to the present invention, the source electrodes SE1 and SE2 and the drain electrode DE are formed by depositing a source-drain metal and patterning the metal by a fifth mask process. The source-drain metal may be copper (Cu), but is not limited thereto. The first source electrode SE1 is connected to the source region SA of the first semiconductor layer A1 through a contact hole, and the drain electrode DE is connected to the drain region of the first semiconductor layer A1 through another contact hole. (DA) is connected. The second source electrode SE2 is formed on the intermediate insulating layer ILD ( S110 ).

In the present invention, an oxide semiconductor deposition and patterning process, and an oxide semiconductor heat treatment process are performed (S111). The oxide semiconductor is selected from oxide semiconductors such as indium-gallium-zinc oxide (IGZO), indium-gallium oxide (IGO) and indium-zinc oxide (IZO). The oxide semiconductor layer is patterned by a sixth mask process. The patterned second semiconductor layer A2 overlaps the gate electrode GE with the intermediate insulating layer ILD interposed therebetween, and the intermediate insulating layer ILD, the gate electrode GE, and the gate insulating layer GI are interposed therebetween. and overlaps the first semiconductor layer A1. The second semiconductor layer A2 is connected to the drain electrode DE and the second source electrode SE2. The hydrogenation process and the heat treatment process of the oxide semiconductor can be performed simultaneously because the process temperature is in the range of 350 to 380 °C.

In the present invention, after depositing silicon oxide (SiO ₂ ), a contact hole passing through the silicon oxide film is formed by a seventh mask process, a transparent conductive material is deposited, and patterned by an eighth mask process (S112 and S113). As a result, the protective film PAS and the transparent electrode ITO are formed. The transparent electrode ITO is simultaneously formed of the same transparent conductive material as the pixel electrode. The transparent electrode ITO may be connected to the first source electrode SE1 through a contact hole penetrating the passivation layer PAS.

The first and second thin film transistors shown in FIG. 3 may be used as switch elements of the multiplexer as shown in FIGS. 5 to 7 . As shown in FIG. 11 , the multiplexer 210 reduces the number of output channels of the data driver 200 by time division distribution of the data voltage from the data driver to a plurality of data lines DL. When the first and second thin film transistors shown in FIG. 3 are applied as switch elements of the multiplexer 210, the number of control signal wirings can be reduced to one.

5 and 6 are equivalent circuit diagrams illustrating an example in which the first and second thin film transistors shown in FIG. 3 are applied as a switch element of the multiplexer 210 as shown in FIG. 11 . FIG. 7 is a waveform diagram showing input/output signals of the multiplexer 210 shown in FIG. 5; 7, Vg is a control signal of the multiplexer 210, and Vd is a data voltage. DL1 is a first data line, and DL2 is a second data line.

5 to 7 , the multiplexer 201 includes a plurality of multiplexers connecting the output channels OUT1 to OUT3 of the data driver 200 to the data lines DL1 to DL6. Each of the multiplexers includes a plurality of first thin film transistors PT and PT1 to PT3 and a plurality of second thin film transistors NT and NT1 to NT3.

The first multiplexer includes a first output channel OUT1 of the data driver 200 and first and second thin film transistors PT1 and NT1 connected between the first and second data lines DL1 and DL2. do. The first thin film transistor PT1 includes a gate electrode GE connected to the control signal line, a drain electrode DE connected to the first output channel OUT1 , and a first source electrode SE1 connected to the first data line DL1 . includes The second thin film transistor NT1 includes a gate electrode GE connected to the control signal line, a drain electrode DE connected to the first output channel OUT, and a second source electrode SE2 connected to the second data line DL2. includes The control signal Vg is generated as a positive polarity voltage H and a negative polarity voltage L and is supplied to the control signal wiring. In the first and second thin film transistors PT1 and NT1 , the gate electrode GE and the drain electrode DE are shared.

In the first multiplexer, the first thin film transistor PT1 is turned on in response to the negative voltage L of the control signal to supply the data voltage from the first output channel OUT1 to the first data line DL1 . The second thin film transistor NT1 is turned on in response to the positive voltage H of the control signal to supply the data voltage from the first output channel OUT1 to the second data line DL2 . Accordingly, the first multiplexer time division distributes the data voltage from the first output channel OUT1 of the data driver 200 to the first and second data lines DL1 and DL2 .

The second multiplexer includes a second output channel OUT2 of the data driver 200 and third and fourth thin film transistors PT2 and NT2 connected between the third and fourth data lines DL3 and DL4. do. The third thin film transistor PT2 is turned on in response to the negative voltage L of the control signal to supply the data voltage from the second output channel OUT2 to the third data line DL3 . The fourth thin film transistor NT2 is turned on in response to the positive voltage H of the control signal to supply the data voltage from the second output channel OUT2 to the fourth data line DL4 . Accordingly, the second multiplexer time division distributes the data voltage from the second output channel OUT2 of the data driver 200 to the third and fourth data lines DL3 and DL4 .

8 is a view showing a vertical cross-section of a thin film transistor substrate according to a third embodiment of the present invention.

Referring to FIG. 8 , the thin film transistor substrate of the present invention includes first and second thin film transistors in which first and second semiconductor layers A1 and A2 are vertically (z-axis) overlapped.

The first thin film transistor includes a first semiconductor layer A1 , a gate electrode GE, a first source electrode SE1 , and a first drain electrode DE1 . The first source electrode SE1 and the first drain electrode DE1 are connected to the first semiconductor layer A1 . The second thin film transistor includes a second semiconductor layer A2 , a gate electrode GE, a second source electrode SE2 , and a second drain electrode DE2 . The second source electrode SE2 and the second drain electrode DE2 are connected to the second semiconductor layer A2 . Accordingly, in the first and second thin film transistors, the gate electrode GE is shared and is not separated.

The first semiconductor layer A1 includes a polycrystalline silicon material. The second semiconductor layer A2 includes an oxide semiconductor material. The first semiconductor layer A1 and the second semiconductor layer A2 are vertically aligned (z-axis) with the insulating layers GI, ILD1, ILD2 and the gate electrode GE interposed therebetween when viewed from the vertical cross-sectional structure of the thin film transistor. overlap

A buffer layer BUF is deposited on the entire surface of the substrate SUB. In some cases, the buffer layer BUF may be omitted. The buffer layer BUF may have a structure in which a plurality of thin film layers are stacked. A light blocking layer (not shown) may be formed between the buffer layer BUF and the substrate SUB, for example, under the thin film transistor.

The buffer layer BUF may be formed of silicon oxide (SiO ₂ ). A first semiconductor layer A1 is formed on the buffer layer BUF. The first semiconductor layer A1 includes a channel region of the first thin film transistor. The channel region of the first thin film transistor is defined as a region where the gate electrode GE and the first semiconductor layer A1 overlap. Both sides of the channel region are regions doped with impurities, and are defined as a source region SA and a drain region DA. The second semiconductor layer A2 includes a channel region of the second thin film transistor. The channel region of the second thin film transistor is defined as a region where the gate electrode GE and the second semiconductor layer A2 overlap. Both sides of the channel region are doped with impurities, and are defined as a source region and a drain region.

A gate insulating layer GI is deposited on the substrate SUB on which the first semiconductor layer A1 is formed. The gate insulating layer GI may be formed of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ), but in consideration of excessive diffusion of hydrogen, it is more preferable to use silicon oxide (SiO ₂ ). The gate insulating layer GI is formed on the buffer layer BUF to cover the first semiconductor layer A1 .

The gate electrode GE is formed on the gate insulating layer GI. The gate electrode GE overlaps the first semiconductor layer A1 with the gate insulating layer GI interposed therebetween.

The intermediate insulating layer is divided into a first intermediate insulating layer ILD1 and a second intermediate insulating layer ILD2. The first intermediate insulating layer ILD1 is formed on the gate insulating layer GI. The second semiconductor layer A2 is formed of an oxide semiconductor material on the first intermediate insulating layer ILD1 . The second intermediate insulating layer ILD2 is formed on the first intermediate insulating layer ILD1 to cover the second semiconductor layer A2 . The first and second intermediate insulating layers ILD1 and ILD2 may include a nitride layer or an oxide layer.

The second semiconductor layer A2 overlaps the first semiconductor layer A1 with the gate insulating layer GI, the gate electrode GE, and the first intermediate insulating layer ILD1 interposed therebetween.

The first source electrode SE1 , the second source electrode SE2 , the first drain electrode DE1 , and the second drain electrode DE2 are formed on the second intermediate insulating layer ILD2 . The first source electrode SE1 is connected to the first semiconductor layer A1 through a first contact hole penetrating the first and second intermediate insulating layers ILD1 and ILD2 and the gate insulating layer GI. The first drain electrode DE1 is connected to the first semiconductor layer A1 through a second contact hole passing through the first and second intermediate insulating layers ILD1 and ILD2 and the gate insulating layer GI. The second source electrode SE2 is connected to the second semiconductor layer A2 through a third contact hole penetrating the second intermediate insulating layer ILD2. The second drain electrode DE2 is connected to the second semiconductor layer A2 through a fourth contact hole penetrating the second intermediate insulating layer ILD2 .

The passivation layer PAS is formed on the second intermediate insulating layer ILD2 to cover the first source electrode SE1 , the second source electrode SE2 , the first drain electrode DE1 , and the second drain electrode DE2 . . The link LNK may connect the first thin film transistor and the second thin film transistor through contact holes passing through the passivation layer PAS.

The first and second thin film transistors may be implemented as P-MOS, N-MOS, or CMOS depending on doped impurities. The first and second thin film transistors may be applied as a switch element or a driving element in a pixel, and may also be applied to a driving circuit for writing data into the pixel. The first thin film transistor may be implemented as a P-MOS transistor, and the second thin film transistor may be implemented as an N-MOS transistor. In this case, the first and second thin film transistors may be utilized as switch elements of the multiplexer, and may also be utilized as other switch elements in the driving circuit. As shown in FIG. 8 , when the first drain electrode DE1 and the second source electrode SE2 are connected by a link LNK, it may be used as an inverter. The inverter inverts and outputs the logic level of the input signal in the digital circuit.

Hereinafter, a method of manufacturing the thin film transistor substrate shown in FIG. 8 will be described with reference to FIG. 9 .

Referring to FIG. 9 , a light blocking layer (not shown) is formed on a substrate SUB, and a buffer layer BUF is deposited thereon. The buffer layer BUF is deposited on the thin film transistor substrate to cover the light blocking layer ( S201 and S202 ). The light blocking layer may be formed of a metal such as copper (Cu) or molybdenum (Mo). The light blocking layer may be patterned by the first mask process and formed only under the thin film transistor. The buffer layer BUF may be formed of silicon oxide (SiO ₂ ).

The present invention deposits amorphous silicon (a-Si) on the buffer layer (BUF) and sequentially performs a dehydrogenation process, an ion doping process, and a crystallization process to form a poly-silicon layer as the buffer layer (BUF). ) is formed on (S203 and S204). The polysilicon layer is patterned by a second mask process to form the first semiconductor layer A1 ( S205 ).

In the present invention, the gate insulating layer GI is formed by depositing an insulating material such as silicon oxide (SiO ₂ ) on the substrate SUB on which the first semiconductor layer A1 is formed ( S206 ). Next, according to the present invention, a gate electrode GE is formed on the gate insulating layer GI by depositing a gate metal on the gate insulating layer GI and patterning the gate metal using a third mask process ( S207 ). The gate metal is a metal such as copper (Cu) or molybdenum (Mo). The gate electrode GE overlaps a portion of the first semiconductor layer A1 with the gate insulating layer GI interposed therebetween.

In the present invention, an N+ doping process, an ashing process, and an LDD doping process are performed on the lower first semiconductor layer A1 using the gate electrode GE as a mask ( S208 ). Next, in the present invention, a first intermediate insulating layer ILD1 is deposited on the gate insulating layer GI to cover the gate electrode GE, and an activation process and a hydrogenation process are performed on the first semiconductor layer A1 ( S209 ). . Next, in the present invention, an oxide semiconductor deposition and patterning process, and an oxide semiconductor heat treatment process are performed (S210). The oxide semiconductor is selected from oxide semiconductors such as indium-gallium-zinc oxide (IGZO), indium-gallium oxide (IGO) and indium-zinc oxide (IZO). The oxide semiconductor layer is patterned by a fourth mask process. The patterned second semiconductor layer A2 overlaps the gate electrode GE with the first intermediate insulating layer ILD1 interposed therebetween, and the first intermediate insulating layer ILD1, the gate electrode GE, and the gate insulating layer GI. ) overlaps the first semiconductor layer A1 with the interposed therebetween. The hydrogenation process and the heat treatment process of the oxide semiconductor can be performed simultaneously because the process temperature is in the range of 350 to 380 °C. Next, in the present invention, a second intermediate insulating layer ILD2 is deposited on the first intermediate insulating layer ILD1 to cover the second semiconductor layer A2 ( S211 ).

In the present invention, a fifth mask process is performed to expose the source region SA and the drain region DA of the first semiconductor layer A1 and the source region and the drain region of the second semiconductor layer A2 . The source region SA and the drain region DA of the first semiconductor layer A1 are formed through first and second contact holes penetrating the first and second intermediate insulating layers ILD1 and ILD2 and the gate insulating layer GI. exposed A source region and a drain region of the second semiconductor layer A2 are exposed through third and fourth contact holes penetrating the second intermediate insulating layer ILD2 .

Next, according to the present invention, source electrodes SE1 and SE2 and drain electrodes DE1 and DE2 are formed by depositing a source-drain metal and patterning the metal by a sixth mask process ( S212 ). The source-drain metal may be copper (Cu), but is not limited thereto. The first source electrode SE1 is connected to the source region SA of the first semiconductor layer A1 through a first contact hole, and the first drain electrode DE1 is connected to the first semiconductor layer ( It is connected to the drain area DA of A1). The second source electrode SE2 is connected to the source region of the second semiconductor layer A2 through the third contact hole, and the second drain electrode DE2 is connected to the second semiconductor layer A2 through the fourth contact hole. connected to the drain region.

In the present invention, after depositing silicon oxide (SiO ₂ ), a contact hole passing through the silicon oxide film is formed by a seventh mask process, a metal is deposited, and the metal is patterned by an eighth mask process to form a link (LNK). (S112 and S113). The link LNK may be formed of the same transparent conductive material as the pixel electrode.

10 is a cross-sectional view showing a vertical cross-section of a thin film transistor substrate according to a fourth embodiment of the present invention.

Referring to FIG. 10 , a thin film transistor substrate according to an embodiment of the present invention includes first and second semiconductor layers A1 and A2 that are vertically overlapped with respect to a substrate SUBS.

The thin film transistor includes a first semiconductor layer A1 , a second semiconductor layer A2 , a gate electrode GE, a source electrode SE, and a drain electrode DE.

The first semiconductor layer A1 includes a polycrystalline silicon material. The first semiconductor layer A1 may be formed of low-temperature polysilicon (LTPS). The LTPS transistor has advantages of high electron mobility and excellent reliability.

The second semiconductor layer A2 includes an oxide semiconductor material. The second semiconductor layer A2 is at least one of indium-gallium-zinc oxide (IGZO), indium-gallium oxide (IGO), and indium-zinc oxide (IZO). of an oxide semiconductor material. The oxide transistor has a low off-current, so power consumption can be reduced.

The first semiconductor layer A1 and the second semiconductor layer A2 are vertically aligned (z-axis) with the insulating layers GI, ILD1, ILD2 and the gate electrode GE interposed therebetween when viewed from the vertical cross-sectional structure of the thin film transistor. overlap

A buffer layer BUF is deposited on the entire surface of the substrate SUB. In some cases, the buffer layer BUF may be omitted. Alternatively, the buffer layer BUF may have a structure in which a plurality of thin film layers are stacked. Here, for convenience, it is described as a single layer. In addition, a light blocking layer (not shown) may be formed between the buffer layer BUF and the substrate SUB, for example, under the thin film transistor. The light blocking layer is formed for the purpose of preventing external light from being introduced into the semiconductor layer of the thin film transistor formed thereon.

The buffer layer BUF may be formed of silicon oxide (SiO ₂ ). A first semiconductor layer A1 is formed on the buffer layer BUF. The first semiconductor layer A1 includes a channel region of the thin film transistor. The channel region is defined as a region where the gate electrode GE and the semiconductor layer overlap. A source region SA and a drain region DA doped with impurities are defined at edges of the channel region.

The gate insulating layer GI is formed of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) on the buffer layer BUF to cover the first semiconductor layer A1 . The gate insulating film GI is preferably formed of an oxide film such as silicon oxide (SiO ₂ ).

A gate electrode GE is formed on the gate insulating layer GI. The gate electrode GE overlaps the first semiconductor layer A1 with the gate insulating layer GI interposed therebetween.

The first intermediate insulating layer ILD1 is deposited on the gate insulating layer GI to cover the gate electrode GE. The first intermediate insulating layer ILD1 may be formed of a nitride layer such as silicon nitride (SiN _x ). The nitride film is deposited to perform hydrogenation of the first semiconductor layer A1 including polycrystalline silicon by diffusing hydrogen contained therein through a subsequent heat treatment process.

A second intermediate insulating layer IDL2 is deposited on the first intermediate insulating layer ILD1 . The second intermediate insulating layer ILD2 is preferably formed of an oxide layer such as silicon oxide (SiN _x ). Although the first semiconductor layer A1 including the polycrystalline silicon material may be stabilized by the hydrogenation process, the resistance of the second semiconductor layer A2 may be increased, resulting in negative consequences for the second semiconductor layer A2 . The oxide layer may block diffusion of hydrogen emitted from the nitride layer of the first intermediate insulating layer ILD1 into the second semiconductor layer A2 in a subsequent heat treatment process. In order for the hydrogen in the nitride film to diffuse to the first semiconductor layer A1 as much as possible while affecting the second semiconductor layer A2 as little as possible, the oxide film is preferably thicker than the gate insulating film GI. In particular, the oxide film is used to control the diffusion degree of hydrogen emitted from the nitride film, and the oxide film is preferably thicker than the nitride film.

The second semiconductor layer A2 is formed of an oxide semiconductor material on the second intermediate insulating layer ILD2. The second semiconductor layer A2 overlaps the first semiconductor layer A1 with the gate insulating layer GI, the gate electrode GE, and the intermediate insulating layers ILD1 and ILD2 interposed therebetween.

The source electrode SE may be connected to the first and second semiconductor layers A1 and A2 , and the drain electrode DE may be connected to the second semiconductor layer A2 , but is not limited thereto. For example, a source electrode and a drain electrode may be connected to each of the first and second semiconductor layers A1 and A2 . The first and second thin film transistors may share a gate electrode GE and include separate source and drain electrodes. For example, the first thin film transistor may include a gate electrode, a first semiconductor layer A1 , a first source electrode, and a first drain electrode. The second thin film transistor may include a gate electrode, a second semiconductor layer A2 , a second source electrode, and a second drain electrode.

In the example of FIG. 10 , the source electrode SE is connected to the second semiconductor layer A2 , and a contact hole passing through the second intermediate insulating layer ILD2 , the first intermediate insulating layer ILD1 , and the gate insulating layer GI is connected to the first semiconductor layer A1 through The drain electrode DE is connected to the second semiconductor layer A2 on the second intermediate insulating layer ILD2.

The passivation layer PAS is formed on the second intermediate insulating layer ILD2 to cover the second semiconductor layer A2 , the source electrode SE, and the drain electrode DE. The planarization layer PAC is formed on the first passivation layer PAS1 . The planarization layer PAC is an organic passivation layer having a flat surface. The source electrode SE or the drain electrode may be connected to a wiring or another electrode ITO through a contact hole penetrating the passivation layer PAS and/or the planarization layer PAC.

The insulating layers GI, ILD1, and ILD2 may have different thicknesses in the driving circuit and the pixel array to control the on current of the thin film transistor. 10 illustrates an example in which the second intermediate insulating layer ILD2 is formed thinner in the pixel array than in the driving circuit.

The thin film transistor shown in FIG. 10 may be implemented as P-MOS, N-MOS, or CMOS depending on impurities. This thin film transistor can be applied as a switch element or a driving element in a pixel, and can also be applied to a driving circuit for writing data into the pixel.

According to the present invention, reliability and power consumption of a pixel and a driving circuit can be improved without a decrease in the aperture ratio of the pixel or an increase in the bezel area, which is a non-display area, by vertically overlapping different semiconductor material layers with respect to the substrate surface.

It should be noted that the above-described embodiments can be applied together on one thin film transistor substrate.

The thin film transistor substrate described so far can be applied to various flat panel displays. Advantages that can be obtained when thin film transistors having different characteristics are formed on a single substrate as presented in the present invention are diverse. Hereinafter, with reference to FIGS. 11 to 17 , the display device using the thin film transistor substrate according to the present invention will be described in detail about what characteristics and what advantages can be expected.

11 is a block diagram schematically showing the configuration of a display device according to an application example of the present invention.

In the above embodiments, when the thin film transistor having the first semiconductor layer A1 is referred to as a first thin film transistor and the thin film transistor having the second semiconductor layer A2 is referred to as a second thin film transistor, the first and second thin film transistors At least one of the transistors may be a thin film transistor formed in each of the pixels of the display panel 100 to switch a data voltage written to the pixels or to drive the pixels. In the case of an organic light emitting diode display, the second thin film transistor may be applied as a switch element of a pixel, and the first thin film transistor may be applied as a driving element, but is not limited thereto. The switch element may be the switching thin film transistor T shown in FIGS. 12 and 13 and the switching thin film transistor ST shown in FIGS. 14 and 15 . The driving element may be the driving thin film transistor DT shown in FIGS. 14 and 15 . The first and second thin film transistors may be combined and applied as one switch element or one driving element.

In order to reduce power consumption in a mobile device or a wearable device, a low-speed driving method of lowering a frame rate has been attempted. In this case, the frame frequency of a still image or an image having a late data update period may be lowered. If the frame rate is lowered, a phenomenon in which the luminance flickers whenever the data voltage is changed or a flicker phenomenon in which the luminance flickers in the data update cycle due to a prolonged voltage discharge time of the pixel may be seen. When the first and second thin film transistors of the present invention are applied to a pixel, the flicker problem during low-speed driving can be solved.

When the data update period is long during low-speed driving, the amount of leakage current of the switch thin film transistor increases. The leakage current of the switch thin film transistor causes a drop in the voltage of the storage capacitor STG and the gate-source voltage of the driving thin film transistor. In the present invention, the second thin film transistor, which is an oxide transistor, can be applied as a switch thin film transistor of a pixel. Since the oxide transistor has a low off-current, it is possible to prevent a decrease in the gate-source potential of the storage capacitor and the driving thin film transistor. Accordingly, the present invention can prevent flicker when driving at a low speed.

When the first thin film transistor, which is a polysilicon transistor, is applied as a driving thin film transistor of a pixel, the amount of current supplied to the organic light emitting diode can be increased because electron mobility is high. Accordingly, according to the present invention, by applying the second thin film transistor to the switch element of the pixel and the first thin film transistor to the driving element of the pixel, power consumption can be significantly reduced and image quality deterioration can be prevented.

The present invention is effective for application to a mobile device or a wearable device because image quality deterioration can be prevented when a low-speed driving method is applied to reduce power consumption. For example, the portable electronic watch may update data on the display screen in units of 1 second to reduce power consumption. The frame frequency at this time is 1 Hz. According to the present invention, excellent image quality without flicker can be realized even using a driving frequency of 1 Hz or close to a still image. The present invention greatly reduces the frame rate of a still image on the standby screen of a mobile device or a wearable device, thereby significantly reducing power consumption without degrading image quality. As a result, the present invention can improve portability by improving the picture quality of a mobile device or a wearable device and extending the battery life. According to the present invention, power consumption can be greatly reduced without degradation of image quality even in an E-Book with a very long data update cycle.

The first and second thin film transistors may be embedded in one or more driving circuits, for example, one or more of the data driver 200, the multiplexer (MUX, 210), and the gate driver 300 in FIG. 11 to configure the driving circuit. . This driving circuit writes data to the pixel. Also, one of the first and second thin film transistors may be formed in the pixel and the other one may be formed in the driving circuit. The data driver 200 converts the data of the input image into a data voltage and outputs it. The multiplexer 210 reduces the number of output channels of the data driver 200 by time-division-distributing the data voltage from the data driver 200 to the plurality of data lines DL. The gate driver 300 outputs a scan signal (or gate signal) synchronized with the data voltage to the gate lines GL to sequentially select pixels in which data of the input image is written in line units. In order to reduce the number of output channels of the gate driver 300 , a multiplexer (not shown) may be added between the gate driver 300 and the gate lines GL. The multiplexer 210 and the gate driver 300 may be directly formed on the thin film transistor substrate together with the pixel array as shown in FIG. 12 . The multiplexer 210 and the gate driver 300 are disposed in the non-display area NA as shown in FIG. 12 , and the pixel array is disposed in the display area AA.

The display device of the present invention can be applied to any display device requiring a thin film transistor, such as an active display device using a thin film transistor, for example, a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device. Hereinafter, application examples of a display device to which the thin film transistor substrate of the present invention is applied will be described with reference to FIGS. 12 to 17 .

12 is a plan view illustrating a thin film transistor substrate of a fringe field type liquid crystal display, which is a type of horizontal electric field type. 13 is a cross-sectional view of the thin film transistor substrate shown in FIG. 12 taken along the perforated line I-I'.

12 and 13 , the thin film transistor substrate includes a gate line GL and a data line DL crossing a lower substrate SUB with a gate insulating layer GI interposed therebetween, and a thin film transistor formed at each intersection thereof. T) is provided. In addition, a pixel area is defined by the cross structure of the gate line GL and the data line DL.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S, and a gate A semiconductor layer A that forms a channel region between the source electrode S and the drain electrode D when overlapping the gate electrode G on the insulating layer GI is included. In particular, when the semiconductor layer (A) is formed of an oxide semiconductor material, since the off-current is low and the voltage holding period of the pixel is long, a display requiring low-speed driving and/or low power consumption suitable for small Due to these characteristics, the capacity of the storage capacitor may be reduced, which is advantageous in realizing an ultra-high resolution display device having a small pixel area.

A gate pad GP for receiving a gate signal from the outside is included at one end of the gate line GL. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 passing through the gate insulating layer GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 penetrating the first passivation layer PA1 and the second passivation layer PA2 . Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH penetrating the first passivation layer PA1 and the second passivation layer PA2 .

In the pixel area, the pixel electrode PXL and the common electrode COM formed with the second passivation layer PA2 interposed therebetween are provided to form a fringe field. The common electrode COM may be connected to the common line CL arranged in parallel with the gate line GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL. Alternatively, the common electrode COM may be formed over the entire surface of the substrate SUB except for a portion where the drain contact hole DH is formed. That is, it is formed to cover the upper layer of the data line DL, and the common electrode COM may function to shield the data line DL.

The positions and shapes of the common electrode COM and the pixel electrode PXL may be formed in various ways according to the design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that changes frequently according to video data to be implemented is applied to the pixel electrode PXL. Accordingly, a parasitic capacitance may be generated between the data line DL and the pixel electrode PXL. Since such a parasitic capacitance may cause a problem in image quality, it is preferable to first form the common electrode COM and then form the pixel electrode PXL on the uppermost layer.

After the planarization layer PAC is thickly formed of an organic material having a low dielectric constant on the first passivation layer PA1 covering the data line DL and the thin film transistor T, the common electrode COM is formed. Then, after the second passivation layer PA2 covering the common electrode COM is formed, the pixel electrode PXL overlapping the common electrode COM is formed on the second passivation layer PA2 . In this structure, since the pixel electrode PXL is spaced apart by the data line DL, the first passivation layer PA1, the planarization layer PAC, and the second passivation layer PA2, the data line DL and the pixel electrode PXL In between, the parasitic capacity can be reduced.

The common electrode COM is formed in a rectangular shape corresponding to the shape of the pixel area, and the pixel electrode PXL is formed in the shape of a plurality of line segments. In particular, the pixel electrode PXL has a structure that vertically overlaps with the common electrode COM with the second passivation layer PA2 interposed therebetween. Accordingly, a fringe field is formed between the pixel electrode PXL and the common electrode COM. Liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy by the fringe field type electric field. A fringe field is formed between the pixel electrode PXL and the common electrode COM, so that liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy. In addition, the transmittance of light passing through the pixel region varies according to the degree of rotation of the liquid crystal molecules to realize grayscale.

The thin film transistor T used as a switch element of a pixel in the liquid crystal display may be implemented as first and/or second thin film transistors T1 and T2.

14 is a plan view illustrating the structure of one pixel in an organic light emitting diode display. 15 is a cross-sectional view illustrating the structure of the organic light emitting diode display taken along the cut line II-II' in FIG. 14 .

14 and 15 , the organic light emitting diode display includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor, and an organic light emitting diode OLE connected to the driving thin film transistor DT. .

The switching thin film transistor ST is formed at the intersection of the gate line GL and the data line DL. The switching thin film transistor ST supplies a data voltage from the data line DL to the gate electrode of the driving thin film transistor DT and the storage capacitor STG in response to a scan signal to select a pixel. The switching thin film transistor ST includes a gate electrode SG branching from the gate line GL, a semiconductor layer SSE, a source electrode SS, and a drain electrode SD. The driving thin film transistor DT drives the organic light emitting diode OLE of the pixel selected by the switching thin film transistor ST by controlling a current flowing through the organic light emitting diode OLED of the pixel according to the gate voltage. The driving thin film transistor DT has a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DSE, a source electrode DS connected to the driving current line VDD, and a drain and an electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE. An organic light emitting layer OL is interposed between the anode electrode ANO and the cathode electrode CAT. The cathode electrode CAT is connected to the base voltage line VSS. The storage capacitor STG is connected to the driving thin film transistor D1 to maintain a gate-source voltage of the driving thin film transistor D1.

Gate electrodes SG and DG of the switching thin film transistor ST and the driving thin film transistor DT are disposed on the substrate SUB. A gate insulating layer GI covers the gate electrodes SG and DG. The semiconductor layers SA and DA are disposed on a portion of the gate insulating layer GI overlapping the gate electrodes SG and DG. On the semiconductor layers SA and DA, the source electrodes SS and DS and the drain electrodes SD and DD are disposed to face each other with a predetermined interval therebetween. The drain electrode SD of the switching thin film transistor ST contacts the gate electrode DG of the driving thin film transistor DT through the drain contact hole DH passing through the gate insulating layer GI. A protective layer PAS covering the switching thin film transistor ST and the driving thin film transistor DT having such a structure is formed on the entire surface.

A color filter CF is disposed at a portion corresponding to the anode electrode ANO. The color filter CF preferably has as wide an area as possible. For example, it is preferable to have a shape overlapping many regions of the data line DL, the driving current line VDD, and the gate line GL of the previous stage. As described above, the surface of the substrate on which the switching thin film transistor ST, the driving thin film transistor DT, and the color filters CF are disposed is not flat and the level difference is severe. The organic light emitting diode (OLE) must be laminated on a flat surface so that light emission can be uniformly and uniformly emitted. Therefore, a planarization film (PAC) or an overcoat layer (OC) is laminated on the entire surface of the substrate for the purpose of flattening the surface of the substrate.

In addition, the anode electrode ANO of the organic light emitting diode OLE is disposed on the overcoat layer OC. Here, the anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH formed in the overcoat layer OC and the passivation layer PAS.

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On a substrate on which the anode electrode ANO is formed, a bank BA (or , bank pattern). The anode electrode ANO exposed by the bank BA becomes a light emitting area. An organic emission layer OL is stacked on the anode ANO exposed by the bank BA. In addition, a cathode electrode CAT is sequentially stacked on the organic light emitting layer OL. When the organic light emitting layer OL is made of an organic material emitting white light, a color assigned to each pixel by the color filter CF positioned below is indicated. The organic light emitting diode display having the structure shown in FIG. 11 becomes a bottom emission display device that emits light in a downward direction.

A storage capacitor STG is disposed between the gate electrode DG and the anode electrode ANO of the driving thin film transistor DT. The storage capacitor STG is connected to the driving thin film transistor DT so that a voltage applied to the gate electrode DG of the driving thin film transistor DT by the switching thin film transistor ST is stably maintained.

The semiconductor layer of the thin film transistor may be formed of a metal oxide semiconductor material, that is, the second semiconductor layer A2. The metal oxide semiconductor material has a characteristic that its characteristics are rapidly deteriorated when it is voltage driven in a state in which it is exposed to light. Accordingly, it is desirable to have a structure capable of blocking light from the outside in the upper and lower portions of the semiconductor layer. In the case of the thin film transistor substrate described above, the thin film transistor preferably has a bottom gate structure. That is, light entering from the bottom may be blocked to some extent by the gate electrode G, which is a metal material.

In the above-described thin film transistor substrate, a plurality of pixel regions arranged in a matrix manner are disposed. In addition, at least one thin film transistor is disposed in each of the unit pixel areas. That is, it has a structure in which a plurality of thin film transistors are distributed over the entire area of the substrate.

In addition to the thin film transistors ST and DT shown in FIGS. 14 and 15 , a thin film transistor may be further disposed in a pixel of the organic light emitting diode display. If necessary, a compensation thin film transistor for compensating for pixel deterioration is further provided to further supplement function or performance.

A thin film transistor substrate having a driving element embedded in the non-display area of the display device is also used. Hereinafter, a case in which a part of the driving circuit is directly formed on a substrate on which pixels are formed will be described in detail with reference to FIGS. 16 and 17 .

16 is a plan enlarged view illustrating a schematic structure of an organic light emitting diode display. 17 is a view taken along the cut line III-III' in FIG. 16 and shows a cross-sectional structure of the organic light emitting diode display. Here, a detailed description of the thin film transistor and the organic light emitting diode formed in the display area will be omitted.

With reference to FIG. 16, the structure on a plane is demonstrated. The organic light emitting diode display includes a substrate SUB divided into a display area AA displaying image information and a non-display area NA in which various elements for driving the display area AA are disposed. A plurality of pixel areas PA arranged in a matrix manner is defined in the display area AA. In FIG. 16 , pixel areas PA are indicated by dotted lines.

The pixel areas may have the same size or different sizes. In addition, three sub-pixels representing RGB (red, green, blue) colors may be regularly arranged as one unit. Each of the pixels may include an RGB sub-pixel and may further include a W (white) sub-pixel. In the simplest structure, the pixel areas PA have a cross structure of a plurality of gate lines GL running in a horizontal direction and a plurality of data lines DL and a plurality of driving current lines VDD running in a vertical direction. can be defined as

A data integrated circuit DIC in which a data driver for supplying a signal corresponding to image information to the data lines DL is integrated in the non-display area NA, which is defined on the outer periphery of the pixel area PA, and a gate line A gate driver GIP for supplying a scan signal to the GLs may be disposed. In Fig. 16, the multiplexer is omitted. In the case of high resolution higher than the VGA level, in which the number of data lines DL and driving current lines VDD increases, the data integrated circuit DIC is mounted on the outside of the substrate SUB, and the data integrated circuit Data connection pads may be disposed instead of (DIC).

In order to simplify the structure of the display device, the gate driver GIP is preferably directly formed on one side of the substrate SUB. In addition, a base voltage line VSS for supplying a base voltage is disposed at the outermost portion of the substrate SUB. The ground voltage line VSS is preferably disposed to receive a ground voltage supplied from the outside of the substrate SUB and supply the ground voltage to both the data driver DIC and the gate driver GIP. For example, the electromotive voltage line is connected to the data driver DIC to be separately mounted on the upper side of the substrate SUB, and outside the gate driver GIP disposed on the left and/or right side of the substrate SUB. It can be arranged as if wrapping the substrate in the.

In each pixel area PA, an organic light emitting diode, which is a key component of an organic light emitting diode display, and thin film transistors for driving the organic light emitting diode are disposed. The thin film transistors may be formed in the thin film transistor area TA defined at one side of the pixel area PA. The organic light emitting diode includes an anode electrode ANO, a cathode electrode CAT, and an organic light emitting layer OL interposed between the two electrodes. The area actually emitting light is determined by the area of the organic light emitting layer overlapping the anode electrode ANO.

The anode electrode ANO is formed to occupy a portion of the pixel area PA, and is connected to the thin film transistor formed in the thin film transistor area TA. An organic emission layer OL is deposited on the anode electrode ANO, and an area where the anode electrode ANO and the organic emission layer OL overlap is determined as an actual emission region. The cathode electrode CAT is formed as a single body so as to cover at least the area of the display area AA in which the pixel areas PA are disposed on the organic light emitting layer OL.

The cathode electrode CAT crosses the gate driver GIP and contacts the ground voltage line VSS disposed on the outer side of the substrate SUB. That is, the base voltage is applied to the cathode electrode CAT through the base voltage line VSS. The cathode electrode CAT receives the base voltage, the anode electrode ANO receives the image voltage, and the organic light emitting layer OL emits light by the voltage difference therebetween to display image information.

The cathode electrode CAT is formed of a transparent conductive material such as indium-tin oxide or indium-zinc oxide. Such a transparent conductive material tends to have a higher resistivity than a metal material. In the case of the top emission type, since the anode electrode ANO is formed of a metal material having low resistance and high light reflectance, a resistance problem does not occur. On the other hand, the cathode electrode CAT is formed of a transparent conductive material because light must pass therethrough.

The gate driver GIP may include a thin film transistor formed together in the process of forming the switching thin film transistor ST and the driving thin film transistor DT. The switching thin film transistor ST formed in the pixel area PA includes a gate electrode SG, a gate insulating layer GI, a channel layer SA, a source electrode SS, and a drain electrode SD. In addition, the driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a gate insulating layer GI, a channel layer DA, a source electrode DS, and a drain electrode ( DD) is included.

A passivation layer PAS and a planarization layer PL are successively deposited on the thin film transistors ST and DT. An isolated rectangular anode ANO occupying only a certain portion of the pixel area PA is formed on the planarization layer PL. The anode electrode ANO contacts the drain electrode DD of the driving thin film transistor DT through a contact hole penetrating the passivation layer PAS and the planarization layer PL.

A bank BA defining a light emitting area is deposited on the substrate on which the anode electrode ANO is formed. The bank BA exposes most of the anode electrode ANO. An organic light emitting layer OL is stacked on the anode electrode ANO exposed on the bank BA pattern. A cathode electrode CAT made of a transparent conductive material is stacked on the bank BA. Accordingly, the organic light emitting diode OLE including the anode electrode ANO, the organic light emitting layer OL, and the cathode electrode CAT is disposed.

The organic light emitting layer OL may emit white light, and a color may be expressed using a separately formed color filter CF. In this case, the organic light emitting layer OL is preferably stacked to cover at least all of the display area AA.

Preferably, the cathode electrode CAT covers the display area AA and the non-display area NA so as to be in contact with the ground voltage line VSS disposed on the outer side of the substrate SUB beyond the gate driver GIP. . Accordingly, the base voltage may be applied to the cathode electrode CAT through the base voltage line VSS.

The ground voltage line VSS may be formed of the same material as the gate electrode G and on the same layer. In this case, the cathode electrode CAT may be in contact with the passivation layer PAS covering the base voltage line VSS and the contact hole penetrating the gate insulating layer GI. Alternatively, the base voltage line VSS may be formed of the same material as the source-drain electrodes SS-SD and DS-DD and on the same layer. In this case, the ground voltage line VSS may contact the cathode electrode CAT through a contact hole penetrating the passivation layer PAS.

10 and 11 illustrating the fourth application example of the present invention, for convenience, the thin film transistors ST and DT of the organic light emitting diode display and the thin film transistor structures of the gate driver GIP are only schematically illustrated. The structures of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, the second thin film transistor T2 having an oxide semiconductor layer may be applied to the switching thin film transistor ST. The first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the driving thin film transistor DT. In addition, the first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the gate driver GIP. If necessary, the gate driver GIP may include a CMOS type thin film transistor having both a P-MOS type and an N-MOS type.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the present invention should not be limited to the contents described in the detailed description, but should be defined by the claims.

GL: gate wiring DL: data wiring
VDD: drive current wiring PA: pixel area
T, ST, DT: thin film transistor AA: display area
NA: non-display area GE: gate electrode
A1, A2: semiconductor layer SE: source electrode
DE: drain electrode GI: gate insulating film
ILD: intermediate insulating film PAS: protective film
PAC: flattening film 100: display panel
200: data driver 210: multiplexer
300, GIP: gate driver

Claims (16)

A display device having a driving circuit for writing data into a pixel, the display device comprising:
a first semiconductor layer provided on the substrate;
a first insulating layer provided on the substrate to cover the first semiconductor layer;
a gate electrode provided on the first insulating layer and overlapping the first semiconductor layer;
a second insulating layer provided on the first insulating layer to cover the gate electrode; and
a second semiconductor layer provided on the second insulating layer and overlapping the first semiconductor layer and the gate electrode;
one or more thin film transistors having the first semiconductor layer and the second semiconductor layer are embedded in the pixel and the driving circuit;
The second insulating layer includes a first intermediate insulating film having a nitride film, and a second intermediate insulating film having an oxide film,
the first intermediate insulating film and the second intermediate insulating film extend from the pixel to the driving circuit;
The thickness of the second intermediate insulating layer in the region overlapping the first semiconductor layer in the pixel is thinner than the thickness of the second intermediate insulating layer in the region overlapping the second semiconductor layer in the driving circuit. The method of claim 1,
The thin film transistor is
a first thin film transistor having the first semiconductor layer; and
a second thin film transistor having the second semiconductor layer;
The second thin film transistor is a switch element for selecting the pixel in response to a scan signal from a gate wiring,
The first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor. The method of claim 1,
The one or more thin film transistors are combined to operate as a switching element or a driving element of the pixel. The method of claim 1,
The driving circuit is
a data driver converting input image data into a data voltage and outputting the converted data;
a multiplexer that distributes the data voltage from the data driver to data lines;
a gate driver outputting a scan pulse synchronized with the data voltage to gate lines;
The multiplexer and the gate driver are provided on the same substrate together with the pixel,
The display device in which the first semiconductor layer and the second semiconductor layer are embedded in the multiplexer or the gate driver. The method of claim 1,
The first semiconductor layer comprises a polysilicon semiconductor,
and the second semiconductor layer includes an oxide semiconductor. delete 6. The method of claim 5,
a source electrode connected to a source region of the first semiconductor layer through a first contact hole penetrating the first insulating layer and the second insulating layer; and
and a drain electrode connected to a drain region of the first semiconductor layer through a second contact hole penetrating the first insulating layer and the second insulating layer. delete 6. The method of claim 5,
a source electrode partly connected to the second semiconductor layer and partly connected to the first semiconductor layer through a contact hole penetrating the first insulating layer and the second insulating layer; and
and a drain electrode connected to the second semiconductor layer on the second insulating layer. A display device having a driving circuit for writing data into a pixel, the display device comprising:
a first semiconductor layer provided on the substrate;
a first insulating layer provided on the first semiconductor layer;
a gate electrode provided on the first insulating layer and overlapping the first semiconductor layer;
a second insulating layer provided on the substrate to cover the gate electrode; and
a second semiconductor layer provided on the second insulating layer and overlapping the first semiconductor layer and the gate electrode;
one or more thin film transistors having the first semiconductor layer and the second semiconductor layer are embedded in the pixel and the driving circuit;
The second insulating layer includes a first intermediate insulating film having a nitride film, and a second intermediate insulating film having an oxide film,
the first intermediate insulating film and the second intermediate insulating film extend from the pixel to the driving circuit;
The thickness of the second intermediate insulating layer in the region overlapping the first semiconductor layer in the pixel is thinner than the thickness of the second intermediate insulating layer in the region overlapping the second semiconductor layer in the driving circuit. 11. The method of claim 10,
The thin film transistor is
a first thin film transistor having the first semiconductor layer; and
a second thin film transistor having the second semiconductor layer;
The second thin film transistor is a switch element for selecting the pixel in response to a scan signal from a gate wiring,
The first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor. 11. The method of claim 10,
The one or more thin film transistors operate as a switching element or a driving element of the pixel. 11. The method of claim 10,
The driving circuit is
a data driver converting input image data into a data voltage and outputting the converted data;
a multiplexer that distributes the data voltage from the data driver to data lines;
a gate driver outputting a scan pulse synchronized with the data voltage to gate lines;
The multiplexer and the gate driver are provided on the same substrate together with the pixel,
The display device in which the first semiconductor layer and the second semiconductor layer are embedded in the multiplexer or the gate driver. 11. The method of claim 10,
The first semiconductor layer comprises a polysilicon semiconductor,
and the second semiconductor layer includes an oxide semiconductor. delete 15. The method of claim 14,
a first source electrode connected to a source region of the first semiconductor layer through a first contact hole penetrating the second insulating layer;
a drain electrode connected to the drain region of the first semiconductor layer through a second contact hole penetrating the second insulating layer; and
Further comprising a second source electrode provided on the second insulating layer,
The second semiconductor layer covers the second source electrode and the drain electrode.

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