KR102407455B1 - Memory device - Google Patents

Abstract

A memory device according to an embodiment of the present invention provides a memory cell array including a plurality of memory cells including a switch element and a plurality of memory cells connected to the switch element and having an information storage element having a phase change material, and an operating current applied to the memory cells. A memory that performs a control operation on the memory cell by input Includes controller.

Description

memory device {MEMORY DEVICE}

The present invention relates to a memory device.

A memory device using a resistor includes a phase change random access memory (PRAM), a resistive memory device (ReRAM), and a magnetic memory device (MRAM: Magnetic RAM). Unlike a dynamic memory device (DRAM), which records data by charging or discharging electric charge, a memory device using a resistor may write or erase data by using a change in resistance.

One of the objects of the technical idea of the present invention is to provide a memory device capable of increasing a sensing margin of each memory cell and at the same time minimizing an unintentional change in threshold voltage occurring in a memory cell during operation. is in

A memory device according to an embodiment of the present invention provides a memory cell array including a plurality of memory cells including a switch element and a plurality of memory cells connected to the switch element and having an information storage element having a phase change material, and an operating current applied to the memory cells. A memory that performs a control operation on the memory cell by input Includes controller.

A memory device according to an embodiment of the present invention includes a memory having a first electrode, a switch element connected to the first electrode, an information storage element connected to the switch element, and a second electrode connected to the information storage element A memory cell array including a plurality of cells, a read current is input to the memory cell to read data stored in the memory cell, and a compensation current is applied to at least one of before and after the input of the read current to the second electrode Includes input memory controller.

A memory device according to an embodiment of the present invention includes a memory having a first electrode, a switch element connected to the first electrode, an information storage element connected to the switch element, and a second electrode connected to the information storage element a memory cell array including a plurality of cells, and a memory controller configured to input a program current to the memory cells to store data in the memory cells, and to input a compensation current to the second electrode after the input of the program current do.

According to an embodiment of the present invention, a predetermined compensation current may be input before and/or after executing a control operation such as reading data from or writing data to the memory cell, and the compensation current is Information can flow from the storage element to the switch element within the cell. Accordingly, it is possible to effectively secure the sensing margin of the memory cell before and/or after the control operation is executed, and it is possible to stably operate the memory device.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic block diagram illustrating a memory device according to an embodiment of the present invention.
2 is a diagram schematically illustrating a memory cell array included in a memory device according to an embodiment of the present invention.
3 is a diagram schematically illustrating a structure of a memory cell included in a memory device according to an embodiment of the present invention.
4 and 5 are diagrams provided to explain an operation of a memory device according to an embodiment of the present invention.
6 is a diagram provided to explain an operation of a memory device according to an embodiment of the present invention.
7 and 8 are diagrams provided to explain a read operation of a memory device according to an embodiment of the present invention.
9 is a diagram illustrating a read voltage distribution of a memory device according to an embodiment of the present invention.
10 is a diagram provided to explain a read operation of a memory device according to an embodiment of the present invention.
11 is a diagram illustrating a read voltage distribution of a memory device according to an embodiment of the present invention.
12 is a diagram provided to explain an operation of a memory device according to an embodiment of the present invention.
13 is a diagram provided to explain a program operation of a memory device according to an embodiment of the present invention.
14 is a diagram illustrating a read voltage distribution of a memory device according to an embodiment of the present invention.
15 is a schematic block diagram illustrating an electronic device including a memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram illustrating a memory device according to an embodiment of the present invention. 2 is a diagram schematically illustrating a memory cell array included in a memory device according to an embodiment of the present invention.

First, referring to FIG. 1 , a memory device 10 according to an exemplary embodiment may include a memory controller 20 and a memory cell array 30 . The memory controller 20 may include a control logic 21 , a row driver 22 , a column driver 23 , and the like. The memory cell array 30 may include a plurality of memory cells MC.

In an embodiment, the row driver 22 may be connected to the memory cells MC through the first conductive line line CL1 , and the column driver 23 may be connected to the memory cells MC through the second conductive line CL2 . ) can be associated with In an embodiment, the row driver 22 may include an address decoder circuit for selecting a memory cell MC from which data is to be written or data is read, and the column driver 23 may include data to the memory cell MC. It may include a read/write circuit for writing data or reading data from the memory cell MC. Operations of the row driver 22 and the column driver 23 may be controlled by the control logic 21 . Each of the row driver 22 and the column driver 23 may be connected to the memory cell MC through the first conductive line line CL1 and the second conductive line CL2 . For example, each of the first conductive line line CL1 and the second conductive line CL2 may correspond to a word line and a bit line.

Referring to FIG. 2 , a memory cell array 30 according to an exemplary embodiment may include a plurality of memory cells MC. The memory cells MC may be provided at intersections of the first conductive line line CL1 and the second conductive line CL2 . That is, each of the memory cells MC may be connected to one first conductive line line CL1 and one second conductive line CL2 .

Each of the memory cells MC may include a switch element SW and an information storage element VR. In an embodiment, the switch element SW may include at least one of a PN junction diode, a Schottky diode, and an ovonic threshold switch OTS. Meanwhile, in an embodiment, the information storage device VR may be formed of a phase change material having any one of a chalcogenide material and a super-lattice. That is, the information storage device VR may include a phase change material capable of phase transition into an amorphous phase and a crystalline phase depending on heating time and temperature. The information storage element VR and the switch element SW may be connected in series with each other.

The memory controller 20 converts the phase change material of the information storage device VR included in each of the plurality of memory cells MC into an amorphous phase or a second conductive line CL2 through the first conductive line line CL1 and the second conductive line CL2 . By making a phase transition to the crystalline phase, data can be recorded or erased. In an embodiment, the memory controller 20 increases the resistance of the information storage device VR by changing the phase change material of the information storage device VR included in the memory cell MC to an amorphous phase, and writes data. can Conversely, the memory controller 20 may reduce the resistance of the information storage device VR and erase data by changing the phase change material of the information storage device VR included in the memory cell MC to a crystalline phase. . The memory controller 20 may read data of each of the plurality of memory cells MC by detecting a resistance or a threshold voltage of the information storage device VR included in each of the plurality of memory cells MC.

3 is a diagram schematically illustrating a structure of a memory cell included in a memory device according to an embodiment of the present invention.

Referring to FIG. 3 , in the memory device 100 according to an embodiment of the present invention, a first memory cell MC1 and a second word line are provided between a first word line 101 and a bit line 103 . A second memory cell MC2 provided between the 102 and the bit line 103 may be included. The first memory cell MC1 and the second memory cell MC2 may each operate as independent memory cells.

The first memory cell MC1 may include a first heating electrode 110 , a first information storage device 120 , and a first switch device 130 . The first switch element 130 may include a first switch electrode 131 , a second switch electrode 133 , and a first selection layer 133 disposed therebetween. In an embodiment, the first selection layer 133 may include an Ovonic Threshold Switch (OTS) material. When a voltage greater than a threshold voltage is applied between the first switch electrode 131 and the second switch electrode 133 , a current may flow through the first selection layer 133 .

The first information storage device 120 may include a phase change material, and in an embodiment, may include a chalcogenide material. For example, the first information storage device 120 may include Ge-Sb-Te (GST), and stores the first information according to the types and chemical composition ratios of elements included in the first information storage device 120 . The crystallization temperature, melting point, and phase change rate according to the crystallization energy of the device 120 may be determined.

The second memory cell MC2 may have a structure similar to that of the first memory cell MC1 . Referring to FIG. 3 , the second memory cell MC2 may include a second heating electrode 140 , a second information storage device 150 , and a second switch device 160 . The structure and characteristics of each of the second heating electrode 140 , the second information storage element 150 and the second switch element 160 , the first heating electrode 110 , the first information storage element 120 , and the second 1 may be similar to the switch element 130 . Hereinafter, a method of writing and erasing data will be described with reference to the first memory cell MC1 as an example.

When a voltage is supplied through the first word line 101 and the bit line 103 , at the interface between the first heating electrode 110 and the first information storage element 120 , Joule heat according to the voltage is generated. This can happen. The phase change material constituting the first information storage element 120 may change from an amorphous phase to a crystalline phase or from a crystalline phase to an amorphous phase by the Joule heat. The first information storage device 120 may have a high resistance in an amorphous phase and a low resistance in a crystalline phase. In an embodiment, data '0' or '1' may be defined according to the resistance value of the first information storage element 120 .

In order to write data to the first memory cell MC1 , a program voltage may be supplied through the first word line 101 and the bit line 103 . The program voltage is greater than the threshold voltage of the ovonic threshold switch material included in the first switch element 130 , and thus a current may flow through the first switch element 130 . The phase change material included in the first information storage device 120 may change from an amorphous phase to a crystalline phase by the program voltage, and thus data may be recorded in the first memory area. In an embodiment, a case in which the phase change material included in the first information storage device 120 has a crystalline phase may be defined as a set state.

Meanwhile, in order to erase data written in the first memory cell MC1 , the phase change material included in the first information storage device 120 may return from a crystalline phase to an amorphous phase. For example, a predetermined erase voltage may be supplied through the first word line 101 and the bit line 103 . The phase change material included in the first information storage device 120 may change from a crystalline phase to an amorphous phase by the erase voltage. For example, the maximum value of the erase voltage may be greater than the maximum value of the program voltage, and the period during which the erase voltage is supplied may be shorter than the period during which the program voltage is supplied.

As described above, the resistance values of the information storage elements 120 and 150 may change according to the state of the phase change material included in the information storage elements 120 and 150 , and the memory controller controls the information storage elements 120 . , 150) can distinguish between data ‘0’ and ‘1’. Accordingly, as the resistance difference between the information storage elements 120 and 150 that appears according to the state of the phase change material included in the information storage elements 120 and 150 increases, the memory controller can accurately write or read data.

4 and 5 are diagrams provided to explain an operation of a memory device according to an embodiment of the present invention.

The memory device according to an embodiment of the present invention may operate by power supplied from the memory controller 220 to the memory cell 210 . 4 and 5 , the memory controller 220 applies at least one of a first current I1 flowing in a first direction and a second current I2 flowing in a second direction to the memory cell 210 . can be entered. In an embodiment, the first direction and the second direction may be opposite to each other.

The memory cell 210 may include a lower electrode 211 , a heating electrode 212 , an information storage element 214 , a switch element 215 , and an upper electrode 216 . The lower electrode 211 and the upper electrode 216 may receive a voltage output from the memory controller 220 through a word line or a bit line. An insulating layer 213 may be provided around the heating electrode 212 , and in a partial region 214a of the information storage element 214 adjacent to the heating electrode 212 , the first current I1 or the second A phase change may occur due to the current I2.

Referring to FIG. 4 , the first current I1 supplied in the first direction by the memory controller 220 may flow from the switch element 215 to the information storage element 214 in the memory cell 210 . Conversely, referring to FIG. 5 , the second current I2 supplied in the second direction may flow from the information storage element 214 to the switch element 215 in the memory cell 210 . Accordingly, due to the Peltier effect, the effect of heat generated from the heating electrode 212 may be less when the second current I2 is supplied than when the first current I1 is supplied.

In an embodiment, a program operation for writing data may be executed by inputting a program current in the first direction. In an embodiment, the information storage device 214 may change from a crystalline phase to an amorphous phase by the program current. When the resistance of the memory cell 210 is high, the memory controller 220 may determine that the memory cell 210 is programmed.

Meanwhile, a read operation for determining data of the memory cell 210 may be performed by inputting a read current in the first direction or the second direction. In order to prevent an unintentional state change of the information storage device 214 in the memory cell 210 due to a read operation, the read current may have a smaller magnitude than the program current. The memory controller 220 may measure the resistance value of the memory cell 210 by supplying a read current to the memory cell 210 , and whether data is written to the memory cell 210 according to the size of the resistance value. can be judged

In the memory device according to an embodiment of the present invention, data may be written or erased using a phase change phenomenon of the information storage element 214 included in the memory cell 210 . For example, when the information storage element 214 has a crystalline phase and has a relatively low resistance value and when the information storage element 214 has an amorphous phase and has a relatively high resistance value, data '0' and You can program and read `1'. Accordingly, as the voltage difference detected from the memory cell 210 increases according to the state of the information storage device 214 , the memory controller 220 may accurately read data written to the memory cell 210 .

Meanwhile, a drift phenomenon may occur in the switch element 215 , and a difference in voltage detected by the memory cell 210 may decrease according to the state of the information storage element 214 due to the drift phenomenon. For example, due to the drift phenomenon occurring in the switch element 215 , the total resistance of the memory cell 210 in which the information storage element 214 has a crystalline phase may increase, and as a result, the information storage element 214 may have a crystalline phase. The voltage difference of the memory cell 210 according to the state may decrease. Accordingly, there may be a problem in that data stored in the memory cell 210 cannot be accurately read due to the drift phenomenon.

In an embodiment of the present invention, before the memory controller 220 reads data written to the memory cell 210 , a compensation current may be input to the memory cell 210 to solve the problem caused by the drift phenomenon. In an embodiment, the memory controller 220 may input the compensation current in the same second direction as the second current I2 , and use the compensation current to the switch device 215 while minimizing the effect on the information storage device 214 . can only be turned on. Accordingly, it is possible to compensate for an increase in resistance of the memory cell 210 having the crystalline information storage element 214 due to a drift phenomenon occurring in the switch element 215 .

In an embodiment, the compensation current may be input after the read operation is completed. The compensation current input after the read operation is completed may compensate for the increase in the resistance of the memory cell 210 due to the drift phenomenon of the switch element 215 or compensate for the increase in the resistance of the memory cell 210 due to the read current. have. Alternatively, according to an embodiment, the compensation current may be input both before and after the read operation.

In addition, in one embodiment of the present invention, after the memory controller 220 supplies a program voltage to the memory cell 210 , a compensation current is applied to the memory cell 210 for the purpose of quickly stabilizing the information storage device 214 . You can complete the program operation by entering The compensation current input to the memory cell 210 in the program operation may be a voltage for supplying energy that causes a drift phenomenon in the information storage device 214 whose phase is changed to an amorphous phase by the program voltage. By the compensation current, the information storage element 214 may be rapidly stabilized in the amorphous phase, and as a result, the resistance value of the information storage element 214 may rapidly increase. Accordingly, the resistance difference of the memory cell 210 according to the phase change of the information storage element 214 may be increased, and the memory controller 220 may accurately read data written to the memory cell 210 . The compensation current input after the program operation may be input in the same second direction as the second current I2 to minimize the effect on the memory cell 210 .

6 is a diagram provided to explain an operation of a memory device according to an embodiment of the present invention.

First, referring to FIG. 6A , a set read voltage distribution 300 detected when a read current is input to memory cells having a set state, and a read in memory cells having a reset state A reset read voltage distribution 400 detected when a current is input is shown. In an embodiment, the set state may be a state in which the information storage element has a crystalline phase, and the reset state may be a state in which the information storage element has an amorphous phase. Since the information storage element has a relatively lower resistance in the set state, the set read voltage distribution 300 may be smaller than the reset read voltage distribution 400 .

The exemplary embodiment shown in FIG. 6( a ) is an ideal case in which a drift phenomenon does not occur in a switch element, etc., and the set read voltage distribution 300 may have the first set distribution 301 , and the reset read voltage distribution 400 may have a first reset distribution 401 . Referring to FIG. 6A , a predetermined sensing margin SM may exist between the first set distribution 301 and the first reset distribution 401 . The memory controller may determine the state of the memory cell as one of a set state and a reset state by comparing the read voltage detected from the memory cells with the reference voltage V _REF positioned within the sensing margin SM.

Next, the embodiment shown in FIG. 6(b) may correspond to a case in which a drift phenomenon occurs in a switch element of a memory cell having a set state. Referring to FIG. 6B , the set read voltage distribution 300 may increase from the first set distribution 301 to the second set distribution 302 due to a drift phenomenon occurring in the switch element of the memory cell. Comparing the embodiment shown in FIG. 6(b) with the embodiment shown in FIG. 6(a), as the set read voltage distribution 300 increases to the second set distribution 302, the sensing margin SM increases. can decrease. If the difference between the first set distribution 301 and the second set distribution 302 is large, a portion of the second set distribution 302 may overlap the reference voltage V _REF , and the memory controller receives data from the memory cell. An error may occur during a read operation.

7 and 8 are diagrams provided to explain a read operation of a memory device according to an embodiment of the present invention.

First, referring to FIG. 7 , in an embodiment of the present invention, after inputting the read current I _RD , the compensation current I _CP may be input. Referring to FIG. 7A , the compensation current I _CP may be input in the opposite direction to the read current I _RD . For example, the read current I _RD may be input to flow from the switch element to the information storage element in the memory cell, and the compensation current I _CP may be input to flow from the information storage element to the switch element in the memory cell. can Accordingly, the compensation current I _CP may turn on the switch element while minimizing the effect on the information storage element, and may eliminate a drift phenomenon occurring in the switch element.

Next, referring to FIG. 7B , the compensation current I _CP and the read current I _RD may be input in the same direction. In the exemplary embodiment illustrated in FIG. 7B , both the compensation current I _CP and the read current I _RD may be input to flow from the information storage device to the switch device in the memory cell. Accordingly, heat generated in the heater of the memory cell by the read current I _RD may be minimized, and a phase change phenomenon that may occur in the information storage device may be effectively suppressed. In addition, a drift phenomenon occurring in the switch element may be eliminated by using the compensation current I _CP .

Meanwhile, in the exemplary embodiment illustrated in FIG. 8 , the compensation current I _CP may be input before the read current I _RD is input. Referring to FIG. 8A , the compensation current I _CP may be input in the opposite direction to the read current I _RD . For example, the read current I _RD may be input to flow from the switch element to the information storage element in the memory cell, and the compensation current I _CP may be input to flow from the information storage element to the switch element in the memory cell. can Accordingly, the compensation current I _CP may turn on the switch element while minimizing the effect on the information storage element, and may eliminate a drift phenomenon occurring in the switch element.

In the exemplary embodiment illustrated in FIG. 8B , the compensation current I _CP and the read current I _RD may be input in the same direction. In the exemplary embodiment illustrated in FIG. 8B , both the compensation current I _CP and the read current I _RD may be input to flow from the information storage device to the switch device in the memory cell. Accordingly, heat generated in the heater of the memory cell by the read current I _RD may be minimized, and a phase change phenomenon that may occur in the information storage device may be effectively suppressed. In addition, a drift phenomenon occurring in the switch element may be eliminated by using the compensation current I _CP .

In the embodiments described with reference to FIGS. 7 and 8 , the magnitude of the compensation current I _CP may be greater than the magnitude of the read current I _RD , and the input time of the compensation current I _CP is the read current I _RD ) may be shorter than the input time. For example, the read current I _RD may be smaller than the first threshold current having a magnitude at which a phase change may occur in the information storage device, whereas the compensation current I _CP may be greater than the first threshold current. However, according to various embodiments of the present disclosure, the magnitude and input time of the compensation current I _CP may be variously modified. In an embodiment, unlike the embodiments shown in FIGS. 7 and 8 , the compensation current I _CP may be input to the memory cells by pulses generated multiple times.

9 is a diagram illustrating a read voltage distribution of a memory device according to an embodiment of the present invention.

As an example, FIG. 9 may be a diagram illustrating a set read voltage distribution 300 and a reset read voltage distribution 400 detected in memory cells. First, referring to FIG. 9A , a predetermined sensing margin SM exists between a first set distribution 301 of memory cells having a set state and a first reset distribution 401 of memory cells having a reset state. can The memory controller may read data of the memory cells by comparing a read voltage obtained by inputting a read current I _RD to the memory cells with a reference voltage V _REF existing within the sensing margin SM.

According to an embodiment of the present invention, the set read voltage distribution 300 may increase to the second set distribution 302 as shown in FIG. 9B due to various factors. In an embodiment, the set read voltage distribution 300 may increase due to a drift phenomenon occurring in the switch element or a soft program phenomenon in which a weak phase change occurs in the information storage element due to the read current I _RD . If the sensing margin SM decreases as the set read voltage distribution 300 increases, a problem may occur in the accuracy of the read operation. In an embodiment of the present invention, the above problem may be solved by inputting the compensation current I _CP to the memory cells before or after inputting the read current I _RD .

9( c ) may be a diagram illustrating a read voltage distribution of memory cells displayed by inputting a compensation current I _CP . Referring to FIG. 9(c) , the drift phenomenon of the switch element may be removed by the compensation current I _CP input before or after the read current I _RD is input, and the set read voltage distribution 300 ) may decrease from the second set distribution 302 to the third set distribution 303 . Accordingly, the sensing margin SM between the set read voltage distribution 300 and the reset read voltage distribution 400 may increase, and the accuracy of the read operation may be improved.

10 is a diagram provided to explain a read operation of a memory device according to an embodiment of the present invention.

First, referring to FIG. 10 , in an embodiment of the present invention, first and second compensation currents I _CP1 and I _CP2 may be input before and after input of the read current I _RD . 10A , the first and second compensation currents I _CP1 and I _CP2 may be input in opposite directions to the read current I _RD . For example, the read current I _RD is input to flow from the switch element to the information storage element in the memory cell, while the first and second compensation currents I _CP1 and I _CP2 are supplied from the information storage element in the memory cell. It can be input to flow to the switch element. Accordingly, the first and second compensation currents I _CP1 and I _CP2 may turn on the switch element while minimizing the effect on the information storage element, and may eliminate a drift phenomenon occurring in the switch element.

Next, referring to FIG. 10B , the first and second compensation currents I _CP1 and I _CP2 and the read current I _RD may be input in the same direction. In the embodiment shown in FIG. 10( b ), the first and second compensation currents I _CP1 , I _CP2 and the read current I _RD are both input to flow from the information storage element to the switch element in the memory cell. can be Accordingly, heat generated in the heater of the memory cell by the read current I _RD may be minimized, and a phase change phenomenon that may occur in the information storage device may be effectively suppressed. In addition, a drift phenomenon occurring in the switch element may be eliminated by using the first and second compensation currents I _CP1 and I _CP2 .

Although it is illustrated in FIG. 10 that the first compensation current I _CP1 has a smaller magnitude than the second compensation current I _CP2 , the present invention is not limited thereto. In some embodiments, the first compensation current I _CP1 and the second compensation current I _CP2 have the same magnitude or the first compensation current I _CP1 is smaller than the second compensation current I _CP2 . can Meanwhile, the input time of each of the first compensation current I _CP1 and the second compensation current I _CP2 may also be variously selected.

11 is a diagram illustrating a read voltage distribution of a memory device according to an embodiment of the present invention.

As an example, in FIG. 11 , when the first and second compensation currents I _CP1 and I _CP2 are input before and after inputting the read current I _RD to the memory cells, respectively, as shown in FIG. 10 . It may be a diagram showing the distribution of the displayed read voltage. Referring to FIG. 11 , a sensing margin SM may exist between the set read voltage distribution 310 and the reset read voltage distribution 410 of the memory cells.

First, referring to FIG. 11A , read voltages of memory cells having a set state may have a first set distribution 311 , and read voltages of memory cells having a reset state may have a first reset distribution 411 . can have When the distribution of read voltages detected from the memory cells is the same as in FIG. 10A , the memory controller obtains a read voltage by inputting a read current I _RD to the memory cells, and sets the read voltage to a reference voltage V _REF . In comparison with , data of memory cells may be read. The reference voltage V _REF may be a voltage included in the sensing margin SM.

However, in an embodiment of the present invention, the set read voltage distribution 310 may be changed as shown in FIG. 11( b ) due to various factors. In one embodiment, the set read voltage distribution 310 is the second set by a drift phenomenon occurring in the switch element, and/or a soft program phenomenon in which a weak phase change occurs in the information storage element by the read current I _RD , etc. distribution 312 may increase. When the sensing margin SM decreases as the set read voltage distribution 310 increases to the second set distribution 312 , a problem may occur in the accuracy of the read operation. In an embodiment of the present invention, before and after inputting the read current I _RD , the first and second compensation currents I _CP1 and I _CP2 are input to the memory cells to solve the above problem. .

11C may be a diagram illustrating a read voltage distribution of memory cells that appear after the first compensation current I _CP1 is input. Referring to FIG. 11(c) , the drift phenomenon of the switch element may be removed by the first compensation current I _CP1 input before the read current I _RD is input, and the set read voltage distribution 310 ) may decrease from the second set distribution 312 to the third set distribution 313 . Accordingly, the sensing margin SM between the set read voltage distribution 310 and the reset read voltage distribution 410 may increase, and the accuracy of the read operation may be improved.

Next, referring to FIG. 11(d) , a weak phase change may occur in the information storage device of the memory cell due to the read current I _RD , and accordingly, the set read voltage distribution 310 changes to the third set distribution 313 . ) to the fourth set distribution 314 . Due to the soft programming phenomenon by the read current I _RD , the sensing margin SM may decrease, which may cause deterioration of the accuracy of the next read operation.

In the present invention, after reading the data of the memory cells by inputting the read current I _RD , the second compensation current I _CP2 may be input to compensate for the decrease in the sensing margin SM as described above. Referring to FIG. 11(e) , the set read voltage distribution 310 may decrease to the fifth set distribution 305 by the second compensation current I _CP2 , and the sensing margin SM may increase therefrom. have. Accordingly, it is possible to secure a sufficient sensing margin SM in a read operation to be executed later, and to minimize an error rate in the read operation.

12 is a diagram provided to explain an operation of a memory device according to an embodiment of the present invention.

12 , a set read voltage distribution 500 detected in memory cells having a set state and a reset read voltage distribution 600 detected in memory cells having a reset state are illustrated. The set read voltage and reset read voltage may be voltages detected by inputting a predetermined read current to each of the memory cells having the set state and the memory cells having the reset state. As described above, since the memory cells in the set state have a relatively lower resistance than the memory cells in the reset state, the set read voltage distribution 500 may be smaller than the reset read voltage distribution 600 .

12A may be a graph illustrating a state in which memory cells included in a memory device are not programmed. That is, FIG. 12A may correspond to a state in which all memory cells have a set state, and thus only the set read voltage distribution 500 may appear.

12B may be a graph illustrating a state in which some of memory cells included in the memory device are programmed and switched to a reset state. Referring to FIG. 12( b ), a reset read voltage distribution 600 is shown together with the set read voltage distribution 500 , and the set read voltage distribution 500 has a first set distribution 501 , and a reset read voltage distribution ( 600 may have a first reset distribution 601 . A sensing margin SM may exist between the first set distribution 501 and the first reset distribution 601 . The memory device may perform a read operation of reading data programmed into each of the memory cells by comparing the read voltage detected from each of the memory cells with a predetermined reference voltage V _REF included in the sensing margin SM.

As the sensing margin SM between the set read voltage distribution 500 and the reset read voltage distribution 600 increases, the error rate of the read operation may be reduced. In the memory device according to an embodiment of the present invention, an information storage element included in the memory cell may change from a crystalline phase to an amorphous phase by a program operation for writing data to the memory cell. However, more time may be required until the information storage device is stabilized in the amorphous phase and the resistance of the memory cell is increased. Therefore, the sensing margin SM may not be sufficiently secured as shown in FIG. .

12( c ) may be a graph illustrating the set read voltage distribution 500 and the reset read voltage distribution 600 after the program operation is terminated and time elapses. As described above, the information storage element of the memory cells switched to the reset state as time elapses after the end of the program operation may be stabilized in the amorphous phase. Accordingly, as shown in FIG. 12C , the reset read voltage distribution 600 may increase from the first reset distribution 601 to the second reset distribution 602 .

However, since it takes time until the memory cells programmed in the reset state are stabilized and the reset read voltage distribution 600 increases, the sensing margin SM cannot be effectively secured immediately after the program operation. In addition, as time elapses after the program operation is terminated, the resistance of the memory cells may increase due to a drift phenomenon occurring in the switch element of the memory cells. In particular, resistance of the memory cells in the set state may increase due to a drift phenomenon occurring in the memory cells in the set state. Therefore, as shown in FIG. 12(c) , the set read voltage distribution 500 may increase from the first set distribution 501 to the second set distribution 502 , and the sensing margin SM increases immediately after the program operation. may not increase significantly.

In the present invention, the above problem can be solved by inputting a program current for writing data to the memory cells and then inputting a predetermined compensation current to the memory cells. Hereinafter, it will be described with reference to FIGS. 13 and 14 .

13 is a diagram provided to explain a program operation of a memory device according to an embodiment of the present invention, and FIG. 14 is a diagram illustrating a read voltage distribution of a memory device according to an embodiment of the present invention.

First, referring to FIG. 13 , in an embodiment of the present invention, after inputting the program current I _PGM , the compensation current I _CP may be input. The compensation current I _CP may be input in a direction opposite to the program current I _PGM . For example, the program current I _PGM may be input to flow from the switch element to the information storage element in the memory cell, and the compensation current I _CP may be input to flow from the information storage element to the switch element in the memory cell. can

In an embodiment, the compensation current I _CP may be input to the memory cells in the reset state in which the information storage device is transitioned to the amorphous phase by the program current I _PGM . By the compensation current I _CP , the information storage element included in the memory cells in the reset state may be rapidly stabilized in the amorphous phase, and thus the resistance of the memory cells in the reset state may be rapidly increased. Accordingly, it is possible to quickly secure a sensing margin after the program operation, and to operate the memory device accurately.

Also, in an embodiment, the compensation current I _CP may be input to memory cells in a set state to which the program current I _PGM is not input in addition to the memory cells in the reset state. The compensation current I _CP input to the memory cells in the set state may remove a drift phenomenon occurring in the switch element. Accordingly, it is possible to prevent the resistance of the memory cells in the set state of the compensation current I _CP from increasing, and as a result, a sensing margin between the memory cells in the set state and the memory cells in the reset state may be increased.

The magnitude and input time of the compensation current I _CP may be variously determined. For example, the magnitude and input time of the compensation current I _CP may be similar to the magnitude and input time of the program current I _PGM , respectively. The program current I _PGM and the compensation current I _CP may be greater than the first threshold current having a magnitude capable of causing a phase change in the information storage device.

14 may be a diagram illustrating a distribution of read voltages detected by inputting a predetermined read current to memory cells. First, referring to FIG. 14A , only the set read voltage distribution 500 may appear before the program operation is executed. When the program current I _PGM is input to some of the memory cells, the reset read voltage distribution 600 may be obtained together with the set read voltage distribution 500 as shown in FIG. 14B . The set read voltage distribution 500 may have a first set distribution 501 , the reset read voltage distribution 600 may have a first reset distribution 601 , and the first set distribution 501 and the first A sensing margin SM may exist between the reset distributions 601 .

In an embodiment of the present invention, after the program current I _PGM is input, the compensation current I _CP may be input to the memory cells. As described above, the compensation current I _CP may be input only to the memory cells in the reset state, or may be input to both the memory cells in the reset state and the memory cells in the set state.

The compensation current I _CP input to the memory cells in the reset state may rapidly stabilize the information storage device of the memory cells in the reset state in the amorphous phase. Accordingly, as shown in FIG. 14(c) , the reset read voltage distribution 600 rapidly increases up to the second reset distribution 602 by the compensation current I _CP and may be stabilized.

Also, according to an embodiment of the present invention, the compensation current I _CP may be input to the memory cells in the set state after the program operation. The compensation current I _CP input to the memory cells in the set state may remove a drift phenomenon occurring in the switch element of the memory cells in the set state. Since the drift phenomenon may be a factor to increase the resistance of the memory cells, the compensation current I _CP may minimize the increase in the set read voltage distribution 500 from the first set distribution 501 .

In summary, an increase in the set read voltage distribution 500 may be minimized by the compensation current I _CP , and the reset read voltage distribution 600 may be rapidly increased and stabilized. Accordingly, as shown in FIG. 14C , the sensing margin SM may be increased, and as a result, the accuracy of the read operation of the memory device may be improved.

In various embodiments of the present disclosure, various effects may be obtained by inputting a compensation current to the memory cells before and/or after inputting the operating current to the memory cells. In an embodiment, the operating current may be a read current for reading data from the memory cells or a program current for writing data to the memory cells. The magnitude and input time of the compensation current may be variously selected in consideration of the magnitude and input time of the operating current.

A compensation current may be input to the memory cell to flow from the information storage element to the switch element in the memory cell. According to embodiments, the direction in which the compensation current flows may be the same as or different from the direction in which the operating current flows. When the operating current is the program current, the compensation current may flow in a direction opposite to the operating current. When the operating current is a read current, the operating current and the compensation current may flow in the same direction or in different directions.

For example, the compensation current input before and/or after the read current is a drift phenomenon that occurs in a memory cell having a set state, and a switch element is turned on by the read current so that a part of the information storage element is transitioned to an amorphous phase. Soft program phenomenon and the like can be compensated. Meanwhile, the compensation current supplied after the program current may contribute to securing a sensing margin by rapidly stabilizing the information storage device in the reset state memory cell.

15 is a schematic block diagram illustrating an electronic device including a memory device according to an embodiment of the present invention.

The electronic device 1000 according to the embodiment shown in FIG. 15 may include a display 1010 , an input/output unit 1020 , a memory 1030 , a processor 1040 , and a port 1050 . Components such as the display 1010 , the input/output unit 1020 , the memory 1030 , the processor 1040 , and the port 1050 may communicate with each other through the bus 1060 . In addition to the components shown above, the electronic device 1000 may further include a power supply unit, a communication unit, a sensor unit, and the like.

The processor 1040 may perform a specific operation, an instruction, a task, or the like. The processor 1040 may be a central processing unit (CPU), a microprocessor unit (MCU), an application processor (AP), or the like, and a display 1010 , an input/output unit 1020 , a memory 1030 through a bus 1060 . , port 1050, and other components.

The memory 1030 included in the electronic device 1000 illustrated in FIG. 15 may include memory devices according to various embodiments of the present disclosure. For example, the memory 1030 may be implemented as a memory device according to various embodiments described with reference to FIGS. 1 to 14 . The memory 1030 may include a plurality of memory cells, and a predetermined compensation current may be input to the memory cells before and/or after input of an operating current for executing a control operation such as read/program. The compensation current may contribute to securing a sensing margin necessary for a read operation by compensating for a drift phenomenon, a soft programming phenomenon, etc. occurring in the memory cells or by rapidly stabilizing memory cells programmed in a reset state.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Therefore, various types of substitution, modification and change will be possible by those skilled in the art within the scope not departing from the technical spirit of the present invention described in the claims, and it is also said that it falls within the scope of the present invention. something to do.

10: memory device
20: memory controller
30: memory cell array
100, 210: memory cell
220: memory controller
300, 500: set read voltage distribution
400, 600: reset read voltage distribution

Claims (20)

a memory cell array including a plurality of memory cells having a switch element and an information storage element connected to the switch element and having a phase change material; and
A control operation is performed on the memory cell by inputting an operating current into the memory cell, and a compensating current flowing from the information storage element to the switch element in the memory cell at least one before and after the input of the operating current is applied. a memory controller inputting to the memory cell; includes,
A direction in which the compensation current flows and a direction in which the operating current flows are opposite to each other.
According to claim 1,
When the control operation is a program operation, the memory controller inputs the compensation current to the memory cell after the operation current is input.
delete 3. The method of claim 2,
The memory controller is configured to input the compensation current only to the memory cell having a reset state.
The method of claim 1,
When the control operation is a read operation, the memory controller inputs the compensation current to the memory cell before or after the input of the operation current.
delete 6. The method of claim 5,
The magnitude of the compensation current is greater than the magnitude of the operating current.
6. The method of claim 5,
The memory controller is configured to input the compensation current only to the memory cell having a set state.
a memory cell array including a plurality of memory cells each having a first electrode, a switch element connected to the first electrode, an information storage element connected to the switch element, and a second electrode connected to the information storage element; and
a memory controller configured to input a read current to the first electrode of the memory cell to read data stored in the memory cell, and to input a compensation current to the second electrode before and after the input of the read current; includes,
The read current is input to the first electrode and flows from the switch element to the information storage element, and the compensation current is input to the second electrode and flows from the information storage element to the switch element.
a memory cell array including a plurality of memory cells each having a first electrode, a switch element connected to the first electrode, an information storage element connected to the switch element, and a second electrode connected to the information storage element; and
a memory controller that inputs a program current to the first electrode of the memory cell, stores data in the memory cell, and inputs a compensation current to the second electrode after the input of the program current; includes,
The program current is input to the first electrode and flows from the switch element to the information storage element, and the compensation current is input to the second electrode and flows from the information storage element to the switch element.
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