KR102362743B1 - Communication method and display device using the same - Google Patents

Abstract

The present invention relates to a communication method capable of reducing manufacturing cost and a display device using the same. A display device according to an embodiment of the present invention includes a control board including a timing controller and a first connector, a system board including a system on chip and a second connector, and a first connector of the control board and a second connector of the system board and a first cable connected to The system-on-chip transmits any one of video data and PC data to the timing controller to the first interface through some lanes of the first cable.

Description

COMMUNICATION METHOD AND DISPLAY DEVICE USING THE SAME

The present invention relates to a communication method and a display device using the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have recently been used. Among them, the organic light emitting display device can be driven at a low voltage, is thin, has an excellent viewing angle, and has a fast response speed.

An organic light emitting display device includes a display panel including data lines, scan lines, pixels formed at intersections of data lines and scan lines, a scan driver supplying scan signals to the scan lines, and applying data voltages to the data lines. It includes a data driver that supplies the data driver, a timing controller that controls operation timings of the scan driver and the data driver, and a power supply that supplies driving voltages to pixels, the scan driver, the data driver, and the timing controller. Each of the pixels includes an organic light emitting diode, a driving transistor that adjusts the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, and data on the data line in response to the scan signal of the scan line. A scan transistor for supplying a voltage to the gate electrode of the driving transistor, and a storage capacitor for maintaining the voltage of the gate electrode of the driving transistor for a predetermined period.

The threshold voltage of the driving transistor may vary for each pixel due to a process deviation during manufacturing of the organic light emitting diode display or deterioration of the driving transistor due to long-term driving. That is, when the same data voltage is applied to the pixels, the current supplied to the organic light emitting diode must be the same. However, even when the same data voltage is applied to the pixels due to the difference in threshold voltage of the driving transistor between the pixels, the The supplied current may vary for each pixel. In addition, the organic light emitting diode may also be deteriorated due to long-term driving, and in this case, the luminance of the organic light emitting diode may vary for each pixel. Accordingly, even when the same data voltage is applied to the pixels, the luminance emitted by the organic light emitting diode may be different for each pixel. To solve this problem, a compensation method for compensating for a threshold voltage and electron mobility of a driving transistor has been proposed.

The threshold voltage and electron mobility of the driving transistor may be compensated by an external compensation method. In the external compensation method, a preset data voltage is supplied to the pixel, the source voltage of the driving transistor is sensed through a predetermined sensing line according to the preset data voltage, and the sensed voltage is obtained using an analog digital converter. A method of converting digital data into sensing data, calculating compensation data based on the sensing data, and compensating digital image data to be supplied to pixels according to the compensation data.

In the case of compensating for the threshold voltage and electron mobility of the driving transistor by an external compensation method, the timing controller of the organic light emitting diode display is controlled using a computer before shipment to calculate compensation data, and the compensation data is stored in the memory of the organic light emitting display device. save to Specifically, the organic light emitting display device and the computer are connected through the interface board. Then, a timing controller of the organic light emitting display device is controlled using a computer to transmit sensing data of the organic light emitting display device to the computer. Then, the compensation data calculated from the computer is transmitted to the organic light emitting display device and stored in the memory of the control board. The control board is a circuit board on which the timing controller and memory are mounted.

The interface board is connected to the computer and the control board of the organic light emitting display device to control the organic light emitting display device using a computer. Since the control board is connected to the interface board through a cable, the control board must have a connector to connect to the cable. However, since the interface board is used to connect the computer and the organic light emitting diode display to store compensation data in the memory of the organic light emitting diode display before product shipment, there is no need for a connector on the control board to communicate with the interface board after product shipment. . Accordingly, when the connector of the control board for communicating with the interface board is deleted, the manufacturing cost can be reduced.

An object of the present invention is to provide a communication method capable of reducing manufacturing cost and a display device using the same.

A communication method according to an embodiment of the present invention includes transmitting any one of video data and PC data to a first interface from a system board to a display module through a cable, and displaying an image according to the video data when video data is input controlling the display module in the display mode to do so, controlling the display module in the first PC communication mode to calculate sensed data when PC data is input, and transferring the sensed data from the display module to the system board through a cable sending to the interface.

A display device according to an embodiment of the present invention includes a control board including a timing controller and a first connector, a system board including a system on chip and a second connector, and a first connector of the control board and a second connector of the system board and a first cable connected to The system-on-chip transmits any one of video data and PC data to the timing controller to the first interface through some lanes of the first cable.

An embodiment of the present invention may transmit video data from the SoC to the timing controller using the first cables, as well as transmit sensing data from the timing controller to the interface board. That is, in the embodiment of the present invention, video data is transmitted from the SoC to the timing controller through the first cables, and sensing data can be transmitted from the timing controller to the interface board using the remaining lanes. As a result, in the embodiment of the present invention, the control board is not directly connected to the interface board, but may be connected to and communicate with the interface board through the system board. Accordingly, in the embodiment of the present invention, since the connector for connecting to the interface board can be deleted from the control board, the manufacturing cost can be reduced.

1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a block diagram schematically illustrating an interface board, a system board, and a control board of FIG. 1 .
3 is a flowchart illustrating a communication method according to an embodiment of the present invention.
4 is a perspective view illustrating a display device according to an exemplary embodiment.
5 is a block diagram schematically illustrating the display module of FIG. 4 .
6 is a circuit diagram of the pixel of FIG. 5 .

Like reference numerals refer to substantially identical elements throughout. In the following description, a detailed description of configurations and functions known in the art and cases not related to the core configuration of the present invention may be omitted. The meaning of the terms described in this specification should be understood as follows.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than within the scope where the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of “at least one of the first, second, and third items” means that each of the first, second, or third items as well as two of the first, second and third items It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention can be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention.

Referring to FIG. 1 , a display device according to an exemplary embodiment includes a display module 100 , a system board 200 , and an interface board 300 . As shown in FIG. 2 , the display module 100 and the system board 200 may be connected through a first cable 400 , and the system board 200 and the interface board 300 may be connected through a second cable 500 . .

In the embodiment of the present invention, the description has been focused on that the display module 100 is an organic light emitting display (OLED). The display module 100 may include a display panel 110 , a display panel driver 120 , and a timing controller 130 .

The display panel 110 includes data lines, scan lines, and pixels formed at intersections of the data lines and the scan lines. Each of the pixels receives the data voltage DV from the data line when the gate signal GS is applied from the scan line, and emits light with a predetermined brightness according to the data voltage. Accordingly, the display panel 100 may display an image using pixels.

The display panel driver 120 receives the video data DATA or the first PC data PCD1 , the scan control signal GCS, and the data control signal DCS from the timing controller 130 . The display panel driver 120 generates driving signals for driving the display panel 100 according to the scan control signal GCS and the data control signal DCS, and supplies the driving signals to the display panel 100 . That is, the display panel driver 120 generates the scan signals GS according to the scan control signal GCS and supplies them to the scan lines of the display panel 100 , and the video data DATA or the first PC data PCD1 . ) to generate data voltages DV and supply them to data lines of the display panel 100 .

Also, the display panel driver 120 may sense the source voltages of the driving transistors of the pixels of the display panel 100 through the reference voltage line, that is, the sensing voltages SV. The display panel driver 120 converts the sensing voltages SV into sensing data SD, which is digital video data, and transmits it to the timing controller 130 .

The timing controller 130 receives video data DATA and first PC data PCD1 from a system on chip (hereinafter, referred to as “SoC”, 210 ) of the system board 200 through the first cables 400 . ) or the second PC data PCD2 and timing signals. The timing signals may include a vertical sync signal, a horizontal sync signal, and a data enable signal.

The timing controller 130 controls the display module 100 in the display mode when the video data DATA is input, and sets the display module 100 to the first PC communication mode when the first PC data PCD1 is input. control, and when the second PC data PCD2 is input, the second PC communication mode is controlled. In the first PC communication mode and the second PC communication mode, when the threshold voltage and electron mobility of the driving transistor are compensated by an external compensation method, compensation data is calculated by controlling the timing controller of the organic light emitting display device with a computer before shipment of the product. , are modes for storing compensation data in the memory of the organic light emitting diode display.

The timing controller 130 generates a scan control signal GCS and a data control signal DCS based on the timing signals in the display mode, and uses compensation data stored in an electrically erasable programmable read-only memory. to externally compensate the video data DATA. The timing controller 130 supplies the compensated video data DATA, the scan control signal GCS, and the data control signal DCS to the display panel driver 120 .

The timing controller 130 generates a scan control signal GCS and a data control signal DCS based on the timing signals in the first PC communication mode, the first PC data PCD1, the scan control signal GCS, and The data control signal DCS is supplied to the display panel driver 120 . The timing controller 130 receives the sensed data SD sensed according to the first PC data PCD1 from the display panel driver 120 in the first PC communication mode. The timing controller 130 transmits the sensing data SD to the system board 200 through a low voltage differential signal (LVDS) interface.

The timing controller 130 stores the second PC data PCD2 as compensation data in the nonvolatile memory in the second PC communication mode.

The system board 200 includes an SoC 210 .

The SoC 210 receives the video data DATA from the outside or receives the first PC data PCD1 or the second PC data PCD2 through the interface board 300 . The SoC 210 may convert the video data DATA to a resolution suitable for display by the display module 100 by including a scaler. When the video data DATA is input, the SoC 210 outputs the video data DATA and timing signals to the timing controller 230 . When the first PC data PCD1 or the second PC data PCD2 is input, the SoC 210 outputs the first PC data PCD1 or the second PC data PCD2 to the timing controller 230 . The SoC 210 may communicate with the timing controller 230 through a V-by-one (hereinafter, referred to as “Vx1”) interface.

Since the Vx1 interface is a high-speed serial interface that does not require fixed frequency clock transmission, EMI noise can be reduced compared to the LVDS interface that requires fixed frequency clock transmission. In addition, the Vx1 interface can transmit data at a higher speed than the LVDS interface. That is, in the embodiment of the present invention, the communication interface between the SoC 210 and the timing controller 130 that needs to transmit a larger amount of data is communicated between the timing controller 130 and the transmission/reception module 310 of the interface board 300 . It can be applied as a higher-speed interface than the interface. As a result, the embodiment of the present invention can transmit video data DATA from the SoC 210 to the timing controller 130 using the first cables 400 as well as from the timing controller 130 to the interface board ( 300) to transmit the sensing data SD.

As described above, in the embodiment of the present invention, video data DATA is transmitted from the SoC 210 to the timing controller 130 in the first cables 400 in the first PC communication mode, and the remaining lanes are used to The sensing data SD may be transmitted from the timing controller 130 to the interface board 300 . That is, according to the embodiment of the present invention, lanes for transmitting video data DATA from the SoC 210 to the timing controller 130 through the first cables 400 and the interface board 300 from the timing controller 130 . ), the lanes for transmitting the sensing data SD are different.

Meanwhile, in the display mode, lanes other than some lanes for transmitting video data DATA from the SoC 210 to the timing controller 130 in the first cables 400 are not used as transmission lanes. That is, in the display mode, the remaining lanes may be dummy lanes.

The interface board 300 includes a transceiver module 310 . The transceiver module 310 may transmit the first PC data PCD1 or the second PC data PCD2 transmitted through the Ethernet interface to the SoC 210 of the system board 200 through the LVDS interface. In addition, the transceiver module 310 may transmit the sensing data SD transmitted through the LVDS interface to the computer through the Ethernet interface.

FIG. 2 is a block diagram schematically illustrating an interface board, a system board, and a control board of a display module of FIG. 1 .

Referring to FIG. 2 , the system board 200 is connected to an external graphic source device through the third connector 430 or the interface board 300 through the fourth connector 510 connected to the second cable 500 . can be connected to That is, the system board 200 may be connected to only one of an external graphic source device or an interface board. 2 illustrates that the system board 200 is connected to the interface board 300 through the fourth connector 510 connected to the second cable 500 for convenience of explanation.

The control board 160 may include a timing controller 130 and first connectors 410 . The timing controller 130 may include a video data receiver 131 , a PC data receiver 132 , a demultiplexer 133 , and a sensing data transmitter 134 as shown in FIG. 2 . Each of the first connectors 410 may be connected to each of the first cables 400 . 2 illustrates that a plurality of first cables 400 are provided, but the present invention is not limited thereto.

The video data receiving unit 131 may be a Vx1 receiving circuit that restores video data DATA from a Vx1 transport packet input from the demultiplexer 133 . When video data DATA is input to the video data receiver 131 , the timing controller 130 controls the display module 100 to be in a display mode.

The PC data receiving unit 132 may be a Vx1 receiving circuit that restores the first PC data PCD1 or the second PC data PCD2 from the Vx1 transport packet input from the demultiplexer 133 . When the first PC data PCD1 is input to the PC data receiver 132 , the timing controller 130 controls the display module 100 to the first PC communication mode. Also, when the second PC data PCD2 is input to the PC data receiver 132 , the timing controller 130 controls the display module 100 to the second PC communication mode.

The demultiplexer 133 selects the Vx1 transport packet transmitted from the SoC 210 of the system board 200 through the first cables 400 according to the selection signal SEL to the video data receiver 131 and the PC data receiver 132 . output one of For example, the demultiplexer 133 outputs a Vx1 transport packet to the video data receiver 131 when the selection signal SEL of the first logic voltage is input, and the selection signal SEL of the second logic voltage is input. In this case, the Vx1 transport packet is output to the PC data receiving unit 132 . In this case, the first logic voltage may be a low level voltage of 0V, and the second logic voltage may be a high level voltage of 3.3V.

The sensing data transmitter 134 transmits the sensing data SD to the system board 200 through the first cable 400 . The sensing data transmitter 134 may transmit the sensing data SD through the LVDS interface. In this case, the sensing data transmitter 134 may convert the sensing data SD into a low voltage differential signal and transmit it to the system board 200 .

The system board 200 may include an SoC 210 , second connectors 420 , a third connector 430 , and a fourth connector 510 . The SoC 210 may include a video data transmitter 211 , a PC data transmitter 212 , a multiplexer 213 , and a selection signal generator 214 . Each of the second connectors 420 may be connected to each of the first cables 400 . The third connector 430 may be connected to an external graphic source device, for example, a set top box, a graphic card of a computer, or the like through a cable. For example, the third connector 430 may be a High-Definition Multimedia Interface (HDMI) port. The HDMI interface supports HDCP (High-bandwidth Digital Contents Protection) technology to prevent content copying. The fourth connector 510 may be connected to the second cable 500 .

The video data transmitter 211 restores the video data DATA from the HDMI transport packet transmitted from the third connector 430 . In this case, the video data transmitter 211 restores video data DATA encrypted with HDCP. The video data transmitter 211 converts the restored video data DATA into a Vx1 transport packet and outputs it to the multiplexer 213 . That is, the video data transmitter 211 may be an HDMI-to-Vx1 conversion circuit that outputs video data DATA input through the HDMI interface to the Vx1 interface.

The PC data transmitter 212 converts the low voltage differential signal transmitted from the transceiver module 310 of the interface board 300 through the second cable 500 into the first PC data PCD1 or the second PC data PCD2. do. The PC data transmitter 212 converts the first PC data PCD1 or the second PC data PCD2 into a Vx1 transport packet and outputs the converted packet to the multiplexer 213 . That is, the video data transmitter 211 may be an LVDS-to-Vx1 conversion circuit that outputs the first PC data PCD1 or the second PC data PCD2 input through the LVDS interface to the Vx1 interface.

The multiplexer 213 transmits any one of the Vx1 transport packet of the video data transmitter 211 and the Vx1 transport packet of the PC data transmitter 212 according to the selection signal SEL input from the selection signal generator 214 to the first cable. It is output to the timing controller 130 of the control board 160 through 400 . For example, when the selection signal SEL of the first logic voltage is input, the multiplexer 213 outputs the Vx1 transport packet of the video data transmitter 211, and the selection signal SEL of the second logic voltage is input. In this case, the Vx1 transport packet of the PC data transmitter 212 is output to the PC data receiver 132 .

The selection signal generator 214 generates and outputs the selection signal SEL according to the PC transmission signal PSS transmitted from the transmission/reception module 310 of the interface board 300 through the second cable 500 . The PC transmission signal PSS indicates whether the first PC data PCD1 or the second PC data PCD2 is transmitted by the transmission/reception module 310 of the interface board 300 . For example, the transmission/reception module 310 of the interface board 300 transmits the first PC data PCD1 or the second PC data PCD2 to the SoC 210 of the system board 200 through the second cable 500 . In the case of transmitting , the PC transmission signal PSS may be generated as the second logic voltage, and otherwise, the PC transmission signal PSS may be generated as the first logic voltage. The selection signal generator 214 transmits the selection signal SEL of the first logic voltage to the multiplexer 213 when the PC transmission signal PSS of the first logic voltage is transmitted, and the PC transmission signal of the second logic voltage When PSS is transmitted, the selection signal SEL of the second logic voltage may be transmitted to the multiplexer 213 .

The interface board 300 includes a transceiver module 310 , a fifth connector 520 , and a sixth connector 530 . The fifth connector 520 may be connected to the second cable 500 . The sixth connector 530 may be connected to a computer through a cable. For example, the sixth connector 530 may be an Ethernet port.

The transmission/reception module 310 converts the Ethernet transmission packet transmitted from the sixth connector 530 into the first PC data PCD1 or the second PC data PCD2. The transceiver module 310 converts the first PC data PCD1 or the second PC data PCD2 into a low voltage differential signal and transmits the converted signal to the multiplexer 213 . That is, the transmission/reception module 310 may be an Ethernet-to-LVDS conversion circuit that transmits the first PC data PCD1 or the second PC data PCD2 transmitted through the Ethernet interface to the LVDS interface.

In addition, the transceiver module 310 converts the low voltage differential signal transmitted from the system board 200 through the second cable 500 into sensing data SD. The transmission/reception module 310 converts the sensed data SD into an Ethernet transport packet and transmits it to the sixth connector 530 .

As described above, in the embodiment of the present invention, not only video data DATA can be transmitted from the SoC 210 to the timing controller 130 using the first cables 400 , but also from the timing controller 130 . The sensing data SD may be transmitted to the interface board 300 . That is, in the embodiment of the present invention, video data DATA is transmitted from the SoC 210 to the timing controller 130 through the first cables 400 and the remaining lanes are used to transfer the video data from the timing controller 130 to the interface board 300 . ) to transmit the sensing data SD. As a result, in the embodiment of the present invention, the control board 160 is not directly connected to the interface board 300 , but may be connected to and communicate with the interface board 300 through the system board 200 . Accordingly, in the embodiment of the present invention, since the connector for connecting to the interface board 300 from the control board 160 can be deleted, manufacturing cost can be reduced.

3 is a flowchart illustrating a communication method according to an embodiment of the present invention.

Hereinafter, a communication method according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3 .

First, any one of the video data DATA, the first PC data PCD1 , and the second PC data PCD2 is transmitted from the system board 200 to the display module 100 .

Specifically, the system board 200 may be connected to an external graphic source device through the third connector 430 or connected to the interface board 300 through the fourth connector 510 connected to the second cable 500 . have. That is, the system board 200 may be connected to only one of an external graphic source device or an interface board. 2 illustrates that the system board 200 is connected to the interface board 300 through the fourth connector 510 connected to the second cable 500 for convenience of explanation.

When the system board 200 is connected to an external graphic source device through the third connector 430 to receive video data DATA, the video data transmitter 211 of the SoC 210 is connected to the third connector 430 . Video data DATA is restored from the HDMI transport packet transmitted from , and the restored video data DATA is converted into a Vx1 transport packet and output to the multiplexer 213 . Since the synchronization signal generator 214 of the SoC 210 does not receive the PC transmission signal PSS when it is not connected to the interface board 300 , it generates and outputs the selection signal SEL of the first logic voltage. . The multiplexer 213 transmits the Vx1 transport packet of the video data transmitter 211 to the timing controller 130 of the control board 160 through the first cables 400 when the selection signal SEL of the first logic voltage is input. send.

When the system board 200 is connected to the interface board 300 through the fourth connector 510 connected to the second cable 500 to receive video data DATA, the PC data transmitter ( 212 converts the low voltage differential signal transmitted from the transceiver module 310 of the interface board 300 through the second cable 500 into the first PC data PCD1 or the second PC data PCD2, and The PC data PCD1 or the second PC data PCD2 is converted into a Vx1 transport packet and output to the multiplexer 213 . When connected to the interface board 300 , the synchronization signal generator 214 of the SoC 210 receives the PC transmission signal PSS of the second logic voltage, and thus generates a selection signal SEL of the second logic voltage. print out The multiplexer 213 transmits the Vx1 transmission packet of the PC data transmitter 212 to the timing controller 130 of the control board 160 through the first cables 400 when the selection signal SEL of the second logic voltage is input. send. (S101 in FIG. 3)

Second, when the video data DATA is transmitted, the timing controller 130 controls the display module 100 to display an image according to the video data DATA in the display mode.

Specifically, the demultiplexer 133 of the timing controller 130 is Vx1 transmitted from the Soc 210 of the system board 200 through the first cables 400 when the selection signal SEL of the first logic voltage is input. The transport packet is output to the video data receiver 131 . The video data receiver 131 restores the video data DATA from the Vx1 transport packet input from the demultiplexer 133 . When video data DATA is input to the video data receiver 131 , the timing controller 130 controls the display module 100 to be in a display mode. The timing controller 130 generates a scan control signal GCS and a data control signal DCS based on timing signals transmitted together with the video data DATA from the system board 200 in the display mode, and a non-volatile memory Video data DATA is externally compensated using compensation data stored in an electrically erasable programmable read-only memory. The timing controller 130 supplies the compensated video data DATA, the scan control signal GCS, and the data control signal DCS to the display panel driver 120 . (S102 in FIG. 3)

Third, when the first PC data PCD1 is transmitted, the timing controller 130 controls the display module 100 to the first PC communication mode to calculate the sensed data SD, and transmits the sensed data SD. It is transmitted from the display module 100 to the system board 200 .

The demultiplexer 133 of the timing controller 130 receives the Vx1 transmission packet transmitted from the Soc 210 of the system board 200 through the first cables 400 when the selection signal SEL of the second logic voltage is input. It is output to the PC data receiving unit 132 . The PC data receiver 132 restores the first PC data PCD1 from the Vx1 transport packet input from the demultiplexer 133 .

When the first PC data PCD1 is input to the PC data receiver 132 , the timing controller 130 controls the display module 100 to the first PC communication mode. The timing controller 130 generates a scan control signal GCS and a data control signal DCS based on the timing signals in the first PC communication mode, the first PC data PCD1, the scan control signal GCS, and The data control signal DCS is supplied to the display panel driver 120 . The timing controller 130 receives the sensed data SD sensed according to the first PC data PCD1 from the display panel driver 120 in the first PC communication mode.

The sensing data transmitter 134 of the timing controller 130 transmits the sensing data SD to the system board 200 through the first cable 400 . Since the sensing data transmitter 134 communicates with the LVDS interface, the sensing data SD may be converted into a low voltage differential signal and transmitted to the system board 200 . In this case, the sensing data SD may be transmitted to the transmission/reception module 310 of the interface board 300 connected through the system board 200 and the second cable 500 . The transmission/reception module 310 of the interface board 300 converts the sensing data SD transmitted as the low-voltage differential signal into an Ethernet transmission packet and transmits it to the sixth connector 530 . (S103 in FIG. 3)

Fourth, when the second PC data PCD2 is transmitted, the timing controller 130 controls the display module 100 to store the second PC data PCD2 in the memory in the second PC communication mode.

Specifically, the demultiplexer 133 of the timing controller 130 is Vx1 transmitted from the Soc 210 of the system board 200 through the first cables 400 when the selection signal SEL of the second logic voltage is input. The transport packet is output to the PC data receiving unit 132 . The PC data receiver 132 restores the second PC data PCD2 from the Vx1 transport packet input from the demultiplexer 133 . The timing controller 130 stores the second PC data PCD2 as compensation data in the memory in the second PC communication mode. (S104 in Fig. 3)

4 is a perspective view illustrating a display device according to an exemplary embodiment.

Referring to FIG. 4 , a display device according to an embodiment of the present invention includes a display module 100 , a system board 200 , an interface board 300 , a first cable 400 , and a second cable 500 . include

As shown in FIG. 4 , the display module 100 includes a display panel 110 , source drive ICs 121 corresponding to the display panel driver 120 , flexible films 122 , a timing controller 130 , and a source circuit board ( 140 ), a flexible cable 150 , and a control board 160 may be included.

The display panel 110 may include a lower substrate 111 and an upper substrate 112 . The lower substrate 111 may be formed of glass or plastic, and the upper substrate 112 may be formed of a plastic film, an encapsulation film, or a barrier film.

The display panel driver 120 may include a gate driver and source drive ICs 121 corresponding to the data driver. Each of the source drive ICs 121 may be adhered to the flexible film 122 . Each of the flexible films 122 may be attached to the lower substrate 111 and the source circuit board 140 of the display panel 110 .

The source circuit boards 140 may be connected to the control board 160 through the flexible cable 150 . Connectors 151 may be provided on each of the source circuit boards 140 and the control board 160 to be connected through the flexible cable 150 .

A timing controller 130 , connectors 151 , first connectors 410 , and a power supply unit may be mounted on the control board 160 . The timing controller 130 and the power supply may be implemented as an integrated circuit. The power supply unit generates driving voltages for driving the timing controller 130 and the source drive ICs 121 , and generates high and low potential voltages for driving the organic light emitting diodes of the pixels of the display panel 110 . can

The system board 200 may include an SoC 210 , second connectors 420 , a third connector 430 , and a fourth connector 510 as shown in FIG. 4 , and the interface board 300 transmits and receives It may include a module 310 , a fifth connector 520 , and a sixth connector 530 . The SoC 210 and the transceiver module 310 may be implemented as an integrated circuit.

Each of the first cables 400 connects the first connector 410 of the control board 160 and the second connector 420 of the system board 200 . 4 illustrates that a plurality of first cables 400 are provided, but the present invention is not limited thereto. The second cable 500 connects the fourth connector 510 of the system board 200 and the fifth connector 520 of the interface board 300 .

5 is a block diagram schematically illustrating the display module of FIG. 4 .

Hereinafter, configurations of the display module will be described in detail with reference to FIG. 5 . In the embodiment of the present invention, the description has been focused on that the display module 100 is an organic light emitting display (OLED).

Referring to FIG. 5 , the display panel 110 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area in which pixels P are formed to display an image. The display panel 110 includes data lines (D1 to Dm, m is a positive integer greater than or equal to 2), reference voltage lines (R1 to Rp, p is a positive integer greater than or equal to 2), and scan lines (S1 to Sn, n). is a positive integer greater than or equal to 2), and sensing signal lines SE1 to SEn are provided. The data lines D1 to Dm and the reference voltage lines R1 to Rp may cross the scan lines S1 to Sn and the sensing signal lines SE1 to SEn. The data lines D1 to Dm and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn and the sensing signal lines SE1 to SEn may be parallel to each other.

Each of the pixels P includes any one of the data lines D1 to Dm, any one of the reference voltage lines R1 to Rp, any one of the scan lines S1 to Sn, and the sensing signal lines ( SE1 to SEn) may be connected to any one of. Each of the pixels P of the display panel 110 may include an organic light emitting diode (OLED) and a plurality of transistors for supplying current to the organic light emitting diode (OLED) as shown in FIG. 14 . A detailed description of each of the pixels P of the display area will be described later with reference to FIG. 14 .

The display panel driver 120 may include a gate driver 170 and a data driver 121D as shown in FIG. 14 .

The data driver 121D may include a plurality of source drive ICs 121 as shown in FIG. 14 . Each of the source drive ICs 121 may include a data voltage supply unit and a sensing unit.

The data voltage supply unit is connected to the data lines to supply data voltages. The data voltage supply unit receives digital video data DATA and a data control signal DCS from the timing controller 130 . The data voltage supply unit converts the digital video data DATA into data voltages according to the data control signal DCS and supplies the data voltages to the data lines.

The sensing unit supplies a reference voltage to the reference voltage lines R1 to Rz, senses the source voltages of the driving transistors of the pixels P through the reference voltage lines R1 to Rz, and converts the sensed voltages into digital data. It is converted into sensed data and output to the timing controller 130 .

The scan driver 170 includes a scan signal output unit 171 and a sensing signal output unit 172 .

The scan signal output unit 171 supplies scan signals to the scan lines S1 to Sn according to the scan control signal GCS input from the timing controller 170 . The sensing signal output unit 172 supplies sensing signals to the sensing signal lines SE1 to SEn according to the scan control signal GCS input from the timing controller 170 .

The scan signal output unit 171 and the sensing signal output unit 172 may include a plurality of transistors and may be directly formed in the non-display area NDA of the display panel 110 in a gate driver in panel (GIP) method. Alternatively, the scan signal output unit 171 and the sensing signal output unit 172 may be formed in the form of a driving chip and mounted on a flexible film (not shown) connected to the display panel 110 .

The timing controller 130 receives the video data DATA, the first PC data PCD1 or the second PC data PCD2 from the system board 200 . Also, the timing controller 130 may receive timing signals together. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 130 controls the display module 100 in the display mode when the video data DATA is transmitted, and sets the display module 100 to the first PC communication mode when the first PC data PCD1 is transmitted. and controls the display module 100 in the second PC communication mode when the second PC data PCD2 is transmitted. The display mode is a mode in which an image is displayed by supplying data voltages according to the video data DATA to the pixels P. In the first PC communication mode, data voltages according to the first PC data PCD1 are supplied to the pixels P, and source voltages of driving transistors of the pixels P are sensed through the reference voltage lines R1 to Rp. is the mode to The second PC communication mode is a mode for storing the second PC data PCD2 as compensation data in a memory mounted on the control board 160 .

The timing controller 130 compensates the video data DATA according to the compensation data stored in the memory in the display mode, and generates the data control signal DCS and the scan control signal GCS according to the timing signals. The timing controller 130 outputs the data control signal DCS and the video data DATA to the data driver 121D in the display mode, and outputs the scan control signal GCS to the scan driver 170 .

The timing controller 130 generates the data control signal DCS and the scan control signal GCS according to the timing signals in the first PC communication mode, and transmits the first PC data PCD1 and the data control signal DCS to the data. It outputs to the driver 121D and outputs the scan control signal GCS to the scan driver 170 .

The timing controller 130 stores the second PC data PCD2 in a memory mounted on the control board 160 in the second PC communication mode.

6 is a circuit diagram of the pixel of FIG. 5 .

Referring to FIG. 6 , the pixel P may include an organic light emitting diode OLED, a driving transistor DT, first and second switching transistors ST1 and ST2 , and a storage capacitor Cst.

The organic light emitting diode OLED emits light according to a current supplied through the driving transistor DT. An organic light emitting diode (OLED) may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In an organic light emitting diode (OLED), when a voltage is applied to an anode electrode and a cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light. An anode electrode of the organic light emitting diode OLED may be connected to a source electrode of the driving transistor DT, and a cathode electrode may be connected to a second power supply line VSL to which a second power lower than the first power is supplied.

The driving transistor DT adjusts a current flowing from the first power line EVL to the organic light emitting diode OLED according to a voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first switching transistor ST1 , the source electrode is connected to the anode electrode of the organic light emitting diode OLED, and the drain electrode is connected to the first power line EVL can be connected to

The first switching transistor ST1 is turned on by the k-th scan signal of the k-th scan line Sk to connect the j-th data line Dj to the gate electrode of the driving transistor DT. The gate electrode of the first switching transistor T1 is connected to the k-th scan line Sk, the first electrode is connected to the gate electrode of the first driving transistor DT1, and the second electrode is connected to the j-th data line Dj. ) can be connected to

The second switching transistor ST2 is turned on by the k-th sensing signal of the k-th sensing signal line SEk to connect the u-th reference voltage line Ru to the source electrode of the driving transistor DT. The gate electrode of the second switching transistor ST3 is connected to the k-th sensing signal line SEk, the first electrode is connected to the u-th reference voltage line Ru, and the second electrode is the source of the driving transistor DT. can be connected to the electrode.

The first electrode of each of the first and second switching transistors ST1 and ST2 may be a source electrode and the second electrode may be a drain electrode, but it should be noted that the present invention is not limited thereto. That is, the first electrode of each of the first and second switching transistors ST1 and ST2 may be a drain electrode, and the second electrode may be a source electrode.

The storage capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The storage capacitor Cst stores a difference voltage between the gate voltage and the source voltage of the driving transistor DT.

The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of thin film transistors. In addition, in FIG. 4 , the driving transistor DT and the first and second switching transistors ST1 and ST2 have been mainly described as being formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it should be noted that the present invention is not limited thereto. shall. The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of a P-type MOSFET.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display module 110: display panel
120: display panel driver 121D: data driver
121: source drive IC 122: flexible film
130: timing controller 140: source circuit board
150: flexible cable 160: control board
170: scan driver 171: scan signal output unit
172: sensing signal output unit 200: system board
210: system on chip (SoC) 300: interface board
310: transmit/receive module 400: first cable
500: second cable

Claims (15)

transmitting any one of video data and PC data from the system board to the display module to the first interface through the first cable;
controlling the display module in a display mode to display an image according to the video data when the video data is input;
controlling the display module in a first PC communication mode to calculate sensing data when the PC data is input; and
Transmitting the sensing data from the display module to the system board through the first cable to a second interface,
Transmitting any one of the video data and the PC data from the system board to the display module to the first interface through the first cable,
A communication method for transmitting any one of the video data and the PC data to the first interface through some lanes of the first cable. delete The method of claim 1,
Transmitting the sensing data to the second interface from the display module to the system board through the first cable,
A communication method for transmitting the sensed data to the second interface through some other lanes of the first cable. The method of claim 1,
The transmission rate of the first interface is higher than the transmission rate of the second interface. The method of claim 1,
transmitting the PC data from the interface board to the system board to the second interface; and
The method further comprising transmitting the sensed data from the system board to the interface board to the second interface. 6. The method of claim 5,
transmitting the PC data from the computer to the interface board through a third interface; and
The communication method further comprising the step of transmitting the sensed data from the interface board to the computer to the third interface. a control board including a timing controller and a first connector;
a system board including a system on chip and a second connector; and
a first cable connected to the first connector of the control board and the second connector of the system board;
The system-on-chip transmits any one of video data and PC data to the timing controller to the first interface through some lanes of the first cable,
wherein the timing controller transmits sensing data to the system board through the remaining lanes of the first cable to a second interface in a first PC communication mode. 8. The method of claim 7,
In the display mode, the remaining lanes of the first cable are dummy lanes. delete 8. The method of claim 7,
a transmission rate of the first interface is higher than a transmission rate of the second interface. 8. The method of claim 7,
The system board further includes a third connector and a fourth connector. 12. The method of claim 11,
an interface board including a transceiver module and a fifth connector; and
a second cable connected to the fourth connector of the system board and the fifth connector of the interface board;
In the first PC communication mode, the transceiver module receives the sensing data from the system board to the second interface through the second cable. 13. The method of claim 12,
In the first PC communication mode, the transceiver module transmits the PC data to the system-on-chip through the second cable to the second interface. 13. The method of claim 12,
The interface board further includes a sixth connector. 15. The method of claim 14,
a third cable connected to the fifth connector of the interface board and a computer;
In the first PC communication mode, the transceiver module transmits the sensed data to the computer through the third cable through a third interface.

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