KR102360856B1 - Ceramic substrate and led package having the same - Google Patents

Abstract

A ceramic substrate and an LED package including the same by connecting the upper electrode and the lower electrode respectively formed on the upper and lower surfaces of the ceramic substrate to a plurality of via holes and filling the inside of the via hole with a thermal conductive material to improve the heat dissipation characteristics of the ceramic substrate present The presented ceramic substrate includes a base substrate made of a ceramic material in which a plurality of via holes are formed, first and second upper electrodes formed to be spaced apart from each other on an upper surface of the base substrate, a first lower electrode and a second upper electrode formed to be spaced apart from each other on the lower surface of the base substrate. 2 lower electrodes, wherein the plurality of via holes are formed in a first overlapping area where the first upper electrode and the first lower electrode overlap and a second overlapping area where the second upper electrode and the second lower electrode overlap, each A plurality of via holes are formed in the overlapping region.

Description

Ceramic substrate and LED package including same

The present invention relates to a ceramic substrate and an LED package including the same, and more particularly, to a ceramic substrate for connecting an LED element disposed on the upper portion to a male circuit board disposed on the lower portion, and an LED package including the same.

For LED packages used in lighting, automobiles, and smartphone flashes, ceramic substrates with excellent thermal conductivity and heat resistance are mainly used in order to prevent heat dissipation problems during packaging due to the characteristics of LED elements that generate a lot of heat and consequent deterioration in reliability.

For example, the ceramic substrate can be divided into a DBC (Direct Bonding Copper) ceramic substrate, DPC (Direct Plated Copper) ceramic substrate, LTCC (Low Temperature Co-fired Ceramic) substrate, HTCC (High Temperature Co-fired Ceramic) substrate, etc. depending on the manufacturing process. are classified

In a conventional ceramic substrate for LED packages, metal electrodes are formed on the upper and lower surfaces of a base substrate (ie, ceramic), which are insulators, respectively, and via holes (through holes) filled with a conductive material are formed in the base substrate on the upper and lower surfaces. It is formed in a structure for connecting the formed metal electrodes.

LED package manufacturers are researching the miniaturization of LED packages to reduce costs. As the LED package is miniaturized, the heat density of the LED device is relatively increased, so the reliability of the product can be maintained only when the heat dissipation characteristic of the ceramic substrate is improved.

As a method for improving the heat dissipation characteristics of the ceramic substrate, there is a method of reducing the thickness of the base substrate (ie, the ceramic substrate). That is, it is a method of improving the heat dissipation characteristics of the ceramic substrate by reducing the thickness of the base substrate to minimize the thermal resistance of the ceramic substrate.

However, if the thickness of the base substrate is reduced by a certain level or more, the mechanical strength of the product is lowered, so there is a problem in that defects and damage occur in the manufacturing process, thereby increasing the cost.

In addition, in the process of packaging the LED device on the base substrate, there is a problem in that the probability of breakage is rapidly increased or the risk of damage to the packaged product is increased.

As another method for improving the heat dissipation characteristics of the ceramic substrate, there is a method of using a base substrate having high heat dissipation characteristics. That is, as the base substrate, alumina, aluminum nitride (AlN), etc. are used according to the heat dissipation characteristics required for the substrate.

At this time, since alumina has a thermal conductivity of approximately 24 W/mk (W/m°C) and aluminum nitride (AlN) has a thermal conductivity of approximately 170 W/mk (W/m°C), in order to provide high heat dissipation characteristics Aluminum nitride is used as the base substrate.

However, aluminum nitride has a problem in that the cost is increased because the material price is about 7 to 10 times higher than that of alumina.

As described above, the method of improving the heat dissipation characteristics by changing the thickness and material of the base substrate is difficult to be applied to actual mass production due to problems such as reduced reliability and increased cost.

Meanwhile, referring to FIG. 1 , a conventional ceramic substrate 10 for an LED package has a first upper metal electrode 12 and a second upper metal electrode connected to the LED element on the upper surface of the base substrate 11 (ie, ceramic). (13) are formed to be spaced apart from each other, and on the lower surface of the base substrate, a first lower metal electrode 14 connected to the positive (+) pole of the main circuit board and a second lower metal electrode connected to a negative (-) pole ( 15) are formed spaced apart from each other.

In this case, in the base substrate 11 , a first via hole 16 for connecting the first upper metal electrode 12 and the first lower metal electrode 14 , the second upper metal electrode 13 , and the second lower metal A second via hole 17 for connecting the electrode 15 is formed.

At this time, the conventional ceramic substrate for an LED package has a failure due to the opening of a via (that is, the first via hole 16 or the second via hole 17) during the LED device mounting process or the LED package is mounted and used in a device. And there is a problem that a defect occurs.

Korean Patent Application Laid-Open No. 10-2010-0068593 (Title: Method of Laminating Copper Foil on Ceramic Material Substrate)

The present invention has been proposed to solve the above-mentioned problems in the prior art. The upper electrode and the lower electrode respectively formed on the upper and lower surfaces of a ceramic substrate are connected to a plurality of via holes, and a thermally conductive material is filled in the via holes to form a ceramic substrate. An object of the present invention is to provide a ceramic substrate to improve the heat dissipation characteristics of and an LED package including the same.

In order to achieve the above object, a ceramic substrate according to an embodiment of the present invention includes a base substrate made of a ceramic material in which a plurality of via holes are formed, a first upper electrode formed on the upper surface of the base substrate, a first upper electrode on the upper surface of the base substrate, and a second upper electrode formed to be spaced apart from each other, a first lower electrode formed on a lower surface of the base substrate, and a second lower electrode formed to be spaced apart from the first lower electrode on a lower surface of the base substrate, wherein the plurality of via holes include a first upper electrode and It is formed in a first overlapping area where the first lower electrode overlaps and a second overlapping area where the second upper electrode and the second lower electrode overlap.

The plurality of via holes may include a first via hole formed in the first overlapping region and a second via hole formed in the first overlapping region spaced apart from the first via hole. In this case, the second via hole may be spaced apart from the first via hole by a predetermined interval or more, and the predetermined interval may be a diameter of one selected from the first via hole and the second via hole.

Also, the plurality of via holes may further include a third via hole formed in the second overlapping area spaced apart from the first overlapping area and a fourth via hole formed in the second overlapping area spaced apart from the third via hole. In this case, the fourth via hole may be spaced apart from the third via hole by a predetermined interval or more, and the predetermined interval may be a diameter of one selected from the third via hole and the fourth via hole.

One or more metals selected from copper (Cu), silver (Ag), tin (Sn), indium (In), nickel (Ni), and chromium (Cr) may be filled in the plurality of via holes.

The first upper electrode and the second upper electrode are an LED electrode on which a selected one of an anode and a cathode of the LED element is mounted, a zener electrode on which a selected one of an anode and a cathode of the Zener diode is mounted, and are disposed spaced apart from the LED electrode, and It may include a connection electrode for connecting the LED electrode and the Zener electrode. In this case, the electrode for the LED may be connected to a selected one of the first lower electrode and the second lower electrode and two or more via holes.

In order to achieve the above object, an LED package including a ceramic substrate according to an embodiment of the present invention includes a ceramic substrate mounted on one surface of a main circuit board and an LED device mounted on the ceramic substrate, and the ceramic substrate is made of a ceramic material. The first upper electrode formed on the upper surface of the base substrate, the second upper electrode formed on the upper surface of the base substrate to be spaced apart from the first upper electrode, and the first lower electrode formed on the lower surface of the base substrate and connected to the first upper electrode and the plurality of via holes. and a second lower electrode formed on a lower surface of the base substrate to be spaced apart from the first lower electrode and connected to the second upper electrode and a plurality of via holes.

The LED element may have one end mounted on the first LED electrode of the first upper electrode, and the other end mounted on the second LED electrode of the second upper electrode.

The first electrode for LED may be connected to the first lower electrode through a plurality of via holes, and the second electrode for LED may be connected to the second lower electrode through a plurality of via holes.

A Zener diode may further include one end mounted on the Zener electrode of the first upper electrode and the other end mounted on the Zener electrode of the second upper electrode.

According to the present invention, since the ceramic substrate forms via holes in the green sheet state before firing, it is easy to process, and the cost of forming via holes can be minimized compared to the prior art of forming via holes in the fired base substrate. In this case, when the via hole is formed in the green sheet state, since the via hole can be formed by an easy process such as a punching process, the via hole is approximately 80 to 90% higher than that in the case of forming the via hole in the sintered ceramic. The hole forming cost is reduced.

In addition, the ceramic substrate forms a metal hole inside the via hole through plating, and fills the via hole by forming a metal layer by filling the inside of the metal hole with paste. It is possible to minimize an increase in filling cost due to an increase in the diameter of the via hole.

In addition, since the ceramic substrate does not fill the entire via hole with plating, but only the surface of the via hole is plated and the rest is filled with paste, the plating cost is reduced. That is, in the ceramic substrate manufacturing method, a low-cost process such as a screen printing process can be applied during paste filling, so that the overall via hole filling cost can be maintained at the same level as that of the prior art.

In addition, since the ceramic substrate forms via holes in the green sheet state before firing, there is no change in processing cost even if the diameter of the via hole increases, so that the size of the via hole can be easily adjusted as needed.

In addition, since the ceramic substrate forms a metal hole by plating the inner wall surface of the via hole, the defects of the conventional ceramic substrate manufacturing method of completely filling the via hole by plating and the plating solution residual phenomenon do not occur.

In addition, since the ceramic substrate forms via holes in the green sheet state before firing, local defects (cracks) do not occur in residues and the base substrate after via hole formation. That is, the ceramic substrate manufacturing method and the ceramic substrate are filled with the plating process to a required thickness when the via hole is filled, so that the central part is open. I never do that.

In addition, since the ceramic substrate is subjected to a heat treatment process after filling the remaining area with a paste after plating of the via hole, even if a portion of the plating solution remains, it can be removed through heat treatment.

Accordingly, the ceramic substrate can increase the process yield and reliability compared to the ceramic substrate to which the conventional process is applied.

In addition, since the ceramic substrate has a flat upper end of the via hole and there is no defect containing liquid inside the via hole, a semiconductor chip can be directly mounted on the via hole, and heat can be emitted directly through the via hole to improve heat dissipation characteristics. can be maximized

In addition, by increasing the size of the via hole without increasing the manufacturing cost of the ceramic substrate, heat dissipation characteristics of the ceramic substrate may be increased compared to the conventional method of manufacturing the ceramic substrate.

In addition, since the ceramic substrate has no internal defects (eg, liquid residual defects such as plating solution) by planarizing the surface of the via hole through a polishing process, the semiconductor chip is mounted on the upper end of the via hole to maximize heat dissipation characteristics.

In addition, since the ceramic substrate and the LED package including the same connect the upper electrode and the lower electrode through a plurality of via holes, it is possible to prevent failures and defects due to opening of the vias.

That is, since the conventional ceramic substrate connects the upper electrode and the lower electrode using one via hole, the ceramic substrate cannot be used when a via is opened.

On the other hand, since the ceramic substrate according to the embodiment of the present invention connects the upper electrode and the lower electrode through a plurality of via holes, even if one via hole is opened, the other via hole maintains the connection state of the upper electrode and the lower electrode. This has the effect of minimizing the occurrence of failures and defects due to via opening.

In addition, the ceramic substrate and the LED package including the same connect the upper electrode and the lower electrode through a plurality of via holes, thereby increasing the contact area with the LED element and connecting the upper electrode and the lower electrode through one via hole. There is an effect that can increase the heat dissipation characteristics compared to the ceramic substrate of

That is, the ceramic substrate forms a plurality of via holes in the base substrate and fills the via holes with a metal having higher heat dissipation properties than ceramics, thereby increasing the size of the via holes formed in the base substrate and filling the via holes with a conductive material. There is an effect that can improve the heat dissipation characteristics of the substrate by increasing the contribution of heat dissipation.

1 is a view for explaining a conventional ceramic substrate for an LED package.
2 to 5 are views for explaining a method of manufacturing a ceramic substrate according to an embodiment of the present invention.
6 and 7 are views for explaining a ceramic substrate according to an embodiment of the present invention.
FIG. 8 is a view showing a cross-section taken along line A-A' of FIG. 6;
FIG. 9 is a view for explaining the first upper electrode of FIG. 6 ;
FIG. 10 is a view for explaining a second upper electrode of FIG. 6 ;
11 and 12 are views for explaining an LED package according to an embodiment of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described with reference to the accompanying drawings in order to describe in detail enough that a person of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention. . First of all, in adding reference numerals to the components of each drawing, it should be noted that the same components are given the same reference numerals as much as possible even though they are indicated on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

2 and 3 , the method of manufacturing a ceramic substrate 400 according to an embodiment of the present invention includes a base substrate 100 preparation step (S100), a via hole 200 forming step (S200), and a firing step. (S300), the seed layer 351 forming step (S400), the via hole 200 plating step (S500), the via hole 200 filling step (S600), the planarization step (S700), the etching step (S800) and the metal layer and (356) forming step (S900).

In the base substrate 100 preparation step (S100), the base substrate 100 is prepared. At this time, in the case of preparing the base material 100 with the ceramic in which the base material 100 is sintered, a large-scale facility investment and manufacturing cost are required when the via hole 200 is formed, and the size (diameter) of the via hole 200 is required. ), the manufacturing cost of the via hole 200 increases exponentially.

In addition, since the laser drill method for forming the via hole 200 locally melts and removes the base substrate 100 , there may be unwanted residues after the via hole 200 is formed, or the base substrate 100 . Local defects (cracks) may occur in the

Accordingly, in the base substrate 100 preparation step ( S100 ), the base substrate 100 , which is a green sheet in a pre-fired state, is prepared. In this case, the base substrate 100 is a green sheet containing at least one of oxides of alumina (Al2O3) and zirconium oxide (ZrO2), or a green sheet containing at least one of nitrides of aluminum nitride (AlN) and silicon nitride (Si3N4). In addition, it is clarified that it is possible to transform into a ceramic material that can be used for LED modules and the like.

Of course, in the base substrate 100 preparation step ( S100 ), a ceramic sheet in which a green sheet is fired may be prepared as the base substrate 100 . That is, in the base substrate 100 preparation step (S100), at least one of a green sheet containing at least one of alumina (Al2O3) and zirconium oxide (ZrO2), an oxide, and aluminum nitride (AlN) and silicon nitride (Si3N4). It is clarified that a ceramic sheet obtained by firing the included green sheet can be used as an example, and it can be transformed into a ceramic material that can be used for an LED module and the like.

In the via hole 200 forming step ( S200 ), a via hole 200 is formed in the base substrate 100 . In this case, in the via hole 200 forming step ( S200 ), the via hole 200 is formed in the base substrate 100 , which is a green sheet, through a punching process or a laser drilling process. Here, in the via hole 200 forming step ( S200 ), a cross section horizontal to the base substrate 100 may be formed in various shapes such as a circle, an ellipse, or a rectangle.

In the via hole 200 forming step ( S200 ), if the base substrate 100 is a sintered ceramic sheet, the via hole 200 is formed using a laser drilling process or a sand blasting process.

For example, when the sand blasting process is used in the via hole 200 forming step ( S200 ), both sides of the ceramic sheet are masked with photo resist or dry film, and then processed by sand blasting. to form the via hole 200 .

As such, in the ceramic substrate 400 manufacturing method, the via hole 200 is formed in the green sheet state before firing, so that processing is easy, and compared to the conventional method of forming the via hole 200 in the fired base substrate 100 , the via hole 200 is formed. The cost of forming the hole 200 can be minimized. In this case, when the via hole 200 is formed in the green sheet state, the cost is reduced by about 80 to 90% compared to the case of forming the via hole 200 in the sintered ceramic.

In the firing step ( S300 ), the base substrate 100 in which the via hole 200 is formed is fired. That is, in the firing step ( S300 ), when the base substrate 100 in the state of a green sheet is used, it is fired to form the rigid ceramic substrate 400 .

In the step of forming the seed layer 351 ( S400 ), a seed layer 351 is formed on the ceramic substrate 400 . That is, in the step of forming the seed layer 351 ( S400 ), the seed layer 351 of a predetermined thickness is formed on the inner wall of the via hole 200 together with the upper and lower surfaces of the ceramic substrate 400 . In this case, in the forming step (S400) of the seed layer 351, titanium (Ti), nickel (Ni), or chromium (Cr) having excellent bonding strength with the ceramic substrate 400 . One selected from zirconium (Zr) and copper (Cu), or titanium (Ti), nickel (Ni), chromium (Cr). A target material such as an alloy including at least one of zirconium (Zr) and copper (Cu) is deposited on the surface of the ceramic substrate 400 to form the seed layer 351 . Here, in the seed layer 351 forming step ( S400 ), deposition of one selected from evaporation, e-beam deposition, laser deposition, sputtering, and arc ion plating A seed layer 351 is formed through the process.

In this case, the seed layer 351 may be composed of two or more layers. For example, in the forming step (S400) of the seed layer 351, one selected from titanium (Ti), chromium (Cr) and zirconium (Zr) on the ceramic substrate 400 through sputtering, which is a physical coating method in a vacuum state, or titanium The seed layer 351 is formed by coating an alloy including at least one of (Ti), chromium (Cr), and zirconium (Zr). At this time, each layer is formed to a thickness of approximately 5nm to 10um. In addition, when these elements are in contact with air, at least one protective layer is coated to prevent oxidation, and the protective layer may be copper (Cu), nickel (Ni), or the like.

In the via hole 200 plating step ( S500 ), a plating layer 352 is formed on the inner wall surface of the via hole 200 through a plating process. That is, in the via hole 200 plating step S500 , a plating layer 352 is formed on the upper and lower surfaces of the ceramic substrate 400 and the inner wall surface of the via hole 200 through an electroplating process. In this case, the plating layer 352 is one selected from copper (Cu), nickel (Ni), and tin (Sn), or an alloy including one or more of copper (Cu), nickel (Ni), and tin (Sn). do it with Here, in the plating step S500 of the via hole 200 , a plating layer 352 having a predetermined thickness is formed on the inner wall surface of the via hole 200 to form a metal hole 353 in the center of the via hole 200 .

At this time, one or more plating layers 352 may be formed as needed, and one selected from copper (Cu), nickel (Ni), tin (Sn), and zinc (Zn), or copper (Cu), nickel (Ni) , an alloy including at least one of tin (Sn) and zinc (Zn) may be used.

As such, in the method of manufacturing the ceramic substrate 400 according to the embodiment of the present invention, the metal hole 353 is formed by plating the inner wall surface of the via hole 200 , and thus the conventional ceramic plate completely fills the via hole 200 by plating. Defects in the method of manufacturing the substrate 400 and residual plating solution do not occur.

Accordingly, the method of manufacturing the ceramic substrate 400 may increase the process yield and reliability compared to the ceramic substrate 400 to which the conventional process is applied.

In the via hole 200 filling step ( S600 ), a paste is filled in the metal hole 353 . For example, in the filling of the via hole 200 ( S600 ), the metal hole 353 is filled through a screen printing process.

In the filling of the via hole 200 ( S600 ), a filling layer 354 is formed by printing the paste to fill the metal hole 353 formed in the via hole 200 . In this case, the paste is one of copper (Cu), silver (Ag), tin (Sn), indium (In), nickel (Ni) and chromium (Cr), or copper (Cu), silver (Ag), tin (Sn) ), indium (In), nickel (Ni), and an alloy or mixture containing one or more of chromium (Cr) as an example.

In the filling step (S600) of the via hole 200, the additive is added to reduce the residual stress due to the difference in thermal contraction rate with the ceramic, and to maintain high thermal conductivity while alleviating the difference in thermal expansion (thermal shrinkage) between the filler and the ceramic. The filling layer 354 may be formed by printing the metal hole 353 formed in the via hole 200 . At this time, the additive is tungsten (W), molybdenum (Mo), silicon carbide (SiC), aluminum nitride (AlN), diamond, alumina (Al2O3), silicon nitride (Si3N4), silicon (Si), boron nitride (BN) and oxide For example, containing at least one of beryllium (BeO).

In the via hole 200 filling step (S600), the metal hole 353 formed in the via hole 200 is heat treated at a high temperature in a state in which the paste is filled to remove the binder contained in the paste, and sintered or melted. After cooling, the filling layer 354 is formed. In this case, the heat treatment conditions are an example of a temperature of about 1200° C. or less and one of an inert atmosphere and a vacuum atmosphere. Here, the heat treatment conditions may be changed depending on the type of paste, and heat treatment may not be performed.

As such, in the method of manufacturing the ceramic substrate 400 according to the embodiment of the present invention, the metal hole 353 is formed in the via hole 200 through plating, and the filling layer 354 is filled with a paste inside the metal hole 353 . ) to fill the via hole 200, thereby minimizing the increase in filling cost due to the increase in the diameter of the via hole 200 compared to the conventional ceramic substrate 400 manufacturing method of completely filling the via hole 200 with plating. can

In the planarization step ( S700 ), the surface of the ceramic substrate 400 is polished and planarized. That is, in the planarization step S700 , the base substrate 100 is planarized by polishing the surfaces of the plating layer 352 and the filling layer 354 formed when the via hole 200 is filled.

Meanwhile, referring to FIG. 4 , the method for manufacturing the ceramic substrate 400 according to the embodiment of the present invention may further include a planarization layer forming step (S650) to match the thickness of the plating layer 352 before the planarization step (S700). can

In the planarization layer forming step (S650), a planarization layer (not shown) is formed on the surface of the ceramic substrate 400 through electroplating. That is, in the planarization layer forming step ( S650 ), a planarization layer is formed on the surface of the ceramic substrate 400 through electroplating to match the desired thickness of the plating layer 352 .

In the planarization layer forming step S650, one metal selected from copper (Cu), nickel (Ni), tin (Sn), silver (Ag), and gold (Au), or copper (Cu), nickel (Ni), or tin A planarization layer (not shown) is formed using an alloy including at least one of (Sn), silver (Ag), and gold (Au). In this case, in the planarization layer forming step ( S650 ), a planarization layer (not shown) may be formed through multi-layer plating of two or more layers.

Meanwhile, referring to FIG. 5 , the method for manufacturing a ceramic substrate 400 according to an embodiment of the present invention includes a planarization layer forming step S720 and a planarization layer to match the thickness of the plating layer 352 after the planarization step S700. The step of polishing (S740) may be further included.

In the planarization layer forming step ( S720 ), after the surface of the ceramic substrate 400 is polished, a planarization layer (not shown) is formed through electroplating. That is, in the planarization layer forming step ( S720 ), a planarization layer is formed on the surface of the ceramic substrate 400 through electroplating to match the desired thickness of the plating layer 352 .

In this case, in the planarization layer forming step S720 , one metal selected from copper (Cu), nickel (Ni), tin (Sn), silver (Ag), and gold (Au), or copper (Cu), nickel (Ni) A planarization layer (not shown) is formed using an alloy including at least one of , tin (Sn), silver (Ag), and gold (Au). In this case, in the planarization layer forming step ( S720 ), a planarization layer (not shown) may be formed through multi-layer plating of two or more layers.

In the step of polishing the planarization layer ( S740 ), the surface of the planarization layer is polished. That is, in the polishing of the planarization layer ( S740 ), the surface of the planarization layer is polished to improve the surface flatness of the ceramic substrate 400 .

In the etching step ( S800 ), a circuit pattern having a predetermined shape is formed by etching the surface of the ceramic substrate 400 . That is, in the etching step (S800), a photoresist layer 355 is formed on the surface of the ceramic substrate 400 (S820), at least one of the seed layer 351 and the plating layer 352 is partially etched, and then the photoresist layer By removing 355 ( S840 ), a circuit pattern having a predetermined shape is formed.

In the step of forming the metal layer 356 ( S900 ), the metal layer 356 is formed on the surface of the circuit pattern. That is, in the metal layer 356 forming step (S900), a material that facilitates bonding of the LED device 500 and the ceramic substrate 400 through a plating process or a deposition process is applied to the circuit pattern (ie, the plating layer 352 and the filling layer). A metal layer 356 is formed by plating on the surface of (354)). In this case, in the metal layer 356 forming step ( S900 ), the metal layer 356 is formed on the surface of the plating layer 352 exposed to the upper and lower surfaces of the base substrate 100 and the surface of the filling layer 354 .

Another plating layer (not shown) may be disposed between the metal layer 356 and the filling layer 354 . That is, if the thickness of the plating layer 352 is thinner than the thickness of the required electrode, plating may be performed once again after filling the via hole 200 . In this case, the metal layer 356 does not directly contact the filling layer 354 . Accordingly, the top surfaces of the plating layer 352 and the filling layer 354 may not coincide with each other.

Here, although the metal layer 356 is shown to be formed only on one surface (ie, the upper surface or the lower surface) of the circuit pattern in FIG. 2 , it may be formed on the side surface of the circuit pattern in a plating or deposition process.

Here, in the metal layer 356 forming step (S900), one selected from copper (Cu), nickel (Ni), gold (Au), silver (Ag) palladium (Pd) and tin (Sn), or copper (Cu), An alloy containing at least one selected from nickel (Ni), gold (Au), silver (Ag), palladium (Pd), and tin (Sn) is an example. In this case, the metal layer 356 may be an alloy such as nickel and gold (Ni/Au), nickel and silver (Ni/Ag), or gold and tin (Au/Sn).

In the step of forming the metal layer 356 ( S900 ), the metal layer 356 including multiple layers (ie, two or more layers) may be formed. In this case, each layer of the metal layer 356 may be one selected from copper (Cu), nickel (Ni), gold (Au), silver (Ag), palladium (Pd), and tin (Sn), and adjacent layers are different from each other. It may be formed of a material.

For example, when the metal layer 356 has two layers, the first layer is a metal including nickel (Ni), and the second layer is selected from among gold (Au), silver (Ag), palladium (Pd), and tin (Sn). It may be a single metal.

As another example, when the metal layer 356 consists of three layers, the first layer is a metal including nickel (Ni), and the second layer is gold (Au), silver (Ag), palladium (Pd), and tin (Sn). It is a metal including one, and the third layer may be a metal including one of gold (Au), silver (Ag), and tin (Sn).

As described above, in the method of manufacturing the ceramic substrate 400 according to the embodiment of the present invention, the upper end of the via hole 200 is flat and there is no defect including liquid inside the via hole 200 . It is possible to directly mount the LED chip on the device, and direct heat dissipation through the via hole 200 is possible, thereby maximizing the heat dissipation characteristics.

As described above, in the method of manufacturing the ceramic substrate 400 according to the embodiment of the present invention, the entire via hole 200 is not filled with plating, but only the surface of the via hole 200 is plated and the rest is filled with paste. The plating cost is reduced. That is, in the method of manufacturing the ceramic substrate 400 , a low-cost process such as a screen printing process can be applied when the paste is filled, so that the overall cost of filling the via hole 200 can be maintained at the same level as that of the prior art.

In addition, the ceramic substrate 400 manufacturing method forms the via hole 200 in the green sheet state before firing, so that even if the diameter of the via hole 200 increases, there is no change in the processing cost. can be easily adjusted accordingly.

In addition, in the ceramic substrate 400 manufacturing method, local defects (cracks) do not occur in residues and the base substrate 100 after the via holes 200 are formed by forming the via holes 200 in the green sheet state before firing. does not

That is, in the method of manufacturing the ceramic substrate 400 , since the central portion is opened by filling only the required thickness during the filling of the via hole 200 by the plating process, unlike the conventional method of manufacturing the ceramic substrate 400 , the via hole 200 ) There is no defect that the plating solution remains inside.

In addition, since the ceramic substrate 400 manufacturing method performs a heat treatment process after filling the remaining area with a paste after plating of the via hole 200 , even if a portion of the plating solution remains, it can be removed through heat treatment.

In addition, the method of manufacturing the ceramic substrate 400 increases the size of the via hole 200 without increasing the manufacturing cost, thereby increasing the heat dissipation characteristics of the ceramic substrate 400 compared to the conventional method of manufacturing the ceramic substrate 400 .

In addition, in the method of manufacturing the ceramic substrate 400 , since the surface of the via hole 200 is planarized through a polishing process, there is no internal defect (eg, liquid residual defect such as a plating solution) at the upper end of the via hole 200 . By mounting an LED chip, heat dissipation characteristics can be maximized.

6 to 8 , a ceramic substrate 400 according to an embodiment of the present invention includes a base substrate 100 made of a ceramic material.

The base substrate 100 is a ceramic material having a predetermined thickness, and is a ceramic substrate 400 including at least one of oxides of alumina (Al2O3) and zirconium oxide (ZrO2), or nitrides of aluminum nitride (AlN) and silicon nitride (Si3N4). ) is a ceramic substrate 400 including at least one of them. At this time, it is revealed that the base substrate 100 can be transformed into a ceramic material that can be used in an LED package.

A first upper electrode 310 is formed on an upper surface of the base substrate 100 . In this case, the first upper electrode 310 is connected to a selected one of a positive (+) pole and a negative (-) pole of the LED device 500 mounted on the upper surface of the ceramic substrate 400 .

Referring to FIG. 9 , the first upper electrode 310 includes a first LED electrode 312 , a first Zener electrode 314 , and a first connection electrode 316 . Here, the first LED electrode 312, the first Zener electrode 314, and the first connection electrode 316 are integrally formed in the actual product, but are separated in order to easily understand the embodiment of the present invention. Explain.

The first electrode 312 for LED is formed on the upper surface of the base substrate 100 . The first electrode for LED 312 is connected to a selected one of a positive (+) pole or a negative (-) pole of the LED element 500 mounted on the upper surface of the ceramic substrate 400 . In this case, as an example, the first electrode 312 for LED is formed in a rectangular shape having a long side and a short side.

The first Zener electrode 314 is formed on the upper surface of the base substrate 100 , and is disposed to be spaced apart from the first LED electrode 312 by a predetermined distance. At this time, the first Zener electrode 314 is connected to a selected one of the anode (+) or the cathode (-) of the Zener diode 600 mounted on the upper surface of the base substrate 100 for static electricity protection.

The first connection electrode 316 is formed on the upper surface of the base substrate 100 . In this case, the first connection electrode 316 has one end connected to the first LED electrode 312 , and the other end connected to the first Zener electrode 314 .

The second upper electrode 320 is formed on the upper surface of the base substrate 100 . At this time, the second upper electrode 320 is formed to be spaced apart from the first upper electrode 310 by a predetermined distance, and the positive (+) and negative (-) poles of the LED device 500 mounted on the upper surface of the ceramic substrate 400 are formed. ) connected to a selected one of the poles. Here, the second upper electrode 320 is connected to an electrode different from the first upper electrode 310 (ie, the positive (+) pole or the negative (-) pole of the LED element 500 ).

Referring to FIG. 10 , the second upper electrode 320 includes a second LED electrode 322 , a second Zener electrode 324 , and a second connection electrode 326 . Here, the second LED electrode 322 , the second Zener electrode 324 , and the second connection electrode 326 are integrally formed in the actual product, but are separated in order to easily understand the embodiment of the present invention. Explain.

The second electrode for LED 322 is formed on the upper surface of the base substrate 100 . The second electrode for LED 322 is connected to a selected one of a positive (+) pole or a negative (-) pole of the LED element 500 mounted on the upper surface of the ceramic substrate 400 . In this case, as an example, the second electrode 322 for LED is formed in a rectangular shape having a long side and a short side.

The second electrode for LED 322 is formed to be spaced apart from the first electrode 312 for LED by a predetermined distance. In this case, the second electrode 322 for LED is formed so that one side in the direction of the first electrode for LED 312 is spaced apart from the first electrode 312 for the first LED by at least a set interval (eg, about 100 μm).

The second Zener electrode 324 is formed on the upper surface of the base substrate 100 , and is disposed to be spaced apart from the second LED electrode 322 by a predetermined distance. In this case, the second Zener electrode 324 is disposed to be spaced apart from the first Zener electrode 314 by a predetermined distance.

The second Zener electrode 324 is connected to a selected one of an anode (+) or a cathode (-) of a Zener diode 600 mounted on the upper surface of the base substrate 100 for static electricity protection.

The second connection electrode 326 is formed on the upper surface of the base substrate 100 . At this time, the second connection electrode 326 has one end connected to the second LED electrode 322 , and the other end connected to the second Zener electrode 324 .

The first lower electrode 330 is formed on the lower surface of the base substrate 100 . In this case, the first lower electrode 330 is formed in a region corresponding to the first upper electrode 310 formed on the upper surface of the ceramic substrate 400 , and is formed to overlap at least a portion with the first upper electrode 310 .

The first lower electrode 330 is respectively connected to a selected one of a positive (+) pole and a negative (-) pole of the main circuit board 700 on which the ceramic substrate 400 is mounted. Here, as an example, the positive (+) and negative (-) poles of the main circuit board 700 are patterns for power supply formed on the main circuit board 700 for supplying power to the LED element 500 .

The second lower electrode 340 is formed on the lower surface of the base substrate 100 . In this case, the second lower electrode 340 is formed in a region corresponding to the second upper electrode 320 formed on the upper surface of the ceramic substrate 400 , and at least partially overlaps the second upper electrode 320 .

The second lower electrode 340 is formed to be spaced apart from the first lower electrode 330 by a predetermined distance, and among the positive (+) and negative (-) poles of the main circuit board 700 on which the ceramic substrate 400 is mounted. Each is linked to the selected one. Here, the second lower electrode 340 is connected to an electrode different from the first lower electrode 330 (ie, a positive (+) or negative (-) electrode of the main circuit board 700 ).

Meanwhile, the metal electrodes 300 (ie, the first upper electrode 310 , the second upper electrode 320 , the first lower electrode 330 , and the second lower electrode formed on the upper and lower surfaces of the base substrate 100 ) 340 ) may be configured by sequentially stacking a seed layer 351 , a plating layer 352 , and a metal layer 356 . That is, the metal electrode 300 may include a seed layer 351 formed on the base substrate 100 , a plating layer 352 formed on the seed layer 351 , and a metal layer 356 formed on one surface of the plating layer 352 . can

The seed layer 351 is formed on the surface of the base substrate 100 and is selected from among titanium (Ti), copper (Cu), chromium (Cr) and zirconium (Zr) having excellent bonding strength with the base substrate 100 which is a ceramic material. One or an alloy including one or more of titanium (Ti), copper (Cu), chromium (Cr), and zirconium (Zr) is an example.

Here, the seed layer 351 is formed through one deposition process selected from evaporation, e-beam deposition, laser deposition, sputtering, and arc ion plating. .

The seed layer 351 is one selected from titanium (Ti), chromium (Cr), and zirconium (Zr), or after coating an alloy including one or more of titanium (Ti), chromium (Cr), and zirconium (Zr). It may be formed by coating copper (Cu).

The plating layer 352 is formed on one surface of the seed layer 351 . In this case, the plating layer 352 may be formed on the seed layer 351 through an electroplating process. Here, the plating layer 352 is one selected from copper (Cu), nickel (Ni), and silver (Ag), or an alloy including one or more of copper (Cu), nickel (Ni), and silver (Ag). do it with

The metal layer 356 is formed on one surface of the plating layer 352 . In this case, the metal layer 356 is formed by plating a conductive material on the surface of the plating layer 352 through a plating process or a deposition process. The metal layer 356 may be one selected from copper (Cu), nickel (Ni), gold (Au), silver (Ag), and tin (Sn), or nickel and gold (Ni/Au), nickel and silver (Ni/Ag). ), gold and tin (Au/Sn), nickel, palladium, and multilayer alloys such as gold (Ni/Pd/Au).

Meanwhile, in the metal electrodes 300 , a region connected to the via hole 200 may be formed of only the metal layer 356 . That is, the metal electrodes 300 may include a metal layer 356 in a region connected to the via hole 200 and a filling layer 354 formed on the lower surface of the metal layer 356 .

A plurality of via holes 200 for connecting the upper electrode and the lower electrode are formed in the base substrate 100 . In this case, the base substrate 100 may be formed by forming a plurality of via holes 200 in a green sheet state and then firing, or may be manufactured by firing the green sheet and then forming the via holes 200 . Here, the via hole 200 is filled by the plating layer 352 formed on the inner wall surface and the filling layer 354 formed in the metal hole 353 formed inside the via hole 200 by the plating layer 352 .

In this case, the plurality of via holes 200 penetrate the base substrate 100 to form an upper electrode (ie, the first upper electrode 310 or the second upper electrode 320 ) and a lower electrode (ie, the first lower electrode ( 330) or the second lower electrode 340) is electrically connected.

In the base substrate 100 , a first via hole 220 and a second via hole 240 are formed. In this case, the first via hole 220 and the second via hole 240 are formed through the base substrate 100 to connect the first upper electrode 310 and the first lower electrode 330 . That is, the first via hole 220 and the second via hole 240 are formed through the base substrate 100 , and are formed in a region where the first LED electrode 312 and the first lower electrode 330 overlap. is formed One end of the first via hole 220 and the second via hole 240 is connected to the first electrode for LED 312 , and the other end is connected to the first lower electrode 330 .

The first via hole 220 and the second via hole 240 are formed to be spaced apart from each other by a predetermined distance. In this case, the first via hole 220 and the second via hole 240 are formed to have the same first diameter, and the spacing between the first via hole 220 and the second via hole 240 is greater than the first diameter. long formed. Here, when the first diameter is Φ1, the spacing between the first via hole 220 and the second via hole 240 is about Φ1+1 μm as an example.

The first via hole 220 and the second via hole 240 may be formed to have a maximum cross-section within the overlapping area of the first upper electrode 310 and the first lower electrode 330 while securing a separation distance. . That is, the first via hole 220 and the second via hole 240 maximize the contact area between the first upper electrode 310 and the first lower electrode 330 in order to improve the heat dissipation effect.

Here, the first via hole 220 and the second via hole 240 have been described as having the same diameter as an example, but the present invention is not limited thereto and may be formed to have different diameters. In this case, the spacing between the first via hole 220 and the second via hole 240 may be formed to be longer than any one diameter.

The base substrate 100 has a third via hole 260 and a fourth via hole 270 formed therein. In this case, the third via hole 260 and the fourth via hole 270 are formed through the base substrate 100 to connect the second upper electrode 320 and the second lower electrode 340 . That is, the third via hole 260 and the fourth via hole 270 are formed to pass through the base substrate 100 , and are formed in a region where the second LED electrode 322 and the second lower electrode 340 overlap. is formed The third via hole 260 and the fourth via hole 270 have one end connected to the second LED electrode 322 and the other end connected to the second lower electrode 340 .

The third via hole 260 and the fourth via hole 270 may be formed to have a maximum cross-section within the overlapping area of the second upper electrode 320 and the second lower electrode 340 while securing a separation distance. . That is, the third via hole 260 and the fourth via hole 270 maximize the contact area between the second upper electrode 320 and the second lower electrode 340 in order to improve the heat dissipation effect.

The third via hole 260 and the fourth via hole 270 are formed to be spaced apart from each other by a predetermined distance. In this case, the third via hole 260 and the fourth via hole 270 are formed to have the same second diameter, and the spacing between the third via hole 260 and the fourth via hole 270 is greater than the second diameter. long formed. Here, when the second diameter is Φ2, the spacing between the third via hole 260 and the fourth via hole 270 is approximately Φ2+1 μm.

Here, the third via hole 260 and the fourth via hole 270 have been described as having the same diameter as an example, but the present invention is not limited thereto and may be formed to have different diameters. In this case, the spacing between the third via hole 260 and the fourth via hole 270 may be formed to be longer than any one diameter.

Here, although the upper electrode and the lower electrode are illustrated as being connected to the two via holes 200 in FIGS. 6 to 8 , the present invention is not limited thereto and may be connected by three or more via holes 200 .

However, if the number of via holes 200 for connecting the upper electrode and the lower electrode increases, the cost of forming the via hole 200 (laser drilling) and the cost of filling the via hole 200 (via filling, plating) are exponentially increased. increases

Therefore, the upper electrode and the lower electrode are connected by two via holes 200 , and it is preferable to form each via hole 200 to have a maximum diameter.

Meanwhile, the via hole 200 (ie, the first via hole 220 to the fourth via hole 270 ) includes a seed layer 351 , a plating layer 352 , and a filling layer 354 .

The seed layer 351 is formed on the inner wall surface of the via hole 200 . In this case, the seed layer 351 is formed to a predetermined thickness and is integrally formed with the seed layer 351 of the above-described metal electrode 300 .

The plating layer 352 is formed on the seed layer 351 . The plating layer 352 is formed on the seed layer 351 to a predetermined thickness to form a metal hole 353 in the via hole 200 . The upper surface (or lower surface) of the plating layer 352 may be planarized to coincide with the upper surface (or lower surface) of the filling layer 354 .

The filling layer 354 is formed in the metal hole 353 formed in the via hole 200 by the plating layer 352 . In this case, the filling layer 354 electrically connects the metal electrodes 300 (ie, the metal layer 356 of the metal electrode 300 ) disposed at the upper and lower ends of the via hole 200 . Here, the upper surface (or lower surface) of the filling layer 354 may be planarized to coincide with the upper surface (or lower surface) of the plating layer 352 .

The filling layer 354 is formed by heat-treating after a paste is filled in the metal hole 353 formed in the via hole 200 through a printing process. In this case, the paste is one of copper (Cu), silver (Ag), tin (Sn), indium (In), nickel (Ni) and chromium (Cr), or copper (Cu), silver (Ag), tin (Sn) ), indium (In), nickel (Ni), and an alloy or mixture containing at least one of chromium (Cr) is an example.

Here, the paste is one selected from tungsten (W), molybdenum (Mo), silicon carbide (SiC), aluminum nitride (AlN), diamond, boron nitride (BN), and beryllium oxide (BeO), or tungsten (W), molybdenum An additive including at least one of (Mo), silicon carbide (SiC), aluminum nitride (AlN), diamond, boron nitride (BN), and beryllium oxide (BeO) may be further included.

As described above, the ceramic substrate 400 according to the embodiment of the present invention connects the upper electrode and the lower electrode through the plurality of via holes 200, thereby preventing failure and failure due to the opening of the via. there is an effect

That is, since the conventional ceramic substrate 400 connects the upper electrode and the lower electrode using one via hole 200 , the ceramic substrate 400 cannot be used when a via is opened.

On the other hand, since the ceramic substrate 400 according to the embodiment of the present invention connects the upper electrode and the lower electrode through a plurality of via holes 200, even if one via hole 200 is opened, another via hole ( 200) maintains the connection state of the upper electrode and the lower electrode, thereby minimizing the occurrence of failures and defects due to via opening.

In addition, the ceramic substrate 400 connects the upper electrode and the lower electrode through the plurality of via holes 200 , thereby increasing the contact area with the LED device 500 , thereby increasing the upper electrode and the lower electrode through one via hole 200 . Compared to the conventional ceramic substrate 400 for connecting electrodes, there is an effect of increasing heat dissipation characteristics.

That is, the ceramic substrate 400 is formed in the base substrate 100 by forming a plurality of via holes 200 in the base substrate 100 and filling the via holes 200 with a metal having higher heat dissipation characteristics than ceramic. There is an effect of increasing the size of the via hole 200 and filling the via hole 200 with a conductive material to increase the contribution of heat dissipation, thereby improving the heat dissipation characteristics of the substrate.

11 and 12 , the LED package according to the embodiment of the present invention includes a ceramic substrate 400 , an LED device 500 , and a Zener diode 600 .

The ceramic substrate 400 has a first upper electrode 310 and a second upper electrode 320 spaced apart from each other on an upper surface thereof, and a first lower electrode 330 and a second lower electrode 340 spaced apart from each other on a lower surface of the ceramic substrate 400 . this is formed In this case, the first upper electrode 310 and the first lower electrode 330 are disposed to face each other around the ceramic substrate 400 to form a first overlapping region, and the second upper electrode 320 and the second lower electrode ( 340 is disposed to face the ceramic substrate 400 to form a second overlapping region.

In the ceramic substrate 400 , first via holes 220 to fourth via holes 270 connecting the upper electrode and the lower electrode are formed. In this case, the first via hole 220 and the second via hole 240 are formed to be spaced apart from each other by a predetermined distance, and pass through the first overlapping region to connect the first upper electrode 310 and the first lower electrode 330 to each other. connect The third via hole 260 and the fourth via hole 270 are formed to be spaced apart from each other by a predetermined distance, and pass through the second overlapping region to connect the second upper electrode 320 and the second lower electrode 340 . .

The ceramic substrate 400 is mounted on one surface of the main circuit board 700 . The first lower electrode 330 and the second lower electrode 340 formed on the lower surface of the ceramic substrate 400 contact the positive (+) and negative (+) electrodes of the main circuit board 700 , respectively. Here, as an example, the main circuit board 700 is a board mounted in an electronic device on which the LED package is mounted.

The LED element 500 is mounted on the upper surface of the ceramic substrate 400 . The LED element 500 is mounted to contact the first upper electrode 310 and the second upper electrode 320 formed on the upper surface of the ceramic substrate 400 . At this time, the LED element 500 is in contact with the first electrode 312 for LED of the first upper electrode 310 and the second electrode 322 for LED of the second upper electrode 320 .

The LED element 500 has a positive (+) pole and a negative (-) pole in contact with the first upper electrode 310 and the second upper electrode 320 , respectively. Here, the positive (+) pole of the LED element 500 is connected to one electrode connected to the positive (+) pole of the main circuit board 700 among the first upper electrode 310 and the second upper electrode 320 and , the negative (-) pole of the LED element 500 is connected to the other electrode.

The Zener diode 600 is mounted on the top surface of the ceramic substrate 400 . The Zener diode 600 is mounted to contact the first upper electrode 310 and the second upper electrode 320 formed on the upper surface of the ceramic substrate 400 . In this case, the Zener diode 600 is in contact with the first Zener electrode 314 of the first upper electrode 310 and the second Zener electrode 324 of the second upper electrode 320 .

The Zener diode 600 has an anode (+) and a cathode (Cathode; -) in contact with the first upper electrode 310 and the second upper electrode 320 , respectively. That is, in the Zener diode 600 , an anode and a cathode contact the first Zener electrode 314 of the first upper electrode 310 and the second Zener electrode 324 of the second upper electrode 320 , respectively. Here, the anode of the Zener diode 600 is connected to one electrode connected to the positive (+) electrode of the main circuit board 700 among the first upper electrode 310 and the second upper electrode 320, and the Zener diode ( 600) is connected to the other electrode.

Through this, the LED package may improve heat dissipation performance by transferring heat generated from the LED device 500 to the main circuit board 700 through the upper electrode, the via hole 200 and the lower electrode.

In particular, the LED package mounts the LED element 500 on the ceramic substrate 400 to which the upper electrode and the lower electrode are connected through a plurality of via holes 200, so that the LED element 500 and a metal having high heat dissipation performance (that is, , using a conventional ceramic substrate 400 that connects the upper electrode and the lower electrode through one via hole 200 by increasing the contact area of the conductive material filled in the via hole 200). Compared to the LED package, heat dissipation It has the effect of increasing the characteristics.

That is, the LED package forms a plurality of via holes 200 in the base substrate 100 and fills the via holes 200 with a metal having higher heat dissipation properties than ceramics, thereby forming a via hole formed in the base substrate 100 ( 200) and filling the via hole 200 with a conductive material to increase heat dissipation contribution, thereby improving heat dissipation characteristics.

In addition, since the LED package connects the upper electrode and the lower electrode of the base substrate 100 through a plurality of via holes 200 , there is an effect of preventing failures and defects due to opening of the vias.

That is, since the conventional LED package uses a ceramic substrate 400 that connects the upper electrode and the lower electrode using one via hole 200 , a failure occurs due to the opening of the via.

On the other hand, since the LED package according to the embodiment of the present invention connects the upper electrode and the lower electrode through a plurality of via holes 200 , even if one via hole 200 is opened, the other via hole 200 is By maintaining the connection state of the upper electrode and the lower electrode, there is an effect of minimizing the occurrence of failures and defects due to the opening of the via.

Although the preferred embodiment according to the present invention has been described above, it can be modified in various forms, and those of ordinary skill in the art can make various modifications and modifications without departing from the scope of the claims of the present invention. It is understood that it can be implemented.

100: base material 200: via hole
220: first via hole 240: second via hole
260: third via hole 270: fourth via hole
300: metal electrode 310: first upper electrode
312: electrode for first LED 314: first zener electrode
316: first connection electrode 320: second upper electrode
322: second LED electrode 324: second zener electrode
326: second connection electrode 330: first lower electrode
340: second lower electrode 351: seed layer
352: plating layer 353: metal hole
354: filling layer 355: photoresist layer
356: metal layer 400: ceramic substrate
500: LED element 600: Zener diode
700: main circuit board

Claims (12)

a ceramic base substrate having a plurality of via holes formed therein; and
a plurality of metal electrodes in which a seed layer, a plating layer, and a metal layer are sequentially stacked on the base substrate;
The metal electrode is
a first upper electrode formed on an upper surface of the base substrate;
a second upper electrode formed on an upper surface of the base substrate to be spaced apart from the first upper electrode;
a first lower electrode formed on a lower surface of the base substrate; and
and a second lower electrode formed on a lower surface of the base substrate to be spaced apart from the first lower electrode,
In the base substrate, a plurality of via holes are formed in each of a first overlapping region in which the first upper electrode and the first lower electrode overlap and a second overlapping region in which the second upper electrode and the second lower electrode overlap. becomes,
The via hole is
A seed layer formed on the inner wall surface, a plating layer formed on the seed layer, and a filling layer in which a paste is filled in the metal hole formed by the plating layer,
The metal electrode and the via hole are integrally formed with a seed layer and a plating layer,
The filling layer of the via hole,
A ceramic substrate electrically connecting the metal layer of the first upper electrode and the metal layer of the first lower electrode, and electrically connecting the metal layer of the second upper electrode and the metal layer of the second lower electrode. According to claim 1,
The plurality of via holes are
a first via hole formed in the first overlapping area; and
and a second via hole spaced apart from the first via hole by a predetermined distance or more and formed in the first overlapping area;
The set interval is a diameter of one selected from the first via hole and the second via hole. 3. The method of claim 2,
The plurality of via holes are
a third via hole formed in the second overlapping area spaced apart from the first overlapping area; and
and a fourth via hole spaced apart from the third via hole by a predetermined distance or more and formed in the second overlapping area;
The set interval is a diameter of one selected from the third via hole and the fourth via hole. According to claim 1,
The paste is a ceramic substrate comprising at least one metal selected from copper (Cu), silver (Ag), tin (Sn), indium (In), nickel (Ni), and chromium (Cr). According to claim 1,
The first upper electrode and the second upper electrode are
an electrode for an LED on which a selected one of an anode and a cathode of the LED element is mounted;
a zener electrode disposed to be spaced apart from the electrode for the LED and mounted with a selected one of an anode and a cathode of the zener diode; and
A ceramic substrate comprising a connection electrode for connecting the LED electrode and the Zener electrode. 6. The method of claim 5,
The electrode for the LED is a ceramic substrate connected to a selected one of the first lower electrode and the second lower electrode and two or more via holes. a ceramic substrate mounted on one surface of the main circuit board; and
Including an LED device mounted on the ceramic substrate,
The ceramic substrate is
It includes a plurality of metal electrodes in which a seed layer, a plating layer, and a metal layer are sequentially stacked on a ceramic base substrate,
The metal electrode is
a first upper electrode formed on the upper surface of the base substrate;
a second upper electrode formed on an upper surface of the base substrate to be spaced apart from the first upper electrode;
a first lower electrode formed on a lower surface of the base substrate and connected to the first upper electrode and a plurality of via holes; and
and a second lower electrode formed on a lower surface of the base substrate to be spaced apart from the first lower electrode and connected to the second upper electrode and a plurality of via holes,
The via hole is
A seed layer formed on the inner wall surface, a plating layer formed on the seed layer, and a filling layer in which a paste is filled in the metal hole formed by the plating layer,
The metal electrode and the via hole are integrally formed with a seed layer and a plating layer,
The filling layer of the via hole,
An LED package for electrically connecting the metal layer of the first upper electrode and the metal layer of the first lower electrode, and electrically connecting the metal layer of the second upper electrode and the metal layer of the second lower electrode. 8. The method of claim 7,
The LED element is
An LED package having one end mounted on the first LED electrode of the first upper electrode and the other end mounted on the second LED electrode of the second upper electrode. 9. The method of claim 8,
The first electrode for LED is connected to the first lower electrode through a plurality of via holes,
and the second electrode for LED is connected to the second lower electrode through a plurality of via holes. 8. The method of claim 7,
The LED package further comprising a Zener diode having one end mounted on the Zener electrode of the first upper electrode and the other end mounted on the Zener electrode of the second upper electrode. delete delete

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