KR102347841B1 - Memory management apparatus and control method thereof - Google Patents

Abstract

The present invention proposes a method for more efficiently increasing performance and reliability when configuring RAID in a storage system including a flash-based device such as an SSD.

Description

MEMORY MANAGEMENT APPARATUS AND CONTROL METHOD THEREOF

The present invention relates to a storage system, and more particularly, to a technology capable of more efficiently increasing performance and reliability in a storage system including a flash-based device such as an SSD.

Recently, as SSD (Solid State Drive) with improved performance compared to HDD (Hard Disk Drive) has been widely used, a storage system employing multiple flash-based SSDs is configured to provide data services through a network. .

For example, the storage system may simply support a block-level storage service to provide a data service, which may serve as a Storage Area Network (SAN) / NAS (Network Attached Storage) role, or Data service (eg DB, web service) can be provided directly by operating the application server.

In such a storage system composed of a plurality of flash-based SSDs, like a storage system composed of an existing HDD, devices can be bundled and used with a RAID algorithm for high performance and high reliability.

In the case of a flash-based device such as an SSD, the performance of a flash-based device such as a small write (hereinafter referred to as small write) is degraded similarly to that of the HDD, but unlike the HDD, it accelerates the P/E (program/erase) cycle. Additionally, it exhibits a weak reliability characteristic, and when devices are bundled through a RAID algorithm, that is, the reliability vulnerability is doubled due to the update of the parity information during RAID configuration.

Therefore, in the case of a storage system composed of conventional HDDs, high performance and high reliability could be achieved only by using a RAID configuration that bundles devices through a RAID algorithm. And there is a lack of achieving high reliability.

Accordingly, in the present invention, in a storage system composed of a plurality of flash-based SSDs, it is intended to propose a method for more efficiently increasing performance and reliability when configuring RAID.

The present invention was created in view of the above circumstances, and an object of the present invention is to more efficiently increase performance and reliability when configuring a RAID in a storage system composed of a flash-based device such as an SSD.

According to a first aspect of the present invention, there is provided a memory control device comprising: a grouping unit for grouping a plurality of memory chips constituting a memory device into two or more memory groups; an allocation control unit distributedly allocating write requests received from the memory device to the two or more memory groups so that data of the write requests are distributed and buffered in data buffers corresponding to the two or more memory groups; and independently performing a data write operation of writing data buffered in the data buffer to a corresponding memory group for each data buffer corresponding to each of the two or more memory groups, so that the write requests can be processed in parallel in units of memory groups. It includes a data recording control unit.

Preferably, the allocation control unit determines, for each of the write requests, a memory group to be allocated among the two or more memory groups based on a logical block address (LBA) of the write request and the number of memory groups Thus, it is possible to distribute and allocate to the two or more memory groups.

Preferably, in the data buffer, the transferred data is buffered at the most empty position in the data buffer, and in the data writing operation, when the data buffer is in a full state, all data buffered in the data buffer is buffered. and writing parity information related to all the data in a memory group corresponding to the data buffer, and emptying the data buffer.

Preferably, in the data buffer, transmitted data is buffered at an empty leading position in the data buffer, the data buffer is divided into two or more partial buffers, and the data write operation causes the data buffer to become full. Previously, when a specific partial buffer among the two or more partial buffers in the data buffer becomes full, the data buffered in the specific partial buffer is written to a memory group corresponding to the data buffer, and the last part of the two or more partial buffers When the buffer becomes full and the data buffer becomes full, the data buffered in the last partial buffer and parity information related to all data buffered in the data buffer are written to the memory group, and the data buffer is emptied. can be

Preferably, the partial buffer may be related to a chunk size of each memory chip included in the memory group.

Preferably, in the data buffer*, transferred data is buffered at an empty leading position in the data buffer, and the data writing operation takes out data at an earlier non-empty position in the data buffer to communicate with the data buffer. It may be an operation of writing to a corresponding memory group.

According to a second aspect of the present invention, there is provided an operating method of a memory control device, comprising: a grouping step of grouping a plurality of memory chips constituting the memory device into two or more memory groups; an allocation control step of distributedly allocating write requests received with respect to the memory device to the two or more memory groups so that data of the write requests are distributed and buffered in data buffers corresponding to each of the two or more memory groups; and independently performing a data write operation of writing data buffered in the data buffer to a corresponding memory group for each data buffer corresponding to each of the two or more memory groups, so that the write requests can be processed in parallel in units of memory groups. and a data recording control step.

Preferably, in the allocation control step, for each of the write requests, a memory group to be allocated among the two or more memory groups is selected based on a logical block addressing (LBA) of the write request and the number of memory groups. It can be determined and distributed to the two or more memory groups.

Preferably, in the data buffer, the transferred data is buffered at the most empty position in the data buffer, and in the data writing operation, when the data buffer is in a full state, all data buffered in the data buffer is buffered. and writing parity information related to all the data in a memory group corresponding to the data buffer, and emptying the data buffer.

Preferably, in the data buffer, the transferred data is buffered at the most empty position in the data buffer, the data buffer is divided into two or more partial buffers, and the data write operation is performed when the data buffer is in a full state. Before, when a specific partial buffer among the two or more partial buffers in the data buffer becomes full, the data buffered in the specific partial buffer is written to a memory group corresponding to the data buffer, and the last of the two or more partial buffers is written When the partial buffer becomes full and the data buffer becomes full, the data buffered in the last partial buffer and parity information related to all data buffered in the data buffer are written to the memory group, and the data buffer is emptied. It can be an action.

Accordingly, according to the memory control apparatus and the method of operating the memory control apparatus of the present invention, in a storage system configured with a flash-based device such as an SSD, performance and reliability can be more efficiently increased during RAID configuration.

1 is a schematic diagram showing the configuration of a storage system including a memory control device according to a preferred embodiment of the present invention.
2 is a block diagram specifically showing an apparatus for controlling a memory according to a preferred embodiment of the present invention.
3 and 4 are exemplary diagrams illustrating a path in which write requests are parallelly processed in units of memory groups in a storage system including a memory control device according to a preferred embodiment of the present invention.
5 is an operation flowchart illustrating a method of operating a memory control apparatus according to a preferred embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First, a configuration of a storage system including a memory control device according to a preferred embodiment of the present invention will be described with reference to FIG. 1 .

As shown in FIG. 1, the storage system includes a memory device 10 as a storage space, a file system or an application that attempts a memory operation to the memory device 10 (hereinafter referred to as the file system 200); and a memory control device 100 for controlling the memory device 10 between the file system 200 and the memory device 10 .

In this case, the memory device 10 includes a plurality of memory chips composed of several flash memories, wherein the memory chips are preferably flash-based devices such as solid state drives (SSDs).

That is, as shown in FIG. 1 , the memory device 10 may include a plurality of memory chips #0, #1, #2...#N-1, for example, N flash-based SSDs. .

The memory control device 100 may be a control module or control software for controlling the memory device 10 between the file system 200 and the memory device 10 .

Currently, as described above, a storage system employing a plurality of flash-based SSDs is used as an array to construct a memory array system having multiple arrays, that is, a storage system, and an external client computer ( (not shown) to provide data service.

In such a storage system, by adopting a redundancy algorithm (eg, a Redundant Array of Independent Disks (RAID) algorithm, hereinafter referred to as a RAID algorithm) for high performance and high reliability, memory chips, that is, SSDs can be bundled and used as a RAID algorithm.

However, in a storage system composed of a plurality of flash-based SSDs, there is a lack of achieving sufficient high performance and high reliability by only using a RAID configuration that bundles SSDs with a RAID algorithm as described above.

Accordingly, in the present invention, it is intended to propose a method for more efficiently increasing performance and reliability when configuring RAID in a storage system composed of a plurality of flash-based SSDs, and specifically to propose a memory control device for realizing this.

Hereinafter, a memory control apparatus according to a preferred embodiment of the present invention will be described in detail with reference to FIG. 2 . For convenience of description, reference numerals of the memory control apparatus 100 corresponding to the above-described FIG. 1 will be used for description.

The memory control device 100 according to the present invention includes a grouping unit 110 for grouping a plurality of memory chips constituting the memory device 10 into two or more memory groups, and a write request received from the memory device 10 . an allocation control unit 120 for distributedly allocating the data to the two or more memory groups so that the data of the write requests are distributed and buffered in data buffers corresponding to each of the two or more memory groups; The data write control unit 130 includes a data write control unit 130 that independently performs a data write operation for writing to a group for each data buffer corresponding to each of the two or more memory groups so that the write requests can be processed in parallel in units of memory groups.

The memory device 10 includes a plurality of memory chips composed of several flash memories, wherein the memory chips are preferably flash-based devices such as solid state drives (SSDs).

That is, as shown in FIG. 1 , the memory device 10 may include a plurality of memory chips, for example, N flash-based SSDs (#0, #1, #2...#N-1). . Hereinafter, for convenience of description, a memory chip and an SSD may be used interchangeably.

The memory control device 100 according to the present invention is a memory control device for controlling the memory device 10 composed of a plurality of flash-based SSDs, and may be in the form of a control module or control software, and controls the memory device 10 . The storage space (eg, data buffer, etc.)

The grouping unit 110 groups a plurality of memory chips #0, #1, #2...#N-1, for example, N SSDs constituting the memory device 10 into two or more memory groups.

That is, the memory control apparatus 100 according to the present invention is based on the RAID algorithm, that is, the memory chips, that is, SSDs are bundled and operated in the form of a memory group.

At this time, the memory control device 100 according to the present invention includes a plurality of memory chips (#0, #1, #2...#N-1) constituting the memory device 10, for example, N SSDs into one. Rather than grouping them to form a RAID, we want to configure a memory group, that is, a RAID group, which is grouped with fewer than N number of SSDs.

To this end, the grouping unit 110 divides a plurality of memory chips (#0, #1, #2...#N-1) constituting the memory device 10, for example, N SSDs into two or more memory groups. group it

Accordingly, referring to FIG. 3 , the grouping unit 110 includes N a plurality of memory chips #0, #1, #2...#N-1 constituting the memory device 10 . It can be grouped into M memory groups (#0...#M-1) by grouping them into smaller numbers (eg 5). After all, M memory groups (#0...#M-1) mean M RAID groups.

The allocation control unit 120 distributes and allocates write requests received for the memory device 10 to two or more memory groups grouped by the grouping unit 110, so that the data of the write requests is data corresponding to each of the two or more memory groups. Enable distributed buffering in the buffer.

Before describing the function of the allocation control unit 120, a storage space held inside the memory control device 100 to control the memory device 10, that is, the structure of the data buffer, will be described with reference to FIG. 3 . .

As shown in FIG. 3, in each of the grouped two or more memory groups, that is, the M memory groups #0...#M-1, a data buffer in which data to be written into the memory group is buffered is provided to correspond to each. do.

Accordingly, the data buffer #0 corresponds to the memory group #0, the data buffer #1 to the memory group #1, ... The data buffer #M is provided to correspond to the memory group #M.

In this case, the size of the data buffer is preferably a size capable of maximizing the performance of individual memory chips included in the memory group, that is, an individual SSD, or a size capable of maximizing the performance of a memory group, that is, a RAID group. .

For example, if a memory chip or SSD consists of 8 channels, 8 way, and the physical page size of flash memory is 8 KB, at least 512 KB, which is 8 x 8 x 8 KB, or 256 KB, which is half of that, is used as a data buffer. By determining the size of , the performance of individual SSDs can be maximized. This is a value that depends on the characteristics of the SSD.

On the other hand, for the maximum performance of the memory group, that is, the RAID group, it is important to minimize the parity information update. For example, if the RAID 5 algorithm is configured with 5 memory chips with a chunk size of 256 KB, if the data buffer size is 1024 KB, which is 4 x 256 KB, the performance of the memory group, that is, the RAID group, can be maximized. have.

Hereinafter, for convenience of explanation, 10 (N=10) memory chips are configured in the memory device 10 , and the 10 memory chips are grouped into 2 (M=2) memory groups in the grouping unit 110 . An example of grouping into #0 and memory group #1 will be described.

The memory control device 100 receives a request for attempting a memory operation with respect to the memory device 10 from the file system 200 . Hereinafter, a case in which a write request is received will be described for convenience of explanation of the present invention.

That is, the memory control device 100 receives a write request for attempting a write operation on the memory device 10 from the file system 200 .

The allocation control unit 120 divides each write request received from the file system 200 for the memory device 10, that is, each write request received in the order in which a write operation is attempted with respect to the memory device 10, in the grouping unit. Distributed allocation to two or more memory groups grouped in (110).

More specifically, for each of the received write requests, the allocation control unit 120 allocates among the two or more memory groups based on a logical block address (LBA) of the write request and the number of memory groups. By determining the memory group to be used, it is possible to distribute and allocate to two or more memory groups grouped by the grouping unit 110 .

Each write request received from the file system 200 is given a logical block address (LBA) of a numerical system that sequentially increases or decreases according to the received order.

Accordingly, for each of the received write requests, the allocation control unit 120 may determine a memory group to be allocated among two or more memory groups based on the logical block address (LBA) of the write request and the number of memory groups.

For example, the allocation control unit 120 selects a numbering memory group corresponding to the remainder of dividing the logical block address (LBA) of the write request by the number of memory groups (M), and selects a memory group to which the write request is to be allocated. can decide

3, referring to the write requests, that is, each write request 1, 2, 3, 4, 5, 6... received in the order in which a write operation is attempted with respect to the memory device 10, As described above, an example of grouping into two memory groups #0 and #1 will be described as follows.

The allocation control unit 120 checks the remaining value obtained by dividing the logical block address (LBA) of the received write request 1 by the number of memory groups (2). For example, if the remaining value is 0, the allocation control unit 120 determines the numbering memory group #0 corresponding to the remaining value 0 as the memory group to which the write request 1 is to be allocated, and the memory group # to which the write request 1 is determined. assigned to 0.

Accordingly, data 1 of write request 1 will be transferred to data buffer #0 of memory group #0 to which write request 1 is allocated and will be buffered in data buffer #0.

Similarly, the allocation control unit 120 checks the remainder obtained by dividing the logical block address (LBA) of the received write request 2 by the number of memory groups (2). For example, if the remaining value is 1, the allocation control unit 120 determines the numbering memory group #1 corresponding to the remaining value 1 as the memory group to which the write request 2 is to be allocated, and the memory group # to which the write request 2 is determined. assigned to 1.

Accordingly, the data 2 of the write request 2 will be transferred to the data buffer #1 of the memory group #1 to which the write request 2 is allocated and will be buffered in the data buffer #1.

Similarly, the allocation control unit 120 checks the remainder obtained by dividing the logical block address (LBA) of the received write request 3 by the number of memory groups (2). For example, if the remaining value is 0, the allocation control unit 120 determines the numbering memory group #0 corresponding to the remaining value 0 as the memory group to which the write request 3 is to be allocated, and the memory group # to which the write request 3 is determined. assigned to 0.

Accordingly, data 3 of write request 3 will be transferred to data buffer #0 of memory group #0 to which write request 3 is allocated and will be buffered in data buffer #0.

In this way, the allocation control unit 120 checks the remainder of the logical block address (LBA) divided by the number of memory groups (2) for each of the write requests 4, 5, 6.... Accordingly, the allocation control unit 120 writes the numbering memory group (#0 or #1) corresponding to the remaining values (0 or 1) of the write requests 4,5,6... Write requests 4,5,6. .. Determines each memory group to be allocated, and allocates write requests 4, 5, 6... to the determined memory group (#0 or #1).

Therefore, data 4,5,6... of write requests 4,5,6... are data buffers (#0 or #1) of the memory group (#0 or #1) to which write requests 4,5,6... are allocated. It will be transferred to #0 or #1 and will be buffered in the data buffer (#0 or #1).

As such, the allocation control unit 120, for each of the received write requests, that is, write requests 1, 2, 3, 4, 5, 6..., the logical block address (LBA) of the write request and the number of memory groups ( Based on M=2), by distributing and allocating to two or more memory groups, that is, memory group #0 and memory group #1, data 1,2,3,4,5,6... Distributed buffering is performed in data buffer #0 and data buffer #1 corresponding to each of memory group #1.

At this time, the data buffers corresponding to each of the two or more memory groups, for example, data buffer #0 and data buffer #1, receive data transmitted in random write form, that is, each data of the write requests distributed and allocated by the allocation control unit 120 . , it plays a role in converting to sequential write format within the data buffer unit.

The data write control unit 130 performs a data write operation of writing the data buffered in the data buffer to the corresponding memory group, for example, data buffer #0 of memory group #0 and data buffer # of memory group #1. 1 is performed independently.

That is, the data write control unit 130 performs a data write operation of writing data buffered in data buffer #0 to memory group #0, and writing data buffered in data buffer #1 to memory group #1. By performing the data write operation independently, write requests allocated to memory group #0 (eg 1, 3, 5...) and write requests allocated to memory group #1 (eg: 2, 4, 6...) can be processed in parallel in units of memory groups.

Basically, in the data buffer, the transferred data is buffered at the empty leading position in the data buffer.

That is, as in the above example, as write requests 1, 3, 5... are allocated to memory group #0, write requests 1, 3, 5... are transferred to data buffer #0 as each data 1, 3, 5... is buffered at the most empty position in data buffer #0 when it is transferred to data buffer #0.

Of course, as in the example above, as write requests 2, 4, 6 ... are allocated to memory group #1, write requests 2, 4, 6 ... are transferred to data buffer #1, respectively, data 2, 4, 6... is buffered at the most empty position in data buffer #1 when it is transferred to data buffer #1.

Hereinafter, a data write operation independently performed for each data buffer (memory group) will be described in detail.

First, the first embodiment will be described. In the data write operation of the first embodiment, when the data buffer is in a full state, all data buffered in the data buffer and parity information related to all data are transferred to the data buffer. This is an operation to write to the memory group and empty the data buffer.

Hereinafter, for convenience of description, the data write operation according to the first embodiment will be referred to as a data write operation B with reference to FIG. 4 .

That is, the data write control unit 130 independently performs the data write operation B for each of the data buffer #0 of the memory group #0 and the data buffer #1 of the memory group #1.

For convenience of explanation, a process of performing data write operation B on data buffer #0 will be described. The data write control unit 130 checks whether data buffer #0 is in a full state.

As described above, as the write requests 1, 3, 5... each data 1, 3, 5... delivered to data buffer #0 are buffered sequentially in the empty most leading position in data buffer #0, the data Buffer #0 will become full as shown in data write operation B of FIG. 4 at some point.

The data recording control unit 130, when data buffer #0 is in the full state, all data (eg, data 1, 3, 5...) and all data (eg, data 1, 3) buffered in data buffer #0 ,5...) related parity information is recorded in memory group #0 corresponding to data buffer #0, and data buffer #0 is emptied.

Here, the parity information is information including a unique value (eg, a hash value) calculated based on data, and is information used to determine whether data is duplicated or to determine data integrity.

*For example, when data buffer #0 becomes full, the data write control unit 130 includes all data buffered in data buffer #0 (eg, data 1, 3, 5...) and data buffer # A data segment including the calculated parity information for each of data 1, 3, 5... buffered in 0 is configured, and the configured data segment is used in memory chips in memory group #0, that is, memory chips #0, #1, # By writing across 2, #3, #4, all data (eg data1,3,5...) and all data (eg data1,3,5...) buffered in data buffer #0 Parity information related to can be recorded in memory group #0.

Thereafter, the data write control unit 130 empties the data buffer #0.

The data write control unit 130 independently performs the data write operation B on the data buffer #1, separately from the data write operation B on the data buffer #0 as described above.

That is, when data buffer #1 becomes full, the data write control unit 130 controls all data (eg, data 2, 4, 6...) and all data (eg, data 2) buffered in data buffer #1. ,4,6...) related parity information is recorded in memory group #1 corresponding to data buffer #1, and data buffer #1 is emptied.

As such, the data write control unit 130 independently performs a data write operation B for each of the data buffer #0 of the memory group #0 and the data buffer #1 of the memory group #1, thereby assigning the data to the memory group #0. Write requests (eg 1,3,5...) and write requests allocated to memory group #1 (eg 2,4,6...) can be simultaneously processed in parallel in units of memory groups. will do

If the above-described data write operation B is adopted in the memory control apparatus 100 of the present invention, parity information update can be minimized because it is a constant and large unit (data buffer unit), which is advantageous for performance improvement, while sudden power supply This can be somewhat of a disadvantage in terms of reliability as it can lose a lot of data on the DRAM when off.

Meanwhile, referring to the second embodiment, the data writing operation of the second embodiment is an operation of taking out data from the most advanced non-empty position in the data buffer and writing it to a memory group corresponding to the data buffer.

Hereinafter, for convenience of description, the data write operation according to the second embodiment will be described as a data write operation A with reference to FIG. 4 .

That is, the data write control unit 130 independently performs the data write operation A for each of the data buffer #0 of the memory group #0 and the data buffer #1 of the memory group #1.

For convenience of explanation, the process of performing the data write operation A on data buffer #0 will be described. The data write control unit 130 takes out the most advanced non-empty data in data buffer #0 and data buffer #0. It is written to memory group #0 corresponding to

As described above, as the write requests 1, 3, 5... each data 1, 3, 5... delivered to data buffer #0 are buffered sequentially in the empty most leading position in data buffer #0, the data Data1 will be buffered in the most non-empty position in buffer #0.

Accordingly, as shown in the data write operation A of FIG. 4 , the data write control unit 130 takes out the non-empty data from the most advanced position in the data buffer #0, for example, data 1, and writes it to the memory group #0.

After that, data 3 will be buffered at the most non-empty position in data buffer #0.

Accordingly, the data write control unit 130 takes out data from the most advanced non-empty position in the data buffer #0, for example, data 3, and writes it to the memory group #0.

In this way, the data write control unit 130 transmits/buffers write requests 1, 3, 5... to data buffer #0, each of data 1, 3, 5..., within the unit of data buffer #0. Converts only the address through the management of mapping information (not shown) so that it becomes a sequential write format in , and records it in memory group #0.

Of course, the data write control unit 130 may write parity information of the data to be written into the memory group #0 whenever data is retrieved from the data buffer #0 and written to the memory group #0.

As described above, the data write control unit 130 independently performs the data write operation A for data buffer #1, separately from the data write operation A for data buffer #0.

That is, the data write control unit 130 sequentially transfers/buffered write requests 2, 4, 6... to data buffer #1 within the unit of data buffer #1. Only the address is converted through mapping information (not shown) management so that it becomes a write form, and it is recorded in memory group #1.

As such, the data write control unit 130 independently performs the data write operation A for each of the data buffer #0 of the memory group #0 and the data buffer #1 of the memory group #1, thereby assigning the data to the memory group #0. Write requests (eg 1,3,5...) and write requests allocated to memory group #1 (eg 2,4,6...) can be simultaneously processed in parallel in units of memory groups. will do

If the above-mentioned data writing operation A is adopted in the memory control apparatus 100 of the present invention, compared to the case of adopting the above-mentioned data writing operation B, reliability is excellent in an environment where sudden power-off is concerned, while the small unit of Because there are many small writes, the update of parity information increases, which is disadvantageous in terms of performance improvement.

When the above-described data writing operation A is adopted in the memory control apparatus 100 of the present invention, it can be said that it is disadvantageous in terms of performance improvement compared to the case of adopting the above-mentioned data writing operation B, even if it is a small write, the data buffer unit Since it is a sequential write type within the system, the performance will be improved compared to the small write of the existing random write type.

Meanwhile, a third embodiment of the data write operation will be described as follows.

First, each data buffer is divided into two or more partial buffers.

In this case, the partial buffer is related to the chunk size of each memory chip included in the memory group.

More specifically, for example, if the chunk (or strip) size of each memory chip included in memory groups #0 and #1 is 256KB, each data buffer is divided into partial buffers of 256KB unit equal to the chunk size of each memory chip. can be

Accordingly, in the data write operation according to the third embodiment, before the data buffer becomes full, when a specific partial buffer among two or more partial buffers in the data buffer becomes full, the data buffered in the specific partial buffer is transferred to the data buffer Write to the corresponding memory group. And, in the data writing operation according to the third embodiment, when the last partial buffer among the two or more partial buffers becomes full and the data buffer becomes full, the data buffered in the last partial buffer and all data buffered in the data buffer This is an operation of writing related parity information to the memory group and emptying the data buffer.

Hereinafter, for convenience of description, the data writing operation according to the third embodiment will be described by referring to FIG. 4 as data writing operation C. FIG.

That is, the data write control unit 130 independently performs the data write operation C for each of the data buffer #0 of the memory group #0 and the data buffer #1 of the memory group #1.

For convenience of explanation, a process of performing data write operation C on memory group #0 will be described. The data write control unit 130 checks whether data buffer #0 is in a full state.

If the data buffer #0 is not in the full state, the data write control unit 130 determines that the specific partial data of two or more partial buffers in the data buffer #0, for example, the three partial buffers a, b, and c shown in FIG. 4 is in the full state. data buffered in a specific partial buffer is written to memory group #0 corresponding to data buffer #0.

As described above, as the write requests 1, 3, 5... each data 1, 3, 5... delivered to data buffer #0 are buffered sequentially in the empty most leading position in data buffer #0, the data Among the partial buffers a, b, and c in buffer #0, the most advanced partial buffer a will be in the full state.

In this case, since the data write control unit 130 is before the data buffer #0 becomes the full state, it is buffered in the partial buffer a, that is, the partial buffer a, which is in the full state among the partial buffers a, b, and c in the data buffer #0. Write the data to memory group #0. At this time, the data write control unit 130 does not write the parity information of the data buffered in the partial buffer a to the memory group #0.

After that, as described above, each data 1, 3, 5... of write requests 1, 3, 5... delivered to data buffer #0 are buffered in order in the most empty position in data buffer #0. , among partial buffers a, b, and c in data buffer #0, partial buffer b will become full.

In this case, since the data write control unit 130 is before the data buffer #0 becomes the full state, it is buffered in a specific partial buffer, that is, the partial buffer b, which is in the full state among the partial buffers a, b, and c in the data buffer #0. Write the data to memory group #0. At this time, the data write control unit 130 does not write the parity information of the data buffered in the partial buffer b to the memory group #0.

After that, as described above, each data 1, 3, 5... of write requests 1, 3, 5... delivered to data buffer #0 are buffered in order in the most empty position in data buffer #0. , among the partial buffers a, b, and c in data buffer #0, the last partial buffer c will be in the full state, and in this case, data buffer #0 will be in the full state.

In this case, since the data buffer #0 is in the full state, the data write control unit 130 writes the data buffered in the last partial buffer c to the memory group #0, along with all data buffered in the data buffer #0. Parity information calculated for each (all data buffered in partial buffers a, b, and c) can be written to memory group #0.

Thereafter, the data write control unit 130 empties the data buffer #0.

The data write control unit 130 independently performs the data write operation C on the data buffer #1 separately from the data write operation C on the data buffer #0 as described above.

That is, the data write control unit 130 stores the data buffered in the specific partial buffers (eg, a, b) that are in the full state among the partial buffers a, b, and c before the data buffer #1 becomes the full state in the memory group. Write to #1, and when the last partial buffer c among partial buffers a, b, and c becomes full and data buffer #1 becomes full, the data buffered in the last partial buffer c is written to memory group #1 and together with Parity information calculated for each data buffered in data buffer #1 is recorded in memory group #1, and data buffer #1 is emptied.

As such, the data write control unit 130 independently performs a data write operation C on each of the data buffer #0 of the memory group #0 and the data buffer #1 of the memory group #1, thereby assigning the data to the memory group #0. Write requests (eg 1,3,5...) and write requests allocated to memory group #1 (eg 2,4,6...) can be simultaneously processed in parallel in units of memory groups. will do

If the above-described data writing operation C is adopted in the memory control apparatus 100 of the present invention, the advantages of the above-described data writing operation A and data writing operation B can both be taken.

That is, if the above-described data write operation C is adopted in the memory control apparatus 100 of the present invention, the size of data that is feared to be lost when the power is suddenly turned off can be reduced to a size of a partial buffer smaller than the size of the data buffer. Reliability is improved compared to the case of adopting operation B, and performance can be improved by reducing parity information update compared to the case of adopting data writing operation A.

As described above, the memory control device 100 according to the present invention groups a plurality of memory chips in the memory device 10 into two or more memory groups (RAID groups), and each memory group has a data buffer. Against the background of the structure of Alternatively, by performing C) independently for each data buffer of each memory group, as a result, write requests can be processed in parallel in units of memory groups.

Accordingly, the memory control apparatus 100 according to the embodiment of the present invention derives the effect of more efficiently increasing performance and reliability when configuring RAID in a storage system including a flash-based device such as an SSD.

In addition, the memory control apparatus 100 according to the present invention can provide an environmental advantage that can lead to not only capacity expansion but also performance expansion when the capacity of the storage system is expanded by adding an SSD array.

For example, as in the above example, 10 (N=10) memory chips are configured, and the 10 memory chips are grouped into two (M=2) memory group #0 and memory group #1. In a situation, let's say you expand the capacity of the storage system by adding a new SSD array (eg 10 SSDs).

In this case, according to the present invention, a new RAID group, that is, memory groups (#2, #3) is created, and accordingly, the distribution and allocation of write requests to each memory group also needs to be changed in consideration of the new memory group. .

At this time, as described above, the memory control apparatus 100 of the present invention assigns a numbering memory group corresponding to the remainder value obtained by dividing the logical block address (LBA) of the write request by the number (M) of the memory groups, as described above. Since the memory group to which the write request is allocated is determined/allocated, the parameter used to determine the memory group to be allocated, i.e., the number of memory groups (M), is calculated by changing the number to 4, and the write request is distributed and allocated to each memory group. In consideration of the new memory group, it is possible to simply change (hereinafter, write request allocation relocation).

At this time, the memory control apparatus 100 of the present invention may block a request (write, read, etc.) from an upper level until the write request allocation relocation is completed, and while accepting a request (write, read, etc.) from an upper level It is also possible to proceed with write request allocation relocation.

Accordingly, in the memory control apparatus 100 according to the present invention, when a new memory group is created by expanding the capacity of the storage system, the performance of concurrently processing write requests in parallel is also increased by that amount. It is to provide an environmental advantage that can lead to efficient even expansion.

Hereinafter, a method of operating a memory control apparatus according to a preferred embodiment of the present invention will be described with reference to FIG. 5 . For convenience of description, reference numerals in FIGS. 1 to 4 will be referred to.

In the method of operating the memory control device 100 according to the present invention, a plurality of memory chips (#0, #1, #2...#N-1) constituting the memory device 10, for example, N SSDs, Grouping into two or more memory groups (S100).

At this time, in the present invention, as shown in FIG. 3, in each of two or more memory groups, that is, M memory groups (#0...#M-1), there is a data buffer in which data to be written into the memory group is buffered. They are provided to correspond to each other.

Accordingly, the data buffer #0 corresponds to the memory group #0, the data buffer #1 to the memory group #1, ... The data buffer #M is provided to correspond to the memory group #M.

Hereinafter, for convenience of explanation, 10 (N=10) memory chips are configured in the memory device 10, and in step S100, 10 memory chips are added to two (M=2) memory groups #0, An example of grouping into memory group #1 will be described.

In the operating method of the memory control device 100 according to the present invention, a write request for attempting a write operation on the memory device 10 is received from the file system 200 (S110).

For example, in the operating method of the memory control device 100 according to the present invention, write requests, that is, each write request 1, 2, 3, 4, 5 received in the order in which a write operation is attempted with respect to the memory device 10 ,6... can be received.

In the method of operating the memory control apparatus 100 according to the present invention, for each of the received write requests, two or more memory groups based on the logical block address (LBA) of the write request and the number of memory groups (M=2) That is, a memory group to be allocated among memory group #0 and memory group #1 is determined, and a corresponding write request is allocated to the determined memory group (S120).

For example, in the method of operating the memory control apparatus 100 according to the present invention, the remainder obtained by dividing the logical block address (LBA) of the received write request 1 by the number of memory groups (2) is checked. For example, if the remaining value is 0, the method of operating the memory control apparatus 100 according to the present invention determines the numbering memory group #0 corresponding to the remaining value 0 as the memory group to which the write request 1 is to be allocated, The write request 1 is allocated to the determined memory group #0 (S120).

Accordingly, the data 1 of the write request 1 will be transferred to the data buffer # 0 of the memory group # 0 to which the write request 1 is allocated and will be buffered in the data buffer # 0 ( S130 ).

Similarly, in the method of operating the memory control apparatus 100 according to the present invention, a remainder value obtained by dividing the logical block address (LBA) of the received write request 2 by the number of memory groups (2) is checked. For example, if the remaining value is 1, the method of operating the memory control apparatus 100 according to the present invention determines the numbering memory group #1 corresponding to the remaining value 1 as the memory group to which the write request 2 is to be allocated, The write request 2 is allocated to the determined memory group #1 (S120).

Accordingly, the data 2 of the write request 2 will be transferred to the data buffer #1 of the memory group #1 to which the write request 2 is allocated and will be buffered in the data buffer #1 (S130).

Similarly, in the method of operating the memory control apparatus 100 according to the present invention, the remainder obtained by dividing the logical block address (LBA) of the received write request 3 by the number of memory groups (2) is checked. For example, if the remaining value is 0, the method of operating the memory control apparatus 100 according to the present invention determines the numbering memory group #0 corresponding to the remaining value 0 as the memory group to which the write request 3 is to be allocated, Write request 3 is allocated to the determined memory group #0 (S120).

Accordingly, the data 3 of the write request 3 will be transferred to the data buffer # 0 of the memory group # 0 to which the write request 3 is allocated and will be buffered in the data buffer # 0 ( S130 ).

In this way, the operation method of the memory control apparatus 100 according to the present invention is the remainder of dividing the logical block address (LBA) by the number of memory groups (2) for each of the write requests 4, 5, 6... Check the value. Accordingly, the method of operation of the memory control device 100 according to the present invention is a numbering memory group (#0 or #1) corresponding to the remaining values (0 or 1) of write requests 4, 5, 6... Each of the write requests 4, 5, 6... is determined as a memory group to be allocated, and each of the write requests 4, 5, 6... is allocated to the determined memory group (#0 or #1) (S120).

Therefore, data 4,5,6... of write requests 4,5,6... are data buffers (#0 or #1) of the memory group (#0 or #1) to which write requests 4,5,6... are allocated. It will be transferred to #0 or #1 and buffered in the data buffer (#0 or #1) (S130).

As such, the method of operation of the memory control apparatus 100 according to the present invention provides a logical block address ( LBA) and data 1,2,3,4,5,6 of write requests by distributed allocation to two or more memory groups, that is, memory group #0 and memory group #1, based on the number of memory groups (M=2). .. is distributed buffered in data buffer #0 and data buffer #1 corresponding to memory group #0 and memory group #1, respectively.

In the method of operating the memory control apparatus 100 according to the present invention, a data write operation of writing data buffered in a data buffer to a corresponding memory group is performed in two or more memory groups, that is, data buffer #0 of memory group #0, memory It is independently performed for each data buffer #1 of group #1 (S140).

That is, in the method of operating the memory control apparatus 100 according to the present invention, the above-described data write operation (A or B or C) independently, write requests allocated to memory group #0 (eg 1,3,5...) and write requests allocated to memory group #1 (eg 2,4,6) ...) can be simultaneously processed in parallel in units of memory groups.

As described above, in the method of operating the memory control device 100 according to the present invention according to the present invention, a plurality of memory chips in the memory device 10 are grouped into two or more memory groups (RAID groups), and each memory Against the background of a structure having a data buffer for each group, the write requests received for the memory device 10 are distributed to each memory group so that the data of the write requests are distributed buffered in the data buffer of each memory group, By independently performing a data write operation (A, B, or C) for each data buffer of each memory group, as a result, write requests can be processed in parallel in units of memory groups.

Accordingly, the method of operating the memory control apparatus according to the embodiment of the present invention derives the effect of more efficiently increasing performance and reliability when configuring RAID in a storage system including a flash-based device such as an SSD.

The method of operating a memory control apparatus according to an embodiment of the present invention may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the present invention, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

Although the present invention has been described in detail with reference to preferred embodiments so far, the present invention is not limited to the above-described embodiments, and without departing from the gist of the present invention as claimed in the following claims, the technical field to which the present invention pertains It will be said that the technical idea of the present invention extends to a range where various modifications or corrections are possible by anyone having ordinary knowledge in the present invention.

According to the memory control apparatus and the operating method of the memory control apparatus according to the present invention, in a storage system composed of a flash-based device such as an SSD, performance and reliability can be more efficiently increased during RAID configuration, In addition, it is an invention with industrial applicability because the possibility of marketing or business of the applied device, not only the use of the related technology, is sufficient as well as the extent to which it can be clearly implemented in reality.

10: memory device
100 : memory control device
110: grouping unit 120: allocation control unit
130: data recording control unit
200: file system/application

Claims (17)

a grouping unit for grouping a plurality of memory chips constituting the memory device into two or more memory groups;
By distributing and allocating write requests received to the memory device to the two or more memory groups based on a logical block address (LBA) of each of the write requests and the number of memory groups, the data of the write requests is an allocation control unit for distributed buffering in data buffers corresponding to the two or more memory groups; and
A data write operation for writing data buffered in a data buffer across memory chips included in a corresponding memory group is independently performed for each data buffer corresponding to each of the two or more memory groups, so that the write requests are performed in units of memory groups characterized in that it includes a data recording control unit that allows parallel processing with
the data buffer includes a plurality of partial buffers and the partial buffer stores a plurality of data;
The data write controller is configured to write buffered data to a memory group corresponding to the partial buffer that is full of data when the data buffer is full of data in units of partial buffers.
The method of claim 1,
The allocation control unit,
and allocating each of the write requests to a numbering memory group corresponding to a remainder obtained by dividing the logical block address by the number of memory groups, thereby distributing and allocating the write requests to the two or more memory groups. .
The method of claim 1,
In the data buffer, the data to be transferred is buffered at an empty most leading position in the data buffer.
The method of claim 1,
The data write operation is
When the data buffer is in the full state, all data buffered in the data buffer and parity information related to all data are written to a memory group corresponding to the data buffer, and the data buffer is emptied. memory control device.
According to claim 1,
The partial buffer is associated with a chunk size of each memory chip included in the memory group.
The method of claim 1,
In the data buffer, the transferred data is buffered in the empty most leading position in the data buffer,
The data write operation is
The memory control apparatus according to claim 1, wherein the operation of extracting data from the earliest non-empty position in the data buffer and writing the data to a memory group corresponding to the data buffer.
The method of claim 1,
the number of the memory groups is smaller than the number of the plurality of memory chips constituting the memory device;
memory control device.
8. The method of claim 7,
When the grouping unit changes the number of memory groups,
The allocation control unit relocates the distributed allocated write requests,
memory control device.
a grouping step of grouping a plurality of memory chips constituting the memory device into two or more memory groups;
By distributing and allocating write requests received to the memory device to the two or more memory groups based on a logical block address (LBA) and the number of memory groups of each of the write requests, the data of the write requests is an allocation control step of distributing buffering in a data buffer corresponding to each of the two or more memory groups and including a plurality of partial buffers; and
A data write operation for writing data buffered in a data buffer across memory chips included in a corresponding memory group is independently performed for each data buffer corresponding to each of the two or more memory groups, so that the write requests are performed in units of memory groups characterized in that it includes a data recording control step to enable parallel processing with
The partial buffer stores a plurality of data,
The data write control step includes writing the buffered data to a memory group corresponding to the partial buffer full of data when the data buffer is full in units of partial buffers.
10. The method of claim 9,
The allocation control step is
and allocating each of the write requests to a numbering memory group corresponding to a remainder obtained by dividing the logical block address by the number of memory groups, thereby distributing and allocating the write requests to the two or more memory groups. how it works.
10. The method of claim 9,
The method of operating a memory control device, characterized in that the data buffer is buffered at an empty most leading position in the data buffer.
10. The method of claim 9,
The data write operation is
When the data buffer is in the full state, all data buffered in the data buffer and parity information related to all data are written to a memory group corresponding to the data buffer, and the data buffer is emptied. How to operate a memory control device.
a plurality of flash memory devices;
a data buffer comprising a plurality of partial buffers;
grouping the plurality of flash memory devices into two or more memory groups, allocating the plurality of partial buffers to the two or more memory groups, respectively, and logical block addresses (LBAs) included in write requests to the plurality of flash memory devices : Distributes write data corresponding to the write requests in response to Logical Block Address) to the plurality of partial buffers, and when the distributed write data in at least one of the plurality of partial buffers is full, the two or more A memory control device for storing the distributed write data in a memory group corresponding to a partial buffer filled with the distributed write data among the memory groups
A storage system comprising a.
14. The method of claim 13,
The memory control device
emptying the full partial buffer when the distributed write data is stored in a memory group corresponding to the partial buffer full of the distributed write data;
storage system.
14. The method of claim 13,
The memory control device
Storing the write data distributed in the plurality of partial buffers respectively allocated to the two or more memory groups in the two or more memory groups in parallel for the two or more memory groups,
storage system.
14. The method of claim 13,
the number of the memory groups is smaller than the number of the plurality of flash memory devices;
storage system.
14. The method of claim 13,
The memory control device
After changing the number of memory groups, relocating the write requests distributed in the plurality of partial buffers,
storage system.

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