KR102339943B1 - Apparatus and method for generting physical unclonable function by modifiying photo mask of semiconductor process - Google Patents

Abstract

A method for generating a PUF by causing an unpredictable partial process failure in a semiconductor process is provided. Even when the semiconductor design rule is not violated in the design stage, the second mask pattern in which the size and/or shape of at least one mask window included in the designed first mask pattern is distorted may be printed. In addition, the PUF may be generated by performing photolithography using a photomask including the printed second mask pattern.

Description

TECHNICAL FIELD [0002] A method and apparatus for generating a PFC by deforming a photomask of a semiconductor process

It relates to the field of semiconductor processing, and more specifically, relates to a method of generating a PUF by changing a photomask used in photo lithography of a semiconductor process.

A Physically Unclonable Function (PUF) may provide an unpredictable digital value. Although individual PUFs are given an exact manufacturing process and are manufactured in the same design and process, the digital values provided by the individual PUFs are different.

Therefore, it may be referred to as POWF (Physical One-Way Function practically impossible to be duplicated) that cannot be duplicated.

This characteristic of the PUF may be used to generate an encryption key for security and/or authentication. For example, PUF may be used to provide a unique key to distinguish devices from one another.

In Korean Patent Registration No. 10-1139630 (hereinafter the '630 patent), a method for implementing PUF has been proposed. The '630 patent proposes a method in which the generation of an inter-layer contact or a via between conductive layers of a semiconductor is determined probabilistically by using the process variation of the semiconductor. became

According to one side, when the first mask pattern corresponding to the semiconductor design is input, printing a second mask pattern obtained by deforming at least a portion of the first mask pattern; and performing photolithography using a photomask including the printed second mask pattern, wherein the second mask pattern has a probability of forming a plurality of inter-layer contacts or vias included in the semiconductor design. A semiconductor manufacturing method is provided, which is a pattern generated by deforming the first mask pattern so that at least some of the plurality of inter-layer contacts or vias are not formed.

According to an embodiment, the second mask pattern is a pattern generated by deforming or distorting at least one of a size and a shape of at least one mask window included in the first mask pattern.

According to an embodiment, the plurality of inter-layer contacts or vias is formed with a first critical yield or more by performing photolithography using the first mask pattern, and is formed using the second mask pattern in photolithography using the second mask pattern. It is formed to be greater than or equal to a second critical yield and less than or equal to a third critical yield by performing, the third critical yield may be smaller than the first critical yield, and the second critical yield may be smaller than the third critical yield.

Meanwhile, according to an embodiment, the second mask pattern is a pattern in which the size of the at least one mask window is scaled down by applying a scale factor smaller than 1 to at least one mask window included in the first mask pattern. can be

According to another embodiment, the second mask pattern may be a pattern in which the shape of the at least one mask window is distorted by deforming the shape of at least one mask window included in the first mask pattern in at least one direction. may be

According to another embodiment, the second mask pattern may include omitting optical proximity correction (OPC) or applying a modified OPC to at least one mask window included in the first mask pattern. It may be a pattern in which the shape of at least one mask window is distorted.

According to another aspect, the method comprising: receiving a first mask pattern designed to form a plurality of inter-layer contacts or vias between semiconductor conductive layers; and generating a second mask pattern by distorting the first mask pattern so that at least a portion of the plurality of inter-layer contacts or vias is not implanted in a stochastic manner, wherein photolithography is performed using the second mask pattern. When performing the method, a difference in a ratio between non-formed and formed short-circuiting between the semiconductor conductive layer among the plurality of inter-layer contacts or vias becomes less than or equal to a first threshold.

According to an embodiment, the second mask pattern may be a pattern in which the size of the at least one mask window is scaled down by applying a scale factor smaller than 1 to at least one mask window included in the first mask pattern. have.

According to another exemplary embodiment, in the second mask pattern, the shape of the at least one mask window is distorted by deforming the shape of at least one mask window included in the first mask pattern in at least one direction. can be

Further, according to another exemplary embodiment, the second mask pattern may be obtained by omitting OPC (Optical Proximity Correction) or applying a modified OPC to at least one mask window included in the first mask pattern. It may be a pattern in which the shape of the at least one mask window is distorted.

According to another aspect, receiving a first mask pattern associated with an implantation process of N inter-layer contacts designed to short-circuit between semiconductor conductive layers, where N is a natural number, and the first mask pattern includes the N mask windows corresponding to each of the N inter-layer contacts are included; and deforming or distorting at least one of the shapes and sizes of the N mask windows in the first mask pattern to generate a second mask pattern, wherein the second mask pattern is used to form a second mask pattern between the conductive layers. In the case of performing the implantation process of the N inter-layer contacts, it is probabilistically determined whether each of the designed N inter-layer contacts short-circuit between the conductive layers. do.

Here, the deformation or distortion is performed such that a difference between a ratio of short-circuiting between the conductive layers and a ratio of non-short-circuiting between the conductive layers among the designed N inter-layer contacts is less than a first threshold value of the N mask windows. It may be to change at least one of shape and size.

According to another aspect, when a first mask pattern designed to implant a plurality of inter-layer contacts between semiconductor conductive layers is received, the second mask pattern is not implanted probabilistically for at least some of the plurality of inter-layer contacts. a processing unit configured to deform or distort the first mask pattern to generate a second mask pattern; and a printing unit for printing the second mask pattern, wherein, when photolithography is performed, the second mask pattern is implanted with an inter-layer contact that is not implanted among the plurality of inter-layer contacts and the semiconductor conductivity Generating a semiconductor mask, which is a pattern in which at least one of the size and shape of at least a portion of the mask window included in the first mask pattern is deformed or distorted so that a difference in the ratio of inter-layer contacts that short-circuit between layers is less than or equal to a first threshold A device is provided.

According to an embodiment, the processing unit applies a scale factor smaller than 1 to at least one mask window included in the first mask pattern to scale-down the size of the at least one mask window to the second mask. create as a pattern.

According to another exemplary embodiment, the processing unit may transform the shape of at least one mask window included in the first mask pattern in at least one direction to convert the shape of the at least one mask window into the second pattern. It can be created as a mask pattern.

According to another embodiment, the processing unit may omit or apply a modified OPC (Optical Proximity Correction) to at least one mask window included in the first mask pattern to obtain the at least one mask window. A pattern in which the shape of the mask window is distorted may be generated as the second mask pattern.

1 is a flowchart illustrating a method of manufacturing a semiconductor according to an exemplary embodiment.
FIG. 2 is a conceptual diagram illustrating a process in which a PUF may be generated by distortion of a mask window size in a method of manufacturing a semiconductor according to an exemplary embodiment.
3 is a conceptual diagram for explaining a process of probabilistically determining implant success of an inter-layer contact by distorting a mask window size according to an embodiment.
4 is a graph for explaining a degree to which a mask window size is distorted in order to adjust an implant success probability of an inter-layer contact according to an embodiment.
5 illustrates a mask pattern design corresponding to a plurality of inter-layer contacts designed according to an exemplary embodiment.
6 illustrates a first mask pattern corresponding to the mask pattern design of FIG. 5 according to an exemplary embodiment.
7 illustrates a second mask pattern in which a size of a mask window included in the first mask pattern of FIG. 6 is distorted, according to an exemplary embodiment.
8 illustrates distorted mask windows in accordance with various embodiments.
9 illustrates an apparatus for generating a semiconductor mask according to an embodiment.

Hereinafter, some embodiments will be described in detail with reference to the accompanying drawings. However, it is not limited or limited by these embodiments. Like reference numerals in each figure indicate like elements.

1 is a flowchart illustrating a method of manufacturing a semiconductor according to an exemplary embodiment.

In operation 110 , a first mask pattern according to a semiconductor design is received. The first mask pattern may be a photo mask pattern for forming a plurality of inter-layer contacts (also referred to as 'implants') designed to short-circuit between conductive layers of a semiconductor.

Here, and throughout this specification, the inter-layer contact means any type of conductive element that short-circuits between nodes made with conductive material. For example, a via implanted between conductive layers is an exemplary form that should be understood to be included in the inter-layer contact described herein.

Accordingly, “inter-layer contact” should be understood to include any form capable of shorting between conductive layers in a semiconductor circuit, and should not be limited to some configurations illustratively described herein.

According to an embodiment, the first mask pattern may include N mask windows associated with N inter-layer contacts implanted between the semiconductor conductive layers, where N is a natural number. These N mask windows may be a part of the first mask pattern. This part may be a part corresponding to an area for PUF generation among inter-layer contacts related to the process.

The holes or windows of the N masks included in the first mask pattern may be for a semiconductor process, for example, a photolithography process.

Here, the first mask pattern may ensure that the N inter-layer contacts are successfully implanted between the semiconductor conductive layers by a conventional process according to a semiconductor design.

Accordingly, when the N inter-layer contacts are implanted using a photo mask generated using the first mask pattern, each of the N inter-layer contacts may short-circuit between the semiconductor conductive layers.

According to an embodiment, in step 120 , the size and/or shape of the N mask windows included in the first mask pattern is modified or distorted to form a second mask pattern. create

Illustratively, but not limitedly, the deformation or distortion may be to change the size of each of the N mask windows included in the first mask pattern to be small. Accordingly, the size of each of the N mask windows included in the second mask pattern may be smaller than the size of each of the N mask windows included in the first mask pattern.

Then, the second mask pattern is printed in step 130 to generate a photomask to be used for photolithography in the process according to an embodiment. The printing may be understood as physically forming a chromium pattern corresponding to the second mask pattern on glass for generating a mask.

Then, when photolithography is performed in step 140 , at least some random among the N inter-layer contacts involved in PUF generation may not short-circuit between the semiconductor conductive layers.

In a typical semiconductor process, this result can be accepted as a process failure. In addition, since some of the designed inter-layer contacts are not normally implanted, the semiconductor may be treated as defective.

However, according to one embodiment, as described above, some of the random and unpredictable inter-layer contacts fail to short-circuit between the semiconductor conductive layers (failure in a typical semiconductor manufacturing process). A recognized phenomenon) is used to generate a PUF.

Such a random process failure, for example, is that some of the N mask windows are not sufficiently deposited on the inter-layer in a subsequent photolithography process by the photoresist (also called 'PR') to the inter-layer layer. This may be due to the fact that the inter-layer is not etched because it is not developed.

In addition, even if the PR phenomenon occurs, it may be due to the fact that the entire inter-layer cannot be etched due to the small area exposed to the inter-layer to the etching solution during the etching process.

As described above, by deforming or distorting the size and/or shape of the mask window in a process step, some of the N inter-layer contacts fail to short-circuit between the semiconductor conductive layers, and the N inter-layer contacts Which of these will fall into this category cannot be predicted in advance. This guarantees the randomness of the N-bit digital value generated by the PUF.

Meanwhile, after a process is performed, a specific portion of the N inter-layer contacts that is not short-circuited between the semiconductor conductive layers is maintained unless a separate process is performed. Accordingly, the time-invariance of the N-bit digital value generated by the PUF can be guaranteed to a high level.

Furthermore, even if a plurality of PUFs are generated by performing a process a plurality of times using the same second mask pattern, which of the N inter-layer contacts fails a normal implant may be different for each semiconductor.

Accordingly, even if the second mask pattern is the same, since different digital values are generated, the characteristic of the PUF, that is, physical replication impossibility, may be satisfied.

Accordingly, according to embodiments, by generating N mask windows formed on the glass in the mask manufacturing step as a second design pattern modified from an original design corresponding to the first mask pattern, a subsequent photolithography process is performed After the process, inter-layer contacts are not implanted in random parts. And, the PUF is generated by the randomness of the success or failure of implantation of the N inter-layer contacts.

Mask pattern distortion according to various embodiments will be described in more detail below.

FIG. 2 is a conceptual diagram illustrating a process in which a PUF may be generated by distortion of a mask window size in a method of manufacturing a semiconductor according to an exemplary embodiment.

Four mask window groups 210 , 220 , 230 and 240 are shown for implanting an inter-layer contact, such as a via, into the conductive layer 201 and the conductive layer 202 in a semiconductor manufacturing process.

The mask windows included in the group 210 may be mask windows included in the first mask pattern for a typical photolithography process.

When a photolithography process is performed by forming mask windows included in the group 210 on a photomask, all three inter-layer contacts are successfully implanted. Accordingly, the conductive layer 201 and the conductive layer 202 are both shorted at each node. In this case, the digital value generated by the three nodes may be “000”.

Meanwhile, the mask windows included in the group 240 are extremely reduced in size of the mask windows included in the group 210 .

When a photolithography process is performed by printing the mask windows included in the group 240 on a photomask, all three inter-layer contacts were not successfully implanted. In the case of group 240, in some cases, the PR is not fully developed to the inter-layer layer during the development process, so the inter-layer layer may not be exposed to the etching solution. The area of the inter-layer exposed to the solution may be too small to etch the entire inter-layer.

Thus, in the case of group 240, the conductive layer 201 and the conductive layer 202 are both short-circuited at each node. In this case, the digital value generated by the three nodes may be “111”.

Then, select a size B or size C, which is a value between the mask window size A of the group 210 that results in successful implantation, and the mask window size D of the group 240 that results in both successful implantation and failure. Then, it can be expected that some inter-layer contacts that are determined probabilistically and cannot be predicted in advance are successfully implanted, and other inter-layer contacts are not normally implanted.

The mask window size B of the group 220 may be selected in this way.

When the photolithography process is performed by forming the mask windows included in the group 220 on the photomask, two of the three inter-layer contacts were successfully implanted, but the other one was not normally implanted. Accordingly, the conductive layer 201 and the conductive layer 202 are short-circuited at some nodes and not short-circuited at other nodes. As shown, the digital value generated by the three nodes in this case may be “001”.

Here, the mask windows included in the mask window of the group 220 may be mask windows included in the second mask pattern according to an embodiment.

Also, the mask window size C of the group 230 may be smaller than the size B. In this case, in one node, the PR was developed up to the inter-layer layer, but the area of the inter-layer exposed to the etching solution was too small to etch the entire inter-layer. Since the layer was not fully developed, the inter-layer layer was not exposed to the etching solution, and the conductive layer 201 and the conductive layer 202 were short-circuited due to etching at another node. As shown, the digital value generated by the three nodes in this case may be “110”.

By changing the mask window size and/or shape in this way, some random inter-layer contacts that cannot be predicted in advance are successfully implanted between the conductive layers 201 and 202, and other inter-layer contacts are not successfully implanted. and thus a PUF can be generated.

The effect of such mask window size distortion in the photolithography process will be described in more detail with reference to FIG. 3 .

3 is a conceptual diagram for explaining a process of probabilistically determining implant success of an inter-layer contact by distorting a mask window size according to an embodiment.

In accordance with the design 301 for creating one exemplary inter-layer contact, a mask window 310 is created on the photo mask in a typical normal process.

For example, in a typical process, OPC (Optical Proximity Correction) may be performed, and the mask window 310 performs OPC to develop a photo-resist (PR) in the same manner as in the design 301 . It has a size and shape that makes it Since OPC is well known to semiconductor process engineers, a detailed description thereof will be omitted.

The mask window 310 may be included in the first mask pattern, and the PR is developed to a sufficient size to develop the PR on the interlayer as in the shape 311 . Then, the PR development and etching of PR included in the photolithography process is in the form of a figure 312, and in this case, all inter-layer contacts can be successfully implanted.

Meanwhile, the mask window 330 is an extremely reduced size of the mask window 310 included in the first mask pattern, and the PR is developed like the shape 331 . Then, the PR developing and etching result is in the form of figure 332, in which case the inter-layer contact can most likely fail.

According to an embodiment, a second mask pattern is generated by selecting the mask window 320 . Using the mask window 320, the PR is developed into a distorted shape 321 having a size smaller than normal. The PR development and etching result is then in the form of figure 322 . According to an embodiment, in this case, the mask window 320 may be created such that the probability of successful implantation of the inter-layer contact is about 50%.

For example, if the size of the normal mask window 310 in the exemplary 0.18 micron (um) complementary metal-oxide-semiconductor (CMOS) process is 0.25 microns (um), the second mask pattern is The included mask window 320 may have a size of 0.19 microns.

Of course, the above exemplary figures are merely exemplary, which are different for each semiconductor processing company and can be changed according to various other process factors. Therefore, according to the above embodiment, the probability of short circuit between conductive layers due to successful implantation of the inter-layer being about 50% can be determined by making and testing mask windows of various sizes. The size of may be used for mask window deformation according to embodiments.

On the other hand, as described with reference to the group 230 or the group 240 of FIG. 2, in some cases, the PR development process is incompletely performed because the mask window size is too small, so that the PR is not fully developed to the inter-layer layer. In some cases it is not (not shown). In this case, unlike the figure 322 , there may be a case where the inter-layer layer is not etched at all.

4 is a graph for explaining a degree to which a mask window size is distorted in order to adjust an implant success probability of an inter-layer contact according to an embodiment.

It can be seen from the graph that as the size of the mask window increases, the probability of successful implantation of the inter-layer contact is close to 1. In a typical semiconductor process, the mask window size may be set to Sd in order to be implanted with a yield greater than or equal to a first threshold yield.

In addition, Sm is the theoretical mask window size at which the probability that the inter-layer contact will be successfully implanted is 0.5. Finding Sm is difficult.

Therefore, according to an embodiment, the mask window size Sx is selected so that the probability of successful implantation of the inter-layer is sufficiently close to 0.5 according to a specific experiment.

In this case, Sx may be determined to be within a certain range where the probability of successful implantation, that is, the yield is near 0.5. Exemplarily, the actual Sx value may be determined as any value between the window size value at which the implant success probability becomes 0.45, the second threshold yield, and the window size value, at which the implant success probability becomes 0.55, the third threshold yield. .

On the other hand, even if the implant success probability determines the mask window size Sx value close to 0.5 by experiment, the actual implant success rate after the process is finished may not be 50%. This may be the effect of various process factors.

According to an embodiment, after the N inter-layer contacts are always generated according to the embodiment, the generated N inter-layer contacts are grouped to divide k groups, where k is a natural number.

Then, N/k inter-layer contacts may be included in individual groups. In addition, by comparing N/k-bit digital values generated by each of the two groups, a 1-bit digital value representing the two groups may be determined as “0” or “1”.

This may be understood as a process of balancing between digital values “0” and “1” in the PUF to be actually used. Such balancing may be performed by various methods, and is not limited to the above exemplary description.

Hereinafter, examples of an inter-layer contact design for implementing a PUF, a first mask pattern by a conventional process, and a second mask pattern according to embodiments will be described in detail with reference to FIGS. 5 to 8 .

5 illustrates a mask pattern design corresponding to a plurality of inter-layer contacts designed according to an exemplary embodiment.

The semiconductor design 510 may include a portion 520 constituting the PUF. The portion 520 constituting the PUF may be hidden in a general integrated circuit (Integrated Circuit), and even if the semiconductor integrated circuit is analyzed by X-Ray or the like according to this embodiment, the portion 520 constituting the PUF It is possible to make it difficult to find where this is.

For example, in the portion 520 constituting the PUF, 16 inter-layer contacts 521 are designed. According to this design, a typical first mask pattern for implanting 16 inter-layers by a photolithography process is shown in FIG. 6 .

6 illustrates a first mask pattern 610 corresponding to the mask pattern design of FIG. 5 according to an exemplary embodiment.

Sixteen mask windows 620 corresponding to each of the sixteen inter-layer designs shown in FIG. 5 are shown. For example, OPC is applied to each of the mask windows 620 .

According to an embodiment, a second mask pattern obtained by changing the first mask pattern 610 is generated. An example of the second mask pattern is shown in FIG. 7 .

7 illustrates a second mask pattern 710 in which the size of a mask window included in the first mask pattern of FIG. 6 is distorted according to an exemplary embodiment.

The 16 mask windows 720 included in the second mask pattern 710 are distorted in size and/or shape of each of the 16 mask windows 620 included in the first mask pattern 610 . According to an embodiment, the distortion may be down-scaling the size of each of the mask windows 620 . Even in this embodiment, only the mask windows corresponding to the portion 520 of FIG. 5 for configuring the PUF may be subjected to such downscaling, and the other portions (not shown) that are not related to the PUF configuration proceed as a normal process. can

In addition, this downscaling is only one embodiment of the distortion, and the distortion may include other various embodiments.

8 shows distorted mask windows 830 in accordance with various embodiments.

Examples of distorting the mask window 820 according to a conventional process corresponding to the design 810 of one inter-layer in various ways are exemplarily shown in the mask windows 830 . It is apparent to those skilled in the art that there may be various other embodiments in addition to the exemplary forms included in the mask windows 830 .

According to an embodiment, as shown in the example of FIG. 7 , a mask window 831 obtained by downscaling the mask window 820 may be generated.

According to another embodiment, the mask window 832 in which only the size of the mask window 820 in at least one direction is reduced may be generated.

According to another embodiment, the mask window 833 or the mask window 834 in which both the size and shape of the mask window 820 are changed may be generated.

According to another embodiment, the mask window 835 may be generated by omitting the OPC to be applied to the mask window 820 .

According to another embodiment, the mask window 836 may be generated by reversely applying the OPC pattern to be applied to the mask window 820 .

According to another embodiment, the mask window 837 may be created by inserting a grid pattern into the mask window 820 to reduce the window area.

According to another embodiment, the mask window 837 may be generated by removing at least a portion of the mask window 820 .

As noted above, the mask windows 830 are understood to include any other variations that cause random and stochastic process failure, such that the probability that the inter-layer is successfully implanted between the semiconductor conductive layers approaches 50%. should be

If a photomask is generated by equally patterning N deformed mask windows selected among these embodiments, a PUF may be generated by making a modification in a process without violating a semiconductor design rule in a design stage.

Therefore, a separate additional manufacturing cost is not incurred, a conventional semiconductor process can be used as it is, and a PUF strong against external attacks can be manufactured because it is physically impossible to replicate.

9 illustrates an apparatus 900 for generating a semiconductor mask according to an exemplary embodiment.

According to an embodiment, the design 510 of FIG. 5 or the first mask pattern of FIG. 6 is input to the processing unit 910 of the apparatus 900 .

Then, the processing unit generates the second mask pattern by distorting the size and/or shape of the N mask windows included in the first mask pattern.

Various embodiments of such distortion are as described above with reference to FIGS. 5 to 8 .

When the second mask pattern is generated by the processing unit 910 , the printing unit 920 prints the second mask pattern to generate a photomask to be used in a photolithography process.

When a conventional photolithography process is performed using the photomask, at least some of the N inter-layer contacts according to the original design cannot short-circuit between the semiconductor conductive layers as described above.

Which of the N inter-layer contacts has been successfully implanted can be identified using a read transistor (not shown), and a PUF generating an N-bit digital value can be generated through this value. .

Furthermore, various post-processing for balancing between “0” and “1” of the digital value generated as described above may be added.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (13)

When a mask pattern designed according to a semiconductor design rule is input, OPC is omitted for at least one mask window included in the mask pattern, or the shape of the at least one mask window is modified by applying a modified OPC. printing a photomask; and
performing photolithography using the printed photomask to randomly form a plurality of inter-layer contacts or vias;
including,
The deformed at least one mask window,
a difference between a probability that an inter-layer contact or a via formed using the photomask short-circuits the conductive layers and a probability that the inter-layer contact cannot short-circuit falls within a predetermined range;
and a PUF value is determined based on the plurality of randomly formed inter-layer contacts or vias. According to claim 1,
The photomask is
The semiconductor manufacturing method is generated by deforming or distorting at least one of a size and a shape of at least one mask window included in the mask pattern. According to claim 1,
The plurality of inter-layer contacts or vias include:
A first critical yield or more is formed by performing photolithography using the mask pattern,
By performing photolithography using the photomask, the second critical yield or more and the third critical yield or less are formed,
wherein the third critical yield is less than the first critical yield, and the second critical yield is less than the third critical yield. According to claim 1,
The photomask scales down the size of the at least one mask window by applying a scale factor smaller than 1 to the at least one mask window included in the mask pattern. According to claim 1,
The photomask may deform the shape of the at least one mask window by deforming the shape of the at least one mask window included in the mask pattern in at least one direction. receiving a mask pattern designed to form a plurality of inter-layer contacts or vias between semiconductor conductive layers; and
generating a photomask by deforming the mask pattern so that at least some of the plurality of inter-layer contacts or vias are not implanted in a stochastic manner;
including,
When photolithography is performed using the photomask, a difference in a ratio between non-formed and formed short-circuiting between the semiconductor conductive layer among the plurality of inter-layer contacts or vias is less than or equal to a first threshold,
The photomask is formed by modifying the shape of the at least one mask window by omitting OPC (Optical Proximity Correction) or applying a modified OPC to at least one mask window included in the mask pattern, and ,
The deformed at least one mask window,
a difference between a probability that an inter-layer contact or a via formed using the photomask short-circuits the conductive layers and a probability that the inter-layer contact fails to short-circuit within a predetermined range;
and a PUF value is determined based on the formed plurality of inter-layer contacts or vias. 7. The method of claim 6,
The photomask scales down the size of the at least one mask window by applying a scale factor smaller than 1 to the at least one mask window included in the mask pattern. 7. The method of claim 6,
The photomask may deform the shape of the at least one mask window by deforming the shape of the at least one mask window included in the mask pattern in at least one direction. receiving a mask pattern associated with an implantation process of N inter-layer contacts designed to short-circuit between semiconductor conductive layers, where N is a natural number, and the mask pattern corresponds to each of the N inter-layer contacts contains N mask windows -; and
generating a photomask by omitting OPC or modifying the shape of the N mask windows by applying a modified OPC to the N mask windows in the mask pattern
including,
When the implantation process of the N inter-layer contacts between the conductive layers is performed using the photomask, whether each of the designed N inter-layer contacts short-circuits between the conductive layers is determined. determined probabilistically,
Each of the modified N mask windows,
a difference between a probability that an inter-layer contact or a via formed using the photomask short-circuits the conductive layers and a probability that the inter-layer contact fails to short-circuit within a predetermined range;
and a PUF value is determined based on the formed inter-layer contact or via. 10. The method of claim 9,
The deformation or distortion is such that a difference between a ratio of short-circuiting between the conductive layers and a ratio of non-short-circuiting between the conductive layers among the designed N inter-layer contacts is less than a first threshold;
Changing at least one of the shape and size of the N mask windows. When a mask pattern designed to implant a plurality of inter-layer contacts between semiconductor conductive layers is received, the mask pattern is deformed or distorted so that at least some of the plurality of inter-layer contacts are not implanted in a stochastic manner to form a photomask. processing unit to generate; and
A print unit that prints the photomask
including,
In the photomask, when photolithography is performed, a ratio difference between a non-implanted inter-layer contact and an implanted inter-layer contact shorting between the semiconductor conductive layer among the plurality of inter-layer contacts is a first threshold value. At least one of the size and shape of at least some mask windows included in the mask pattern is deformed or distorted so as to be as follows;
The processing unit,
generating the photomask in which the shape of the at least one mask window is modified by omitting OPC (Optical Proximity Correction) or applying a modified OPC to at least one mask window included in the mask pattern,
The deformed at least one mask window,
a difference between a probability that an inter-layer contact or a via formed using the photomask short-circuits the conductive layers and a probability that the inter-layer contact cannot short-circuit falls within a predetermined range;
and a PUF value is determined based on the formed inter-layer contact or via. 12. The method of claim 11,
The processing unit,
and generating the photomask in which the size of the at least one mask window is scaled down by applying a scale factor smaller than 1 to at least one mask window included in the mask pattern. 12. The method of claim 11,
The processing unit,
and deforming the shape of at least one mask window included in the mask pattern in at least one direction to generate the photomask in which the shape of the at least one mask window is changed.

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