KR102313004B1 - Display device and method of manufacturing the same - Google Patents

Abstract

The display device includes a planarization layer disposed in a display area of a substrate, a first electrode, a second electrode, and a third electrode sequentially stacked on the planarization layer, and an undercut is formed at an edge portion of the first electrode. on the formed first pixel electrode, a pixel defining layer having an opening covering the undercut of the first pixel electrode and exposing a portion of the first pixel electrode, an organic emission layer disposed in the opening of the pixel defining layer, and the organic emission layer and a second pixel electrode disposed to overlap the first pixel electrode. According to this, in the etching process of the pixel electrode layer having a stacked structure of ITO/Ag/ITO, the upper ITO layer is first etched by the first etch process, and the Ag layer and the lower ITO layer are etched by the second etch process. Through this, it is possible to suppress the generation of silver-particles.

Description

Display device and manufacturing method thereof

The present invention relates to a display device and a manufacturing method thereof, and more particularly, to a display device having improved defects and a manufacturing method thereof.

Recently, the importance of a flat panel display having excellent characteristics such as reduction in thickness, weight reduction, and low power consumption is increasing. Among flat panel displays, liquid crystal displays and organic light emitting displays are widely commercialized due to their excellent resolution and image quality. In particular, an organic light emitting diode display has been attracting attention as a next-generation flat panel display because of its fast response speed, low power consumption, and excellent viewing angle because it emits light itself.

The organic light emitting diode display may include an organic light emitting diode formed in the display area and wirings formed in a peripheral area adjacent to the display area. The organic light emitting device may include electrodes and an organic light emitting layer interposed between the electrodes to emit light.

When a metal layer is formed in the display area and the peripheral area and the electrode of the organic light emitting device is etched, the wiring and the metal layer may react with an etchant, which is an electrolyte, to cause galvanic corrosion. Galvanic corrosion refers to a phenomenon in which metal ions are reduced due to the movement of electrons by oxidation-reduction reaction when two metals having different corrosion potentials are connected with an electrolyte. When the corrosion potential of the metal layer and the metal material constituting the wiring is greatly different, galvanic corrosion may occur.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device in which particle defects are improved.

SUMMARY OF THE INVENTION One object of the present invention is to provide a method of manufacturing a display device for suppressing generation of particles.

In order to achieve the above object, a display device according to embodiments of the present invention includes a planarization layer disposed in a display area of a substrate, and a first electrode, a second electrode, and a third electrode sequentially stacked on the planarization layer. a first pixel electrode having an undercut formed at an edge portion of the first electrode, a pixel defining layer having an opening covering the undercut of the first pixel electrode and exposing a portion of the first pixel electrode, the pixel definition an organic light emitting layer disposed in the opening of the layer and a second pixel electrode disposed on the organic light emitting layer and overlapping the first pixel electrode.

According to an embodiment, the first electrode may include indium tin oxide, the second electrode may include silver, and the third electrode may include indium tin oxide.

According to an embodiment, the display device may further include a pad electrode disposed in a non-display area of the substrate surrounding the display area, wherein the pad electrode may include aluminum.

According to an embodiment, the pad electrode includes a first layer, a second layer, and a third layer that are sequentially stacked, the first layer and the third layer include titanium (Ti), and the second The layer may comprise aluminum.

The display device may further include a thin film transistor disposed between the substrate and the first pixel electrode and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

According to an embodiment, the length of the undercut formed at the edge portion of the first pixel electrode may be 190 nm to 250 nm.

In order to achieve the above object, a method of manufacturing a display device according to embodiments of the present invention includes forming a planarization layer disposed on a display area of a substrate, a first electrode layer sequentially stacked on the planarization layer, and a second Forming a first pixel electrode layer including an electrode layer and a third electrode layer, first etching the third electrode layer with a first etchant to pattern a third electrode of the first pixel electrode, the second electrode layer and the first patterning the second electrode and the first electrode of the first pixel electrode by second etching the electrode layer with a second etchant; forming an organic light emitting layer on the first pixel electrode; and the first step on the organic light emitting layer The method may include forming a second pixel electrode overlapping the pixel electrode.

The method may further include forming a pad electrode disposed in a non-display area of the substrate surrounding the display area, wherein the pad electrode may include aluminum.

According to an embodiment, the pad electrode includes a first layer, a second layer, and a third layer that are sequentially stacked, the first layer and the third layer include titanium (Ti), and the second The layer may comprise aluminum.

According to an embodiment, the forming of the first pixel electrode layer may include forming the first pixel electrode layer on the pad electrode disposed in the non-display area.

According to an embodiment, the first electrode layer may include indium tin oxide, the second electrode layer may include silver, and the third electrode layer may include indium tin oxide.

In an embodiment, in the first etching of the third electrode layer, an undercut may be formed in the first electrode layer corresponding to an edge portion of the first pixel electrode and an edge portion of the pad electrode.

In an embodiment, in the second etching of the second electrode layer and the first electrode layer, silver ions generated from the second electrode layer may be collected in the undercut.

According to an embodiment, the length of the undercut formed at the edge portion of the first pixel electrode may be 190 nm to 250 nm.

According to an embodiment, the length of the undercut formed on the edge portion of the pad electrode may be 180 nm to 200 nm.

The method may further include forming a pixel defining layer covering the undercut of the first pixel electrode and having an opening exposing a portion of the first pixel electrode, wherein the organic emission layer is formed through the opening of the pixel defining layer can be formed within.

According to an embodiment, the manufacturing method may further include forming a thin film transistor disposed between the substrate and the first pixel electrode and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

According to the display device and the method for manufacturing the same according to the embodiments of the present invention as described above, in the etching process of the pixel electrode layer having the ITO/Ag/ITO stacked structure, the upper ITO layer is first etched by the first etching process, and the Ag layer And through a two-step etching process of etching the lower ITO layer followed by a second etching process, the generation of silver-particles can be suppressed. As a result, defects in the manufacturing process can be eliminated by the silver-particles. In addition, it is possible to prevent the side surface of the pad electrode from being corroded by blocking the reaction with the aluminum included in the pad electrode.

1 is a plan view of a display device according to an exemplary embodiment.
FIG. 2 is an enlarged view for explaining a portion A of the display device of FIG. 1 .
3 is a cross-sectional view of the display device taken along lines I-I' and II-II' of FIG. 2 .
4 to 10 are cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment.
11A and 11B are photographs for comparing the occurrence of silver-particles according to Examples and Comparative Examples.
12A and 12B are photographs for comparing whether an undercut is generated according to an Example and a Comparative Example.

Hereinafter, with reference to the accompanying drawings, an embodiment of the present invention will be described in more detail.

1 is a plan view of a display device according to an exemplary embodiment.

Referring to FIG. 1 , a display device according to an exemplary embodiment may include a display area DA and a non-display area NDA. A plurality of pixels PX may be disposed in the display area DA. The display area DA may display an image based on the lights emitted by the plurality of pixels PX.

The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may be located on at least one side of the display area DA. For example, the non-display area NDA may surround the display area DA. The non-display area NDA may include a wiring area SLA in which a plurality of fan-out wirings are arranged and a pad area PDA in which a plurality of pad electrodes formed at ends of the plurality of fan-out wirings are arranged.

FIG. 2 is an enlarged view for explaining a portion A of the display device of FIG. 1 . 3 is a cross-sectional view of the display device taken along lines I-I' and II-II' of FIG. 2 .

2 and 3 , a display device according to an exemplary embodiment includes a substrate 110 , a thin film transistor (TFT), an organic light emitting diode (OLED), a fan-out line SL, and a pad electrode 160 . may include.

The substrate 110 includes a display area DA and a non-display area NDA. The substrate 110 may be a transparent or opaque insulating substrate. For example, the substrate 110 may include glass or a plastic such as polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyacrylate, or the like.

A buffer layer 115 may be disposed on the substrate 110 . The buffer layer 115 may block impurities such as oxygen and moisture penetrating through the substrate 110 . In addition, the buffer layer 115 may provide a flat surface on the substrate 110 . The buffer layer 115 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. Optionally, the buffer layer 115 may be omitted.

A thin film transistor (TFT) and an organic light emitting diode (OLED) may be disposed in the display area DA on the buffer layer 115 . The thin film transistor TFT may include a semiconductor layer 120 , a gate electrode 130 , a source electrode 140 , and a drain electrode 150 . In an embodiment, the thin film transistor TFT may have a top-gate structure in which the gate electrode 130 is positioned on the semiconductor layer 120 . Alternatively, the thin film transistor TFT may have a bottom-gate structure in which a gate electrode is positioned under a semiconductor layer. Alternatively, the gate electrode may have a double-gate structure in which the gate electrode is disposed above and below the semiconductor layer 120 , respectively.

The semiconductor layer 120 may be disposed on the buffer layer 115 . The semiconductor layer 120 may be formed of amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like. The semiconductor layer 120 may include a source region, a drain region, and a channel region formed therebetween.

A gate insulating layer 125 covering the semiconductor layer 120 may be disposed on the buffer layer 115 . The gate insulating layer 125 may be positioned in the display area DA and the non-display area NDA on the substrate 110 . The gate insulating layer 125 may insulate the gate electrode 130 from the semiconductor layer 120 . The gate insulating layer 125 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

The gate electrode 130 may be disposed on the gate insulating layer 125 . The gate electrode 130 may overlap the channel region of the semiconductor layer 120 . The gate electrode 130 may be formed of a first metal layer. The first metal layer may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), or an alloy of a metal.

An interlayer insulating layer 135 covering the gate electrode 130 may be disposed on the gate insulating layer 125 . The interlayer insulating layer 135 may be positioned in the display area DA and the non-display area NDA on the substrate 110 . The interlayer insulating layer 135 may insulate the source and drain electrodes 140 and 150 from the gate electrode 130 . The interlayer insulating layer 135 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

The source electrode 140 and the drain electrode 150 may be disposed on the interlayer insulating layer 135 . The source electrode 140 and the drain electrode 150 may be respectively connected to a source region and a drain region of the semiconductor layer 120 through contact holes formed in the interlayer insulating layer 135 and the gate insulating layer 125 . have. The source electrode 140 and the drain electrode 150 may be formed of a second metal layer. The second metal layer may include aluminum (Al). The second metal layer may include aluminum and an aluminum alloy. The aluminum alloy may include any one of copper (Cu), vanadium (V), and silicon (Si).

The second metal layer may include a first layer 161 , a second layer 162 , and a third layer 163 sequentially stacked. For example, the first layer 161 may be disposed on the lower surface of the second layer 162 , and the third layer 163 may be disposed on the upper surface of the second layer 162 . The first layer 161 , the second layer 162 , and the third layer 163 may include titanium (Ti), aluminum (Al), and titanium, respectively.

Although not shown, the display device may further include a storage capacitor disposed in the display area DA on the substrate 110 . The storage capacitor may include a first storage electrode formed of the same first metal layer as the gate electrode 130 and a second storage electrode formed of the same second metal layer as the source and drain electrodes 140 and 150 .

A planarization layer 175 for planarizing the display area DA in which the thin film transistor TFT is formed may be disposed on the substrate 110 . The planarization layer 175 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, or a polyester resin.

The organic light emitting diode OLED may be disposed on the planarization layer 175 . The organic light emitting diode OLE includes a first pixel electrode 180 , an organic emission layer 210 , and a second pixel electrode 230 .

The first pixel electrode 180 may include a first electrode 181 , a second electrode 182 , and a third electrode 183 sequentially stacked.

For example, the first electrode 181 is disposed on the planarization layer 175 , the second electrode 182 is disposed on the first electrode 181 , and the third electrode 183 is disposed on the planarization layer 175 . is disposed on the second electrode 182 .

The first electrode 181 may include indium tin oxide (ITO), the second electrode 182 may include silver (Ag), and the third electrode 183 may include indium tin oxide ( ITO) may be included. The second electrode 182 of the first pixel electrode 180 serves as a main electrode layer, and the first electrode 181 and the third electrode 183 of the first pixel electrode 180 each serve as a second electrode ( 182) may serve as an auxiliary electrode layer to protect the lower and upper surfaces.

A pixel defining layer 190 having an opening exposing the first pixel electrode 180 may be disposed in the display area DA of the substrate 110 on which the first pixel electrode 180 is disposed. The pixel defining layer 190 may include an opening exposing the top surface of the first pixel electrode 180 , and the emission area of the pixel may be defined as the area in which the opening is formed. The pixel defining layer 190 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, or a polyester resin.

The organic emission layer 210 may be disposed in the opening of the pixel defining layer 190 . The organic light emitting layer 210 may include a low molecular weight organic compound or a high molecular weight organic compound.

In an embodiment, the organic emission layer 210 may emit red light, green light, or blue light. Alternatively, when the organic light emitting layer 210 emits white light, the organic light emitting layer 210 includes a multilayer structure including a red light emitting layer, a green light emitting layer, and a blue light emitting layer, or a red light emitting material, a green light emitting material, and a blue light emitting material It may include a single-layer structure comprising a.

The second pixel electrode 230 may be disposed in the display area DA on the substrate 110 on which the organic emission layer 210 is disposed. The second pixel electrode 230 may overlap the first pixel electrode 180 . Specifically, the second pixel electrode 220 may be disposed to cover the organic emission layer 210 and the pixel defining layer 197 . The second pixel electrode 220 may include lithium (Li), calcium (Ca), lithium fluoride (LiF), silver (Ag), aluminum (Al), magnesium (Mg), or a combination thereof. For example, the second pixel electrode 220 may have an Mg/Ag structure in which magnesium (Mg) and silver (Ag) are stacked.

The fan-out line SL and a pad electrode 160 formed at an end of the fan-out line SL may be disposed on the interlayer insulating layer 135 of the non-display area NDA.

The fan-out line SL may be formed of the same first metal layer as the gate electrode 130 , or may be formed of the same second metal layer as the source and drain electrodes 140 and 150 .

The pad electrode 160 may be formed of the same second metal layer as the source and drain electrodes 140 and 150 . The pad electrode 160 may include a first layer 161 , a second layer 162 , and a third layer 163 sequentially stacked. The second layer 162 of the pad electrode 160 serves as a main electrode layer, and the first layer 161 and the third layer 163 of the pad electrode 160 are each a second layer 162 . It can serve as an auxiliary electrode layer to protect the lower and upper surfaces.

When the fan-out line SL is formed of the first metal layer, the pad electrode 160 may contact the fan-out line SL through a contact hole formed in the interlayer insulating layer 135 . Alternatively, when the fan-out line SL is formed of the second metal layer, the pad electrode 160 may be integrally formed with the fan-out line SL.

In an embodiment, the first pixel electrode 180 of the organic light emitting diode (OLED) may be patterned through a two-step etching process. For example, the third electrode 183 positioned above the first pixel electrode 180 is first patterned by a first etching process using a first etchant, and then the third electrode 183 positioned below the first pixel electrode 180 is patterned. The second electrode 182 and the first electrode 181 may be collectively patterned by a second etching process using a second etchant.

In an embodiment, silver particles (Ag) generated by silver ions (Ag+) generated in the etching process by patterning the first pixel electrode 180 including silver (Ag) by the two-step etching process The number of particles) can be reduced. In addition, the silver ions (Ag+) galvanically react with aluminum (Al) included in the pad electrode 160 to reduce a defect in which the side surface of the pad electrode 160 is corroded. The silver-particles may cause various defects in subsequent processes. For example, in a subsequent process, the silver-particles may combine with moisture and gradually multiply to generate a dark spot defect that short-circuits the first pixel electrode 180 and the second pixel electrode 230 . Also, it is possible to short-circuit the adjacent pad electrodes 160 .

Accordingly, according to an embodiment, by performing the etching process of the first pixel electrode 180 as a two-step etching process, generation of the silver-particles is suppressed to improve defects occurring in the manufacturing process of the display device. can

4 to 10 are cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment.

Referring to FIG. 4 , the thin film transistor TFT may be formed in the display area DA of the substrate 110 and the pad electrode 160 may be formed in the non-display area NDA.

A buffer layer 115 may be formed in the display area DA and the non-display area NDA on the substrate 110 . For example, the buffer layer 115 may be formed by various methods such as chemical vapor deposition and sputtering using silicon oxide, silicon nitride, or silicon oxynitride.

The semiconductor layer 120 may be formed in the display area DA of the substrate 110 on which the buffer layer 115 is formed. For example, a film including a material containing silicon or an oxide semiconductor may be formed on the entire surface of the buffer layer 115 and patterned to form the semiconductor layer 120 . When the semiconductor layer 120 is formed using the silicon-containing material, an amorphous silicon film may be formed on the entire surface of the buffer film 115 and crystallized to form a polycrystalline silicon film. Thereafter, after patterning the patterned polysilicon film, impurities may be doped into both sides of the patterned polysilicon film to form the semiconductor film 120 including a source region, a drain region, and a channel region therebetween.

A gate insulating layer 125 may be formed in the display area DA and the non-display area NDA on the substrate 110 on which the semiconductor layer 120 is formed. For example, the gate insulating layer 125 may be formed using silicon oxide, silicon nitride, silicon oxynitride, or the like.

A first metal layer may be formed on the gate insulating layer 125 and the gate electrode 130 may be formed in the upper display area DA by patterning the first metal layer. The gate electrode 130 may overlap the semiconductor layer 120 . The first metal layer may be formed using a metal, an alloy of metals, or the like.

An interlayer insulating layer 135 may be formed in the display area DA and the non-display area NDA on the substrate 110 on which the gate electrode 130 is formed. For example, the interlayer insulating layer 135 may be formed using silicon oxide, silicon nitride, silicon oxynitride, or the like.

A plurality of contact holes exposing the semiconductor layer 120 may be formed in the interlayer insulating layer 135 and the gate insulating layer 125 . For example, the contact holes may expose a source region and a drain region of the semiconductor layer 120 , respectively.

A second metal layer is formed on the substrate 110 on which the interlayer insulating layer 135 is formed, and the second metal layer is patterned. By patterning the second metal layer, the source electrode 140 and the drain electrode 150 may be formed in the display area DA, and the pad electrode 160 may be formed in the non-display area NDA.

The second metal layer may include aluminum (Al) and an aluminum alloy, and the aluminum alloy may include any one of copper (Cu), vanadium (V), and silicon (Si).

In an embodiment, the second metal layer may include a first layer 161 , a second layer 162 , and a third layer 163 sequentially stacked. For example, as the second metal layer, a first layer including titanium (Ti), a second layer including aluminum, and a third layer including titanium may be sequentially stacked on the interlayer insulating layer 135 . . Accordingly, each of the source electrode 140 , the drain electrode 150 , and the pad electrode 160 may have a Ti/aluminum/Ti stacked structure.

Referring to FIG. 5 , a planarization layer 175 is formed on the substrate 110 on which the interlayer insulating layer 135 is formed. The planarization layer 175 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, or a polyester resin. The planarization layer 175 may be formed to have a thickness sufficient to sufficiently cover the source electrode 140 and the drain electrode 150 formed in the display area DA.

The planarization layer 175 may be patterned to remain in the display area DA, and may be removed to expose the pad electrode 160 in the non-display area NDA.

Referring to FIG. 6 , a first pixel electrode layer 180a is formed on the substrate 110 on which the planarization layer 175 is formed. The first pixel electrode layer 180a is formed by sequentially stacking a first electrode layer 181a, a second electrode layer 182a, and a third electrode layer 183a.

The first electrode layer 181a may include indium tin oxide (ITO). The second electrode layer 182a may include silver (Ag). The third electrode layer 183a may include the indium tin oxide (ITO). The first pixel electrode layer 180a may have a stacked structure of ITO/Ag/ITO.

A photoresist pattern PRP is formed in the display area DA on the substrate 110 on which the first pixel electrode layer 180a is formed. The photoresist pattern PRP may be formed on the electrode area EA in which the first pixel electrode 180 of the organic light emitting diode OLED is formed in the display area DA.

Referring to FIG. 7 , the third electrode layer 183a positioned above the first pixel electrode layer 180a is first etched through a first etching process using a first etchant using the photoresist pattern PRP as a mask. . For example, the first etchant may include a composition for etching the indium tin oxide (ITO).

The third electrode layer 183a formed in the display area DA by the first etching process is patterned as the third electrode 183 of the first pixel electrode 180 . Also, the third electrode layer 183a formed in the non-display area NDA is removed.

In the first etching process, the first etchant penetrates to the second electrode layer 182a and the first electrode layer 181a positioned below the third electrode layer 183a. The first electrode layer 181a including the indium tin oxide (ITO), which is the same material as the third electrode layer 183a, is partially removed by the first etching process to form an undercut ( UDC) is formed.

Referring to FIG. 8 , the thickness of the pad electrode 160 is about 6000 ? , and the first pixel electrode layer 180a has a relatively thin thickness of about 1000 ? is formed with Accordingly, the step coverage of the first pixel electrode layer 180a in the step portion of the pad electrode 160 is not good. An undercut UDC is formed on the stepped edge portion of the pad electrode 160 by the first etching process. The length of the undercut UDC at the stepped edge portion of the pad electrode 160 may be about 180 nm to 200 nm.

Thereafter, referring to FIGS. 8 and 9 , the second electrode layer 182a and the first electrode layer 181a of the first pixel electrode layer 180a are etched through a second etching process using a second etchant. The second etchant may include a composition for etching the silver (Ag) and the indium tin oxide (ITO).

In the second etching process, silver (Ag) included in the second electrode layer 182a is oxidized to generate silver ions (Ag+) 182b. The silver ions 182b are collected in the undercut UDC formed in the step portion of the pad electrode 160 . Since the silver ions 182b are gathered in the undercut UDC, it is possible to prevent the silver ions 182b from moving toward the pad electrode 160 .

Accordingly, electrons generated from aluminum included in the pad electrode 160 in the second etching process combine with the silver ions 182b by suppressing movement of the silver ions 182b by the undercut UDC. can be blocked from doing It is possible to prevent the silver ions 182b from being reduced to silver-particles by combining with electrons (−) generated from the aluminum. That is, generation of the silver-particles may be prevented.

On the other hand, when some silver ions 182b move toward the pad electrode 160 , the silver ions 182b are reduced by electrons (−) taken from aluminum included in the pad electrode 160 to form silver particles. can be created However, in this case, hydrogen ions included in the second etchant again take electrons (-) from the silver-particles. Accordingly, the silver-particles having lost electrons (−) may be oxidized to silver ions 182b again. As a result, generation of the silver-particles can be prevented.

As described above, in the process of forming the first pixel electrode 180 by performing the etching process of forming the first pixel electrode 180 by patterning the first pixel electrode layer 180a as a two-step etching process, The number of generated silver-particles can be reduced. In addition, the side surface of the pad electrode 160 may be prevented from being corroded by blocking the reaction of the silver ions 182b with the aluminum included in the pad electrode 160 .

The second electrode layer 182a and the first electrode layer 181a formed in the display area DA by the second etching process are the second electrode 182 and the first electrode ( 181) is patterned. Accordingly, the first pixel electrode 180 of the organic light emitting diode OLED is formed in the electrode area EA. An undercut UDC formed on the first electrode layer 181a in the first etching process is included in an edge portion of the first pixel electrode 180 . The length of the undercut of the first pixel electrode 180 may be about 190 nm to 250 nm.

In addition, the second electrode layer 182a and the first electrode layer 181a formed in the non-display area NDA are removed to expose the pad electrode 160 .

After the second etching process is completed, the photoresist pattern PRP is removed. In addition, silver-particles remaining on the interlayer insulating layer 135 , the pad electrode 170 , and the planarization layer 175 may be removed through a separate cleaning process.

3 and 10 , a pixel defining layer 190 covering the first pixel electrode 180 may be formed in the display area DA on the planarization layer 175 . For example, the pixel defining layer 190 is formed of a polyimide-based resin, a photoresist, an acryl-based resin, a polyamide-based resin, a siloxane-based resin, or the like. can be

The pixel defining layer 190 may be patterned to form an opening exposing a top surface of the first pixel electrode 180 . The pixel defining layer 190 is formed to overlap the undercut UDC formed on an edge portion of the first pixel electrode 180 . Accordingly, it is possible to prevent a display defect caused by the undercut UDC of the first pixel electrode 180 from being recognized by the pixel defining layer 190 .

An organic emission layer 210 may be formed in the opening exposing the first pixel electrode 180 . For example, the organic light emitting layer 210 may be formed of a low molecular weight organic compound or a high molecular weight organic compound using a method such as screen printing, inkjet printing, or deposition.

Thereafter, a second pixel electrode 220 may be formed on the pixel defining layer 190 and the organic emission layer 210 .

The second pixel electrode 220 may be formed of lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), silver (Ag), magnesium (Mg), or the like. For example, the second pixel electrode 220 may include an Mg/Ag stack structure in which a first layer including magnesium (Mg) and a second layer including silver (Ag) are stacked.

11A and 11B are photographs for comparing the generation of silver-particles according to Examples and Comparative Examples. 12A and 12B are photographs for comparing whether an undercut is generated according to an Example and a Comparative Example.

The etching process of the pixel electrode layer having a stacked structure of ITO/Ag/ITO according to the embodiment includes a first etching step of first etching the upper ITO layer, and a second etching step of batch etching the Ag layer and the lower ITO layer.

The etching process of the pixel electrode layer having a stacked structure of ITO/Ag/ITO according to Comparative Example 1 simultaneously etches the upper ITO layer, the Ag layer, and the lower ITO layer.

The etching process of the pixel electrode layer having a stacked structure of ITO/Ag/ITO according to Comparative Example 2 includes a first etching step of first batch etching the upper ITO and Ag layers, and a second etching step of etching the lower ITO layer.

Table 1 shows data comparing the occurrence of silver-particles according to Examples and Comparative Examples.

<Table 1>

11A and <Table 1>, in the case of the embodiment, silver particles (Ag P/C) were hardly generated on the pad electrode 160 .

Meanwhile, referring to FIG. 11B and <Table 1>, in Comparative Example 1, a large number of silver-particles (Ag P/C) were generated on the pad electrode 160 . In addition, in the case of Comparative Example 2, silver-particles (Ag P/C) were also generated on the pad electrode.

Comparing whether the undercut is formed in the electrode layer on the pad electrode with respect to the generation of the silver particles (Ag P/C), in the embodiment in which the silver particles (Ag P/C) are not generated, the pad electrode 160 . The undercut was formed on the upper electrode layer. On the other hand, in Comparative Examples 1 and 2 in which a large number of silver particles (Ag P/C) were generated, no undercut was formed in the electrode layer on the pad electrode 160 .

Therefore, when the undercut is formed in the electrode layer on the pad electrode, it can be confirmed that the silver-particles (Ag P/C) are not generated.

Table 2 is data comparing the occurrence of undercuts according to Examples and Comparative Examples.

<Table 2>

12A and <Table 2>, in the case of the above embodiment, the length of the undercut (UDC) formed in the electrode layer on the pad electrode 160 is about 196.7 nm, and in the case of Comparative Example 1, the length of the undercut formed in the electrode layer on the pad electrode is about 106.5 nm, and in Comparative Example 2, the undercut length formed in the electrode layer on the pad electrode was about 181.0 nm.

Referring to FIG. 12B , the undercut UDC of the example is about twice that of the undercut UDC1 of the comparative example 1.

When the pixel electrode layer is etched by a two-step etching process as in the embodiment, the undercut formed on the electrode layer on the pad electrode is twice as large as the undercut formed on the electrode layer on the pad electrode when the pixel electrode layer is batch-etched as in Comparative Example 1. formed large. On the other hand, in the embodiment in which the undercut is large, it can be seen that the silver-particles (Ag P/C) are not generated.

As a result, when the undercut is formed in the electrode layer on the pad electrode, it can be confirmed that silver-particles (Ag P/C) are not generated.

According to the above embodiments of the present invention, in the etching process of the pixel electrode layer having a stacked structure of ITO/Ag/ITO, the upper ITO layer is first patterned by the first etching process, and the Ag layer and the lower ITO layer are followed by the second etching process The generation of silver-particles can be suppressed through the two-step etching process of patterning with . As a result, it is possible to remove defects that may occur in the manufacturing process due to the silver particles. In addition, it is possible to prevent the side surface of the pad electrode from being corroded by blocking the reaction with the aluminum included in the pad electrode.

The present invention can be applied to a display device and various devices and systems including the same. Accordingly, the present invention is a mobile phone, a smart phone, a PDA, a PMP, a digital camera, a camcorder, a PC, a server computer, a workstation, a notebook computer, a digital TV, a set-top box, a music player, a portable game console, a navigation system, a smart card, a printer It can be usefully used in various electronic devices such as

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. you will understand that you can

110: substrate 120: semiconductor layer
130: gate electrode 140: source electrode
150: drain electrode 160: pad electrode
175: planarization layer 180: first pixel electrode
210: organic light emitting layer 220: second pixel electrode
UDC: Undercut OLED: Organic Light Emitting Diode

Claims (19)

a substrate including a display area and a non-display area;
a thin film transistor disposed in the display area on the substrate;
a first conductive layer, a second conductive layer, and a third conductive layer disposed in the display area on the thin film transistor and sequentially stacked, wherein a length of the first conductive layer is smaller than a length of the second conductive layer pixel electrode;
an organic light emitting layer disposed on the pixel electrode; and
a counter electrode disposed on the organic light emitting layer;
A difference in length between the first conductive layer and the second conductive layer in the edge portion of the pixel electrode is 190 nm to 250 nm. According to claim 1, wherein the thin film transistor,
a semiconductor layer disposed on the substrate;
a gate electrode disposed on the semiconductor layer; and
and a source electrode and a drain electrode disposed on the gate electrode. The display device of claim 2 , wherein the gate electrode and the pixel electrode contain different materials. The display device of claim 3 , wherein the gate electrode is formed as a single layer. 3. The method of claim 2,
a gate insulating layer disposed on the substrate and covering the semiconductor layer in the display area; and
and an interlayer insulating layer disposed on the gate insulating layer and covering the gate electrode in the display area. The display device of claim 5 , wherein the gate insulating layer and the interlayer insulating layer extend from the display area to the non-display area. The method of claim 1, wherein the first conductive layer comprises indium tin oxide (ITO),
The second conductive layer includes silver (Ag),
The third conductive layer includes indium tin oxide (ITO). The method of claim 1,
and an insulating layer disposed between the thin film transistor and the pixel electrode. The display device of claim 8 , wherein the insulating layer is disposed in the display area on the substrate and not in the non-display area. 9. The method of claim 8,
and a pixel defining layer disposed on the insulating layer and having an opening that covers a portion of the pixel electrode and exposes a portion of the pixel electrode. The display device of claim 10 , wherein the pixel defining layer is disposed in the display area on the insulating layer and is not disposed in the non-display area. delete a substrate including a display area and a non-display area;
a thin film transistor disposed in the display area on the substrate;
a pad electrode disposed in the non-display area on the substrate;
a first conductive layer, a second conductive layer, and a third conductive layer disposed in the display area on the thin film transistor and sequentially stacked, wherein a length of the first conductive layer is smaller than a length of the second conductive layer pixel electrode;
an organic light emitting layer disposed on the pixel electrode; and
a counter electrode disposed on the organic light emitting layer;
The second and third conductive layers have a forward-tapered shape. 14. The method of claim 13, wherein the thin film transistor,
a semiconductor layer disposed on the substrate;
a gate electrode disposed on the semiconductor layer; and
and a source electrode and a drain electrode disposed on the gate electrode. The display device of claim 14 , wherein the source and drain electrodes contain the same material as the pad electrode. 15. The method of claim 14,
a gate insulating layer disposed on the substrate and covering the semiconductor layer in the display area; and
and an interlayer insulating layer disposed on the gate insulating layer and covering the gate electrode in the display area. The display device of claim 16 , wherein a top surface of the interlayer insulating layer contacts the source and drain electrodes in the display area and contacts the pad electrode in the non-display area. 14. The method of claim 13, wherein the pad electrode comprises a first layer, a second layer, and a third layer sequentially stacked, the first layer and the third layer comprising titanium (Ti), the second The layer is a display device including aluminum (Al). The display device of claim 13 , wherein the pixel electrode and the pad electrode include different materials.

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