KR102284479B1 - Structure and formation method of semiconductor device with stressor - Google Patents

Abstract

A semiconductor device structure and a method for forming the semiconductor device structure are provided. The semiconductor device structure includes a plurality of semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is interspersed with epitaxial structures. The semiconductor device structure also includes a gate stack that wraps around the semiconductor nanostructure. The semiconductor device structure further includes a stressor structure between the gate stack and the substrate. The epitaxial structure extends beyond the top surface of the stressor structure.

Description

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH STRESSOR

Priority Claims and Cross-References

This application claims the benefit of U.S. Provisional Application No. 62/928,650, filed on October 31, 2019, the entirety of which is incorporated herein by reference.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have created generations of ICs. Each generation has smaller and more complex circuits than the previous generation.

Over the course of IC evolution, the geometric size (ie, the smallest component (or wiring) that can be created using a manufacturing process) has decreased, but the functional density (ie, interconnected devices per chip area) has decreased. )) was generally increased. This reduction process generally provides advantages by increasing production efficiency and lowering associated costs.

However, these advances have increased the complexity of processing and manufacturing ICs. As feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform. Therefore, it is difficult to form a reliable semiconductor device in a smaller and smaller size.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
1A and 1B are top views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments.
2A-2J are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments.
3A-3N are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments.
4A and 4B are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments.
5 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
6 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
7A-7C are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments.
8A-8C are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments.
9 is a cross-sectional view of a semiconductor device structure in accordance with some embodiments.
10 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
11 is a cross-sectional view of a semiconductor device structure in accordance with some embodiments.
12 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
13 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
14A-14C are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments.
15 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
16 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
17A-17C are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments.

The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, examples only and are not intended to be limiting. For example, in the description that follows, forming a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and also include the first feature and the second feature. Embodiments may also include embodiments in which additional features may be formed between the two features, such that the first and second features may not be in direct contact as a result. In addition, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for simplicity and clarity, and, in itself, does not indicate a relationship between the various embodiments and/or configurations being discussed.

Also, for ease of explanation describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures, “beneath”, “below” Spatially relative terms such as , "lower", "above", "upper" and the like may be used herein. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substantially” in the description, as in “substantially flat” or “substantially coplanar,” and the like, will be understood by those skilled in the art. In some embodiments, the adjective may be substantially removed. Where applicable, the term “substantially” may also include embodiments having “totally”, “completely”, “all”, and the like. Where applicable, the term “substantially” may also relate to at least 90%, including at least 100%, such as at least 95%, in particular at least 99%. Moreover, terms such as "substantially parallel" or "substantially perpendicular" are to be construed as not excluding minor deviations from the specified arrangement, which may include, for example, deviations of up to 10°. The word "substantially" does not exclude "completely", for example, a composition "substantially free" of Y may be completely free of Y.

Terms such as “about” in connection with a particular distance or size are to be construed as not excluding minor deviations from the specified distance or size, which may include, for example, deviations of up to 10%. The term “about” in reference to a numerical value x may mean x±5 or 10%.

Embodiments of the present disclosure may relate to FinFET structures having fins. The pins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double-patterning process or a multi-patterning process. In general, double patterning or multiple patterning processes combine photolithography and self-aligned processes, for example, in smaller sizes than otherwise obtainable using a single direct photolithography process. Allows a pattern with a pitch to be created. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. The spacers are formed alongside the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins. However, the fins may be formed using one or more other applicable processes.

Embodiments of the present disclosure may relate to gate all around (GAA) transistor structures. The GAA structure may be patterned using any suitable method. For example, the structure may be patterned using one or more photolithographic processes, including dual patterning or multiple patterning processes. In some embodiments, the double patterning or multiple patterning process combines a photolithography and self-alignment process, eg, a pattern having a smaller pitch than would otherwise be obtainable using a single direct photolithography process. allow it to be created. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. The spacers are formed alongside the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the GAA structure.

Several embodiments of the present disclosure are described. Additional actions may be provided before, during, and/or after the steps described in these embodiments. Some of the steps described may be replaced or eliminated for different embodiments. Additional features may be added to the semiconductor device structure. Some of the features described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in other logical orders.

2A-2J are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 2A , the semiconductor substrate 100 is accommodated or provided. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 100 may include other basic semiconductor materials such as silicon or germanium. The semiconductor substrate 100 may be undoped or doped (eg, p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate 100 includes a semiconductor layer that is epitaxially grown on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or combinations thereof.

In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, compound semiconductors include one or more Group III-V compound semiconductors having a composition defined by the _{formula Al X1} Ga _X2 In _X3 As _Y1 P _Y2 N _Y3 Sb _{Y4 , wherein X1, X2, X3, Y1,} Y2, Y3 and Y4 represent relative proportions. each of them is greater than or equal to zero, and added together they are equal to one. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable substrates comprising II-VI compound semiconductors may also be used.

In some embodiments, the semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMIOX) process, a wafer bonding process, other applicable methods, or a combination thereof. In some other embodiments, the semiconductor substrate 100 includes a multilayer structure. For example, the semiconductor substrate 100 includes a silicon-germanium layer formed on a bulk silicon layer.

In accordance with some embodiments, as shown in FIG. 2A , a semiconductor stack having multiple semiconductor layers is formed over a semiconductor substrate 100 . In some embodiments, the semiconductor stack includes multiple semiconductor layers 102a, 102b, 102c, and 102d, and the semiconductor stack also includes multiple semiconductor layers 104a, 104b, 104c, and 104d. In some embodiments, semiconductor layers 102a - 102d and semiconductor layers 104a - 104d are alternately disposed, as shown in FIG. 2A .

In some embodiments, the semiconductor layer 102a is used as a base layer that will later be partially or fully converted into a stressor structure. In some embodiments, the semiconductor layer 104a functions as a protective layer that prevents the semiconductor layer 102a from being damaged during a subsequent manufacturing process. In some embodiments, the semiconductor layer 104a is thinner than the semiconductor layer 104b , 104c or 104d . In some embodiments, the semiconductor layers 102b - 102d serve as a sacrificial layer to be removed in a subsequent process to separate the semiconductor layers 104b - 104d. The semiconductor layers 104b - 104d may function as a channel structure for one or more transistors.

As shown in FIG. 2A , the semiconductor layer 104a has a thickness T ₁ , and the semiconductor layer 104b has a thickness T ₂ . In some embodiments, thickness T ₂ is greater than thickness T _{1 .} The thickness T ₁ may be in a range from about 2 nm to about 6 nm. For example, the thickness T ₁ is about 4 nm. The ratio of thickness T ₁ to thickness T ₂ , T ₁ /T ₂ , may range from about 2/5 to about 2/3.

In some embodiments, each of the semiconductor layers 102a - 102d and 104b - 104d have substantially the same thickness. In some embodiments, each of the semiconductor layers 104b - 104d is thicker than each of the semiconductor layers 102a - 102d. In some other embodiments, each of the semiconductor layers 102a - 102d is thicker than each of the semiconductor layers 104b - 104d.

In some embodiments, semiconductor layers 102a - 102d and semiconductor layers 104a - 104d are made of different materials. In some embodiments, semiconductor layers 102a - 102d are made of or include silicon germanium or germanium, and semiconductor layers 104a - 104d are made of or include silicon.

In some embodiments, semiconductor layers 102a - 102d and semiconductor layers 104a - 104d are formed using multiple epitaxial growth operations. Each of the semiconductor layers 102a-102d and 104a-104d is a selective epitaxial growth (SEG) process, a CVD process (eg, vapor-phase epitaxy (VPE) process). , a low-pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, Or it may be formed using a combination thereof. In some embodiments, semiconductor layers 102a - 102d and semiconductor layers 104a - 104d are grown in-situ in the same process chamber. In some embodiments, growth of semiconductor layers 102a - 102d and growth of semiconductor layers 104a - 104d are performed alternately and sequentially in the same process chamber to complete formation of the semiconductor stack. In some embodiments, the vacuum in the process chamber is not broken before epitaxial growth of the semiconductor stack is achieved.

A hard mask element is then formed over the semiconductor stack to assist in subsequent patterning of the semiconductor stack. According to some embodiments, as shown in FIG. 2B , one or more etching processes are used to pattern the semiconductor stack into fin structures 106A and 106B. As shown in FIG. 2B , the semiconductor stack is partially removed to form a trench 112 . Each of the fin structures 106A and 106B may include semiconductor layers 102a - 102d and 104a - 104d and portions of the semiconductor fins 101A and 101B. The semiconductor substrate 100 may also be partially removed during an etching process to form the fin structures 106A and 106B. The remaining protruding portions of the semiconductor substrate 100 form semiconductor fins 101A and 101B.

Each of the hard mask elements may include a first mask layer 108 and a second mask layer 110 . The first mask layer 108 and the second mask layer 110 may be made of different materials. In some embodiments, the first mask layer 108 is made of a material that has good adhesion to the semiconductor layer 104d. The first mask layer 108 may be made of silicon oxide, germanium oxide, silicon germanium oxide, one or more other suitable materials, or combinations thereof. In some embodiments, the second mask layer 110 is made of a material that has good etch selectivity to the semiconductor layers 102a-102d and 104a-104d. The second layer 108 may be made of silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or combinations thereof.

1A-1B are top views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments. In some embodiments, FIG. 2B is a cross-sectional view of the structure taken along line 2B-2B of FIG. 1A . In some embodiments, the extending directions of the fin structures 106A and 106B are substantially parallel to each other, as shown in FIG. 1A .

As shown in FIG. 2C , an isolation structure 114 is formed to surround a lower portion of the fin structures 106A and 106B, in accordance with some embodiments. In some embodiments, one or more dielectric layers are deposited over the fin structures 106A and 106B and the semiconductor substrate 100 to overfill the trench 112 . The dielectric layer is made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (BSG). It may be made of fluorinated silicate glass (FSG), a low-k material, a porous dielectric material, or one or more other suitable materials, or combinations thereof. The dielectric layer may be formed by a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, one or more other applicable processes, or It may also be deposited using a combination of these.

A planarization process is then used to partially remove the dielectric layer. The hard mask element (including the first mask layer 108 and the second mask layer 110 ) may also function as a stop layer of the planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, one or more other applicable processes, or combinations thereof. One or more etch back processes are then used to partially remove the dielectric layer. As a result, the remainder of the dielectric layer forms the isolation structure 114 . An upper portion of the fin structures 106A and 106B protrudes from a top surface of the isolation structure 114 , as shown in FIG. 2C .

In some embodiments, the etch back process for forming the isolation structure 114 is performed to ensure that the upper surface of the isolation structure 114 is higher than the upper surface of the semiconductor layer 102a, as shown in FIG. 2C . carefully controlled. Accordingly, the sidewalls of the semiconductor layer 102 are protected by the isolation structure 114 . The isolation structure 114 and the semiconductor layer 104a together protect the semiconductor layer 102a to prevent the semiconductor layer 102a from being damaged during subsequent processes.

Thereafter, as shown in FIG. 1B , dummy gate stacks 120A and 120B are formed to extend across the fin structures 106A and 106B, in accordance with some embodiments. In some embodiments, FIG. 2D is a cross-sectional view of the structure taken along line 2D-2D of FIG. 1B . 3A-3N are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments. In some embodiments, FIG. 3A is a cross-sectional view of a structure taken along line 3A-3A of FIG. 1B .

1B , 2D and 3A , dummy gate stacks 120A and 120B are formed to partially cover and extend across fin structures 106A and 106B, in accordance with some embodiments. In some embodiments, dummy gate stacks 120A and 120B wrap around fin structures 106A and 106B. As shown in FIG. 2D , dummy gate stack 120B extends across and wraps around fin structures 106A and 106B.

2D and 3A , each of dummy gate stacks 120A and 120B includes a dummy gate dielectric layer 116 and a dummy gate electrode 118 . The dummy gate dielectric layer 116 may be made of or include silicon oxide. The dummy gate electrode 118 may be made of or include polysilicon. In some embodiments, a dummy gate dielectric material layer and a dummy gate electrode layer are sequentially deposited over the isolation structure 114 and the fin structures 106A and 106B. The dummy gate dielectric material layer and dummy gate electrode layer are then patterned to form dummy gate stacks 120A and 120B.

In some embodiments, hard mask elements including mask layers 122 and 124 are used to assist in the patterning process to form dummy gate stacks 120A and 120B. One or more etching processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer, with the hard mask element as an etch mask. As a result, the remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form the dummy gate dielectric layer 116 and the dummy gate electrode 118 of the dummy gate stacks 120A and 120B, respectively.

As shown in FIG. 3B , spacer layers 126 and 128 are then deposited over the structure shown in FIG. 3A , in accordance with some embodiments. Spacer layers 126 and 128 extend along sidewalls of dummy gate stacks 120A and 120B. Spacer layers 126 and 128 are made of different materials. The spacer layer 126 may be made of a dielectric material having a low dielectric constant. The spacer layer 126 may be made of or include silicon carbide, silicon oxycarbide, silicon oxide, one or more other suitable materials, or combinations thereof. The spacer layer 128 may be made of a dielectric material that can provide more protection to the gate stack during subsequent processes. Spacer layer 128 may have a dielectric constant greater than that of spacer layer 126 . The spacer layer 128 may be made of silicon nitride, silicon oxynitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, one or more other suitable materials, or combinations thereof. The spacer layers 126 and 128 may be deposited sequentially using a CVD process, an ALD process, a physical vapor deposition (PVD) process, one or more other applicable processes, or a combination thereof.

As shown in FIG. 3C , spacer layers 126 and 128 are partially removed, in accordance with some embodiments. One or more anisotropic etching processes may be used to partially remove the spacer layers 126 and 128 . Consequently, the remaining portions of spacer layers 126 and 128 form spacer elements 126' and 128', respectively. Spacer elements 126 ′ and 128 ′ extend along sidewalls of dummy gate stacks 120A and 120B, as shown in FIG. 3C .

Thereafter, the fin structures 106A and 106B are partially removed to form a recess 130 used to contain an epitaxial structure (eg, a source/drain structure) to be formed later. As shown in FIG. 3C , the fin structure 106A is partially removed to form the recess 130 , in accordance with some embodiments. One or more etching processes may be used to form the recess 130 . In some embodiments, a dry etching process is used to form the recess 130 . Alternatively, a wet etching process may be used to form the recess 130 . In some embodiments, each of the recesses 130 passes through the fin structures 106A. In some embodiments, the recess 130 further extends into the semiconductor fin 101A, as shown in FIG. 3C .

In some embodiments, each of the recesses 130 has a beveled sidewall. The upper portion of the recess 130 is larger (or wider) than the lower portion of the recess 130 . In these cases, due to the profile of the recess (eg, 130 ), the upper semiconductor layer (eg, semiconductor layer 104b ) is shorter than the lower semiconductor layer (eg, semiconductor layer 104d ).

However, embodiments of the present disclosure have many modifications. In some other embodiments, the recess 130 has substantially vertical sidewalls. In these cases, due to the profile of the recess 130 , the upper semiconductor layer (eg, semiconductor layer 104d) is substantially as wide as the lower semiconductor layer (eg, semiconductor layer 104b).

As shown in FIG. 3D , the semiconductor layers 102a - 102d are etched laterally, in accordance with some embodiments. As a result, the edges of the semiconductor layers 102a-102d are retreated from the edges of the semiconductor layers 104a-104d. As shown in FIG. 3D , recess 132 is formed due to lateral etching of semiconductor layers 102a - 102d . The recess 132 may be used to contain an inner spacer to be formed later. The semiconductor layers 102a - 102d may be etched in the transverse direction using a wet etch process, a dry etch process, or a combination thereof.

During the lateral etching of the semiconductor layers 102a-102d, the semiconductor layers 104a-104d may also be slightly etched. As a result, the edge portions of the semiconductor layers 104a - 104d are partially etched and thus contracted to become edge elements 105a - 105d, as shown in FIG. 3D . As shown in FIG. 3D , each of the edge elements 105a - 105d of the semiconductor layer 104a - 104d is thinner than a corresponding inner portion. In some embodiments, each of the edge elements 105a is thinner than other upper edge elements, such as edge elements 105b - 105d.

As shown in FIG. 3E , a spacer layer 134 is deposited over the structure shown in FIG. 3D , in accordance with some embodiments. Spacer layer 134 covers dummy gate stacks 120A and 120B and overfills recess 132 . The spacer layer 134 may be made of or include carbon-containing silicon nitride (SiCN), carbon-containing silicon oxynitride (SiOCN), carbon-containing silicon oxide (SiOC), one or more other suitable materials, or combinations thereof. may be The spacer layer 134 may be deposited using a CVD process, an ALD process, one or more other applicable processes, or a combination thereof.

As shown in FIG. 3F , an etching process is used to partially remove the spacer layer 134 , in accordance with some embodiments. The remainder of the spacer layer 134 forms inner spacers 136 , as shown in FIG. 3F . The etching process may include a dry etching process, a wet etching process, or a combination thereof.

The inner spacers 136 cover the edges of the semiconductor layers 102a - 102d originally exposed by the recesses 132 . In some embodiments, after the etching process to form the inner spacers 136 , the portion of the semiconductor fin 101A that is originally covered by the spacer layer 134 is recessed 130 , as shown in FIG. 3F . exposed by The inner spacers 136 may be used to prevent damage to subsequently formed epitaxial structures (eg, functioning as source/drain structures) during a subsequent gate replacement process. The inner spacers 136 may also be used to reduce parasitic capacitance between the subsequently formed source/drain structures and the gate stack.

As shown in FIG. 3G , an epitaxial structure 138 is formed next to the dummy gate stacks 120A and 120B, in accordance with some embodiments. In some embodiments, epitaxial structure 138 fills recess 130 , as shown in FIG. 3G . In some other embodiments, the epitaxial structure 138 overfills the recess 130 . In these cases, the top surface of the epitaxial structure 138 may be higher than the top surface of the dummy gate dielectric layer 116 . In some other embodiments, epitaxial structure 138 partially fills recess 130 .

In some embodiments, epitaxial structure 138 is coupled to semiconductor layers 104a - 104d. Each of the semiconductor layers 104a - 104d is sandwiched between two of the epitaxial structures 138 . In some embodiments, epitaxial structure 138 functions as a source/drain structure. In some embodiments, epitaxial structure 138 is an n-type region. The epitaxial structure 138 may be formed of epitaxially grown silicon, epitaxially grown silicon carbide (SiC), epitaxially grown silicon phosphide (SiP), or other suitable epitaxially grown semiconductor material. may include.

In some embodiments, the epitaxial structure 138 is formed from a selective epitaxial growth (SEG) process, a CVD process (eg, a vapor phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof.

In some embodiments, epitaxial structure 138 is doped with one or more suitable dopants. For example, epitaxial structure 138 is a Si source/drain feature doped with phosphor (P), antimony (Sb), or other suitable dopant.

In some embodiments, epitaxial structures 138 are doped in situ during their epitaxial growth. In some other embodiments, epitaxial structure 138 is undoped during growth of epitaxial structure 138 . Instead, after formation of the epitaxial structure 138 , the epitaxial structure 138 is doped in a subsequent process. In some embodiments, doping is accomplished by using an ion implantation process, a plasma immersion ion implantation process, a gas and/or solid source diffusion process, one or more other applicable processes, or combinations thereof. In some embodiments, epitaxial structure 138 is further exposed to one or more annealing processes to activate dopants. For example, a rapid thermal annealing process is used.

As shown in FIG. 3H , a contact etch stop layer 139 and a dielectric layer 140 are formed to cover the epitaxial structure 138 and to surround the dummy gate stacks 120A and 120B, in accordance with some embodiments. do. The contact etch stop layer 139 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, one or more other suitable materials, or combinations thereof. Dielectric layer 140 is formed of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low-k material, porous It may be made of or include a dielectric material, one or more other suitable materials, or combinations thereof.

In some embodiments, an etch stop material layer and a dielectric material layer are sequentially deposited over the structure shown in FIG. 3G . The etch stop material layer may be deposited using a CVD process, an ALD process, a PVD process, one or more other applicable processes, or a combination thereof. The dielectric material layer may be deposited using a FCVD process, a CVD process, an ALD process, one or more other applicable processes, or a combination thereof.

A planarization process is then used to partially remove the etch stop material layer and the dielectric material layer. As a result, the remaining portions of the etch stop material layer and the dielectric material layer form the contact etch stop layer 139 and the dielectric layer 140 , respectively. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof. In some embodiments, mask layers 122 and 124 are removed during the planarization process. In some embodiments, after the planarization process, the top surfaces of the contact etch stop layer 139 , the dielectric layer 140 , and the dummy gate electrode 118 are substantially coplanar.

2E and 3I , one or more etching processes are used to remove the dummy gate stacks 120A and 120B to form the trench 142 , in accordance with some embodiments. As shown in FIG. 2E , trench 142 exposes semiconductor layers 102b - 102d and 104b - 104d that are originally covered by dummy gate stacks 120A and 120B. In some embodiments, semiconductor layers 102a and 104a remain covered by semiconductor layer 102b and isolation structure 114 without being exposed by trench 142 , as shown in FIG. 2E .

As shown in FIGS. 2F and 3J , semiconductor layers 102b - 102d (functioning as a sacrificial layer) are removed to form recesses 144 , in accordance with some embodiments. In some embodiments, an etching process is used to remove the semiconductor layers 102b - 102d. Due to the high etch selectivity, the semiconductor layers 104a - 104d are substantially unetched (or slightly etched). The remainder of the semiconductor layers 104a - 104d form a number of semiconductor nanostructures 104a' - 104d' of the fin structures 106A and 106B, as shown in FIGS. 2F and 3J . . The semiconductor nanostructures 104a'-104d' are constituted by the remainder of the semiconductor layers 104a-104d.

In some embodiments, the etchant used to remove the semiconductor layers 102b - 102d also slightly removes the semiconductor layers 104a - 104d forming the semiconductor nanostructures 104a ′ - 104d ′. As a result, the obtained semiconductor nanostructures 104a'-104d' become thinner after removal of the semiconductor layers 102b-102d. In some embodiments, each of the semiconductor nanostructures 104b' - 104d' has an edge portion ( 105b-105d).

After removal of the semiconductor layers 102b - 102d (which serve as sacrificial layers), a recess 144 is formed. Recess 144 connects to trench 142 and surrounds each of semiconductor nanostructures 104b'-104d'. As shown in FIG. 3J , even though recesses 144 are formed between semiconductor nanostructures 104a ′ - 104d ′, semiconductor nanostructures 104b ′ - 104d ′ are retained by epitaxial structures 138 . maintain a state of being Thus, after removal of the semiconductor layer 102b-102d (which functions as a sacrificial layer), the detached semiconductor nanostructures 104b'-104d' are prevented from falling off.

During removal of semiconductor layers 102b - 102d (which serve as sacrificial layers), inner spacers 136 prevent epitaxial structures 138 from being etched or damaged. The quality and reliability of semiconductor device structures are improved.

During the removal of the semiconductor layer 102b - 102d (functioning as a sacrificial layer), the semiconductor layer 102a (functioning as a base layer), as shown in FIGS. 2F and 3J , (functioning as a protective layer) covered by nanostructures 104a ′ and isolation structures 114 . As a result, the semiconductor layer 102a is prevented from being etched or damaged.

As shown in FIGS. 2G and 3K , the nanostructures 104a ′ (functioning as a protective layer) are partially removed to expose the semiconductor layer 102a (functioning as a base layer), in accordance with some embodiments. . The nanostructures 104a ′ may be removed using a dry etch process, a wet etch process, or a combination thereof. The semiconductor nanostructures 104b'-104d' may also be slightly etched during removal of the nanostructures 104a'.

After partial removal of the nanostructures 104a ′, each of the edge elements 105a is still held between two of the inner spacers 136 . In some embodiments, each of the remaining edge elements 105a is thinner than each of the semiconductor nanostructures 104b′-104d′, as shown in FIG. 3K . In some embodiments, each of the remaining edge elements 105a has a length that is shorter than a respective length of the semiconductor nanostructures 104b′-104d′, as shown in FIG. 3K .

_{As noted above, in some embodiments as illustrated in FIG. 2A , the thickness T 1} of the semiconductor layer 104a (which later serves as a protective layer for the semiconductor layer 102a ) versus the (later nanostructures) The ratio (T ₁ /T _{2 ) of the thickness T 2} of the semiconductor layer 104b (becoming 104b′) may range from about 2/5 to about 2/3. In some cases, if the thickness ratio (T ₁ /T ₂ ) is lower than about 2/5, the semiconductor layer 104a with the _{thickness (T 1 ) may be too thin.} As a result, during the removal of the semiconductor layers 102b - 102d (which serve as sacrificial layers) as illustrated in FIGS. 2F and 3J , the semiconductor layer 104a is such that the underlying semiconductor layer 102a is etched away. It may be completely removed or destroyed to expose it. The semiconductor layer 102a may be damaged. In some other cases, if the thickness ratio (T ₁ /T ₂ ) is greater than about 2/3, the _{semiconductor layer 104a having the thickness (T 1} ) may be too thick. Consequently, during the partial removal of the nanostructures 104a' (functioning as a protective layer) to expose the semiconductor layer 102a as illustrated in FIGS. 2G and 3K, the semiconductor nanostructures 104b'-104d' ) may be consumed too much, as a more intensive etching process may be used for partial removal of the thick nanostructures 104a'. The performance of the semiconductor device structure may be adversely affected.

As shown in FIGS. 2H and 3L , the semiconductor layer 102a (which serves as a base layer) is converted to a stressor structure 146 , according to some embodiments. In some embodiments, the entirety of semiconductor layer 102a is converted to stressor structure 146 . As shown in FIG. 2H , the stressor structure 146 is surrounded by an isolation structure 114 . In some embodiments, one of the inner spacers 136 (eg, the bottommost inner spacer 136 ) has a nearby stressor structure 146 and an epitaxial structure 138 , as shown in FIG. 3L . in direct contact with

In some embodiments, the stressor structure 146 is formed by oxidizing the semiconductor layer 102a. Thermal operation may be used to form the stressor structure 146 . The thermal operation may be performed at a temperature ranging from about 400 degrees Celsius to about 850 degrees Celsius. The thermal operating time may range from about 0.5 hours to about 4 hours. The thermal operation may be performed under an oxygen containing atmosphere. The oxygen-containing atmosphere may include oxygen gas or a gas mixture including oxygen gas and hydrogen gas.

After a thermal operation, the semiconductor layer 102a may "expand" and transform into a stressor structure 146 made of a semiconductor oxide material. The stressor structure 146 may include a semiconductor material other than oxygen and silicon (eg, germanium). The stressor structure 146 may be made of or include silicon germanium oxide, germanium oxide, one or more other suitable materials, or combinations thereof. In some embodiments, each of the stressor structures 146 is made thicker than the original semiconductor layer 102a that has not yet been converted to the stressor structures 146 . In some embodiments, the top surface of the stressor structure 146 is at a higher level than that of the semiconductor layer 102a. In some embodiments, the top surface of the stressor structure 146 is substantially as high as the top surface of the edge element 105a.

The compressive stress from the stressor structure 146 to the epitaxial structure 138 is such that due to the expansion generated during the transition from the semiconductor layer 102a to the stressor structure 146 , the epitaxial structure 138 may be slightly pushed. may be authorized. In response, a tensile stress may be applied from the epitaxial structure 138 to the semiconductor nanostructures 104b ′ - 104d ′ that function as channel structures. As a result, electron carrier mobility may be increased. Accordingly, the performance of the semiconductor device structure is greatly improved. In some embodiments, the semiconductor nanostructures 104b'-104d' function as a channel structure of an n-type MOSFET.

During the thermal operation to form the stressor structure 146 , surface portions of the semiconductor nanostructures 104b′-104d′ are also oxidized to oxide elements, as shown in FIGS. 2H and 3L in accordance with some embodiments. 148) may be formed. Oxide element 148 may be made of a different material than that of stressor structure 146 . Oxide element 148 may be made of or include silicon oxide, germanium oxide, one or more other suitable materials, or combinations thereof.

As shown in FIGS. 2I and 3M , oxide element 148 is removed, in accordance with some embodiments. After removal of oxide element 148 , semiconductor nanostructures 104b′ - 104d′ may become thinner. Oxide element 148 may be removed using an etching process. The etching process may also partially remove the stressor structure 146 . Consequently, as shown in FIG. 3M in accordance with some embodiments, the top surface of the stressor structure 146 is at a height level that is between the top and bottom surfaces of the edge element 105a. In some embodiments, the top surface of the stressor structure 146 is at a lower elevation level than the top surface of the isolation structure 114 , as shown in FIG. 2I . The stressor structure 146 may have a thickness ranging from about 10 nm to about 40 nm.

2J and 3N , metal gate stacks 156A and 156B are formed to fill trench 142 , in accordance with some embodiments. Metal gate stacks 156A and 156B extend into recess 144 to wrap around each of semiconductor nanostructures 104b'-104d'. In some embodiments, as shown in FIGS. 2J and 3N , each of the stressor structures 146 includes a corresponding semiconductor fin 101A or 101B, an isolation structure 114 , and a corresponding metal gate stack 156A or 156B. ) in direct contact with

Each of the metal gate stacks 156A and 156B includes a plurality of metal gate stack layers. Each of the metal gate stacks 156A and 156B may include a gate dielectric layer 150 , a work function layer 152 , and a conductive filling 154 . In some embodiments, the formation of the metal gate stacks 156A and 156B involves the deposition of multiple metal gate stack layers over the dielectric layer 140 to fill the trenches 142 . A metal gate stack layer extends into the recess 144 to wrap around each of the semiconductor nanostructures 104b'-104d'.

In some embodiments, the gate dielectric layer 150 is made of or includes a dielectric material having a high-K dielectric constant. The gate dielectric layer 150 is made of hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide. , hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-k materials, or combinations thereof may be made of or may include them. The gate dielectric layer 150 may be deposited using an ALD process, a CVD process, one or more other applicable processes, or a combination thereof.

In some embodiments, prior to the formation of the gate dielectric layer 150 , an interfacial layer is formed on the surface of the semiconductor nanostructures 104b ′ - 104d ′. The interfacial layer is very thin and is made of, for example, silicon oxide or germanium oxide. In some embodiments, the interfacial layer is formed by applying an oxidizing agent on the surface of the semiconductor nanostructures 104b'-104d'. For example, a hydrogen peroxide containing liquid may be applied or provided on the surface of the semiconductor nanostructures 104b'-104d' to form an interfacial layer.

The work function layer 152 may be used to provide a desired work function to the transistor to improve device performance including improved threshold voltage. In some embodiments, the work function layer 152 is used to form an NMOS device. The work function layer 152 is an n-type work function layer. An n-type work function layer may provide a work function value suitable for the device, equal to or less than about 4.5 eV.

The n-type work function layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function layer comprises titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or combinations thereof. In some embodiments, the n-type work function is an aluminum-containing layer. The aluminum-containing layer may be made of or include TiAlC, TiAlO, TiAlN, one or more other suitable materials, or combinations thereof.

The work function layer 152 may also include hafnium, zirconium, titanium, tantalum, aluminum, metal carbide (eg, hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminide, ruthenium, palladium, platinum, cobalt, It may be made of or include nickel, a conductive metal oxide, or a combination thereof. The thickness and/or composition of the work function layer 152 may be fine-tuned to adjust the work function level.

The work function layer 152 may be deposited over the gate dielectric layer 150 using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof. there is.

In some embodiments, a barrier layer is formed prior to the work function layer 152 to interface the gate dielectric layer 150 with a subsequently formed work function layer 152 . A barrier layer may also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed work function layer 152 . The barrier layer may be made of or include a metal containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or combinations thereof. The barrier layer may be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

In some embodiments, the conductive filler 154 is made of or includes a metallic material. The metallic material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or combinations thereof. The conductive layer used to form the conductive fill 154 may be formed using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, a spin coating process, one or more other applicable processes, or combinations thereof. Thus, it may be deposited on the work function layer 152 .

In some embodiments, a blocking layer is formed over the work function layer 152 prior to formation of the conductive layer used to form the conductive fill 154 . A barrier layer may be used to prevent a subsequently formed conductive layer from diffusing or penetrating into the work function layer 152 . The barrier layer may be made of or include tantalum nitride, titanium nitride, one or more other suitable materials, or combinations thereof. The barrier layer may be deposited using an ALD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

A planarization process is then performed to remove portions of the metal gate stack layer outside the trench 142 , in accordance with some embodiments. As a result, the remainder of the metal gate stack layer forms metal gate stacks 156A and 156B, as shown in FIGS. 2J and 3N . In some embodiments, the conductive fill 154 does not extend into the recess 144 because the recess 144 is small and filled with other elements, such as the gate dielectric layer 150 and the work function layer 152 . However, embodiments of the present disclosure are not limited thereto. In some other embodiments, a portion of the conductive fill 154 extends into the recess 144 , particularly in the case of the lower recess 144 , which may have a larger space.

In some embodiments, epitaxial structure 138 extends beyond a top surface of stressor structure 146 . In some embodiments, epitaxial structure 138 extends beyond the interface between stressor structure 146 and metal gate stack 156A or 156B. In some embodiments, the epitaxial structure 138 further extends beyond the bottom surface of the stressor structure 146 . Accordingly, the stressor structure 146 may more readily apply a compressive stress to the epitaxial structure 138 . Accordingly, the epitaxial structure 138 may correspondingly apply a tensile stress to the semiconductor nanostructures 104b'-104d', which may function as channel structures. The performance of the semiconductor device structure is greatly improved.

In some embodiments, the top surface of the stressor structure 146 is between the top surface and the bottom surface of the edge element 105a , as shown in FIG. 3N . However, embodiments of the present disclosure are not limited thereto. Many variations and/or modifications may be made to embodiments of the present disclosure.

4A and 4B are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 4A , a structure similar to that shown in FIG. 3L is formed or accommodated. In some embodiments, the stressor structure 146 extends beyond the top surface of the edge element 105a, as shown in FIG. 4A . A process similar to that illustrated in FIGS. 3M and 3N is then performed. As a result, a semiconductor device structure as shown in FIG. 4B is formed, in accordance with some embodiments. As shown in FIG. 4B , the top surface of the stressor structure 146 is higher than the top surface of the edge element 105a.

Many variations and/or modifications may be made to embodiments of the present disclosure. 5 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments, the top surface of the stressor structure 146 is substantially level with the top surface of the edge element 105a.

Many variations and/or modifications may be made to embodiments of the present disclosure. 6 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments, the top surface of the stressor structure 146 is lower than the bottom surface of the edge element 105a.

In some embodiments, each of the edge elements 105a is sandwiched between two of the inner spacers 136 . In some embodiments, each of the edge elements 105a is not connected to a channel structure, as shown in FIG. 3N . Each of the edge elements 105a is thinner than the edge elements 105b, 105c or 105d.

However, embodiments of the present disclosure are not limited thereto. Many variations and/or modifications may be made to embodiments of the present disclosure. In some other embodiments, the semiconductor device structure does not include an edge element 105a.

7A-7C are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 7A , a structure identical or similar to the structure shown in FIG. 3C is formed or accommodated.

As shown in FIG. 7B , a process the same or similar to the process illustrated in FIG. 3D is performed to etch the semiconductor layers 102a - 102d in the transverse direction to form the recess 132 , in accordance with some embodiments. do. As noted above, during the lateral etching of semiconductor layers 102a - 102d, edge portions of semiconductor layer 104a may also be etched. In some embodiments, the semiconductor layer 104a is very thin. As a result, the edge portion of the semiconductor layer 104 is completely removed (or consumed) during the lateral etching of the semiconductor layers 102a - 102d . No edge portion of the semiconductor layer 104 protrudes from the sidewalls of the semiconductor layers 102a and 102b to form an edge element. Comparing the embodiment shown in FIGS. 7B and 3D , one of the differences is that the embodiment illustrated in FIG. 7B does not have an edge element 105a .

Thereafter, the same or similar process as illustrated in FIGS. 3E to 3N is performed. As a result, the structure shown in FIG. 7C is formed, in accordance with some embodiments.

In some embodiments, as shown in FIGS. 3K and 3L , the entirety of semiconductor layer 102a is oxidized and converted to stressor structure 146 . However, embodiments of the present disclosure are not limited thereto. Many variations and/or modifications may be made to embodiments of the present disclosure. In some other embodiments, the semiconductor layer 102a is partially oxidized and/or converted to the stressor structure 146 . In some embodiments, an upper portion of the semiconductor layer 102a is oxidized and/or converted to the stressor structure 146 , while a lower portion of the semiconductor layer 102a remains unoxidized and/or converted.

8A-8C are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 8A , a structure identical or similar to the structure shown in FIG. 3K is formed or accommodated.

Thereafter, similar to the process illustrated in FIG. 3L , the semiconductor layer 102a is oxidized, as shown in FIG. 8B in accordance with some embodiments. In some embodiments, an upper portion of semiconductor layer 102a is oxidized and/or converted to stressor structure 146 . The lower portion of the semiconductor layer 102a is not oxidized and/or is not converted to the stressor structure 146 . The partial oxidation of the semiconductor layer 102a may be fine-tuned by adjusting the thermal operating temperature, thermal operating time, and/or thermal operating atmosphere. The lower portion of the semiconductor layer 102a that remains unoxidized forms the semiconductor element 102a', as shown in FIG. 8B . In some embodiments, each of the semiconductor elements 102a ′ is in direct contact with a corresponding stressor structure 146 thereon. In some embodiments, the interface between one of the semiconductor elements 102a ′ and one of the stressor structures 146 is substantially planar. The semiconductor element 102a ′ may have a thickness in a range from about 2 nm to about 20 nm. The stressor structure 146 thereon may have a thickness in the range from about 5 nm to about 20 nm.

Thereafter, the same or similar process as illustrated in FIGS. 3M and 3N is performed. As a result, the structure shown in FIG. 8C is formed, in accordance with some embodiments.

9 is a cross-sectional view of a semiconductor device structure in accordance with some embodiments. In some embodiments, FIG. 9 is another cross-sectional view of the structure shown in FIG. 8C when cut along a different direction. In some embodiments, FIG. 9 is a cross-sectional view taken along a longer gate extension direction. In some embodiments, each of the semiconductor elements 102a ′ is disposed between a corresponding stressor structure 146 and the semiconductor substrate 100 , as shown in FIG. 9 . In some embodiments, each of the semiconductor elements 102a ′ is in direct contact with a corresponding stressor structure 146 thereon, an isolation structure 114 , and/or a corresponding semiconductor fin 101A or 101B below it. do.

In some embodiments, the interface between each of the stressor structures 146 and the corresponding semiconductor element 102a ′ beneath it is substantially planar, as shown in FIGS. 8C and 9 . However, embodiments of the present disclosure are not limited thereto. Many variations and/or modifications may be made to embodiments of the present disclosure. In some other embodiments, the interface between each of the stressor structures 146 and the corresponding semiconductor element 102a' below it is curved or has a curved portion.

10 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. The profile of the stressor structure 146 and the semiconductor element 102a ″ below it may be modified by fine-tuning the thermal operation. For example, the thermal operating temperature, thermal operating time, and/or thermal operating atmosphere may be It may be adjusted to modify the profile of the stressor structure 146 .

In some embodiments, the bottom of the stressor structure 146 is curved, as shown in FIG. 10 . In some embodiments, the interface between the stressor structure 146 and the semiconductor element 102a ″ below it is a convex surface facing the semiconductor element 102a ″.

11 is a cross-sectional view of a semiconductor device structure in accordance with some embodiments. In some embodiments, FIG. 11 is another cross-sectional view of the structure shown in FIG. 10 when cut along a different direction. In some embodiments, FIG. 11 is a cross-sectional view taken along a longer direction of gate extension. In some embodiments, each of the semiconductor elements 102a″ is disposed between a corresponding stressor structure 146 and the semiconductor substrate 100, as shown in FIG. 11. In some embodiments, the semiconductor element 102a ") directly contact the corresponding stressor structure 146 thereon, the isolation structure 114, and/or the corresponding semiconductor fin 101A or 101B below it.

12 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. 13 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments, FIG. 13 is another cross-sectional view of the structure shown in FIG. 12 when cut along a different direction. For example, FIG. 12 shows a “fin cut” cross-sectional view of a semiconductor device structure, and FIG. 13 shows a “gate cut” cross-sectional view of a semiconductor device structure. In some embodiments, there are multiple semiconductor elements 102a″″. Each of the semiconductor elements 102a ″″ may be surrounded by a corresponding stressor structure 146 and a corresponding inner spacer 136 . In some embodiments, the stressor structure 146 is in direct contact with the corresponding semiconductor fin 101A or 101B underneath it, as shown in FIGS. 12 and 13 . In some embodiments, the stressor structure 146 and the bottom surface of the semiconductor element 102a″″ are substantially horizontal to each other, as shown in FIGS. 12 and 13 .

In some embodiments, the bottom of epitaxial structure 138 is formed directly on a semiconductor material, such as semiconductor fin 101A or 101B. However, embodiments of the present disclosure are not limited thereto. Many variations and/or modifications may be made to embodiments of the present disclosure. In some other embodiments, another element not made of a semiconductor material is formed between the bottom of the epitaxial structure 138 and the semiconductor substrate 100 .

14A-14C are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 14A , a structure identical or similar to the structure shown in FIG. 3D is formed or accommodated. A spacer layer 134 ′ is then deposited, as shown in FIG. 14A , in accordance with some embodiments. The material and method of forming the spacer layer 134 ′ may be the same as or similar to the spacer layer 134 , as illustrated in FIG. 3E . In some embodiments, the bottom portion of the spacer layer 134 ′ shown in FIG. 14A is thicker than the bottom portion of the spacer layer 134 shown in FIG. 3E . The profile of the recess 130 and/or the deposition process of the spacer layer 134' may cause the spacer layer 134' to have a thicker bottom portion.

Thereafter, the same or similar process to the process illustrated in FIG. 3F is performed. As a result, the structure shown in FIG. 14B is formed, in accordance with some embodiments. As shown in FIG. 14B, similar to FIG. 3F, an inner spacer 136 and a bottom inner spacer 136' are formed. In some embodiments, the bottom inner spacer 136 ′ covers the bottom portion of the recess 130 , as shown in FIG. 14B . A portion of one of the bottom inner spacers 136 ′ at the bottom of the corresponding recess 130 may have a thickness ranging from about 2 nm to about 10 nm.

Thereafter, the same or similar process to the process illustrated in FIGS. 3G to 3N is performed. As a result, the structure shown in FIG. 14C is formed, in accordance with some embodiments. The bottom spacer 136 ′ may help reduce or prevent current leakage from the epitaxial structure 138 . In some embodiments, each of the bottom inner spacers 136 ′ is in direct contact with a corresponding epitaxial structure 138 thereon. In some embodiments, each of the bottom inner spacers 136 ′ has a corresponding epitaxial thereon such that the entirety of the corresponding epitaxial structure 138 is over the bottom inner spacer 136 ′, as shown in FIG. 14C . It surrounds the bottom of the taxial structure 138 .

Many variations and/or modifications may be made to embodiments of the present disclosure. 15 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments, the epitaxial structure 138 is formed using an epitaxial growth process. In an epitaxial growth process, a semiconductor material may tend to grow on the surface of an element made of the semiconductor material. In an epitaxial growth process, semiconductor material may tend to grow on the surface of edge elements 105a - 105d. As a result, a void V is formed between the epitaxial structure 138 and the semiconductor substrate 100 , as shown in FIG. 15 , in accordance with some embodiments.

16 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. A structure similar to the structure shown in FIG. 15 is formed. Similar to the embodiment illustrated in FIGS. 8C , 10 and 12 , there is a semiconductor element 102a ′ that remains unconverted to the stressor structure 146 . In some embodiments, one of the bottom inner spacers 136 ′ is in direct contact with the stressor structure 146 and the semiconductor element 102a ′, as shown in FIG. 16 .

Many variations and/or modifications may be made to embodiments of the present disclosure. 17A-17C are cross-sectional views of various steps of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 17A , the same or similar structure as shown in FIG. 3K is formed.

Then, similar to the embodiment illustrated in FIG. 3L , the semiconductor layer 102a (functioning as a base layer) is converted into a stressor structure 146 , according to some embodiments. In some embodiments, the semiconductor layer 102a is annealed to form the stressor structure 146 . In some embodiments, after the annealing operation, the semiconductor layer 102a expands and transforms into the stressor structure 146 . The top surface of the stressor structure 146 may protrude and have a mesa-like profile. In some embodiments, the stressor structure 146 has a curved top surface, as shown in FIG. 17B .

Thereafter, the same or similar process as illustrated in FIGS. 3M and 3N is performed, according to some embodiments. As a result, the structure shown in Fig. 17C is formed.

In some embodiments, three semiconductor nanostructures 104b'-104d' are formed. However, embodiments of the present disclosure are not limited thereto. Many variations and/or modifications may be made to embodiments of the present disclosure. In some embodiments, the total number of semiconductor nanostructures is greater than three. In some other embodiments, the total number of semiconductor nanostructures is less than three. The total number of semiconductor nanostructures (or channel structures) in each semiconductor device structure may be adjusted according to requirements.

Embodiments of the present disclosure form a semiconductor device structure having a stressor structure under a channel structure. The channel structure is wrapped by a gate stack. For example, a semiconductor device structure includes a stack of multiple channel structures wrapped by a metal gate stack. The semiconductor element below the channel structure is converted to a stressor structure prior to formation of the gate stack. The stressor structure may include an epitaxial structure next to the channel structure to apply a stress (eg, tensile stress) to the channel structure. As a result, carrier mobility in the channel structure may be improved. The performance and reliability of semiconductor device structures are greatly improved.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a plurality of semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is interspersed with epitaxial structures. The semiconductor device structure also includes a gate stack that wraps around the semiconductor nanostructure. The semiconductor device structure further includes a stressor structure between the gate stack and the substrate. The epitaxial structure extends beyond the top surface of the stressor structure.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and a plurality of channel structures stacked over the semiconductor fin. The semiconductor device structure also includes an epitaxial structure adjacent the channel structure and a gate stack that wraps around each of the channel structures. The semiconductor device structure further includes a stressor structure between the substrate and the channel structure. The stressor structure contains a semiconductor material other than oxygen and silicon.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a base layer over a semiconductor substrate and forming a semiconductor stack over the base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers arranged alternately. The method also includes patterning the semiconductor stack and the base layer to form the fin structure and forming the isolation structure to surround a lower portion of the fin structure. The upper surface of the isolation structure is higher than the upper surface of the base layer. The method further includes removing the sacrificial layer to isolate the plurality of semiconductor nanostructures constituted by the remainder of the semiconductor layer. The method also includes converting an upper portion or all of the base layer into a stressor structure. The method also includes forming a metal gate stack to wrap around each of the semiconductor nanostructures.

The foregoing outlines features of various embodiments that may enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art will recognize that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. have to recognize Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. have to recognize

Example

1. A semiconductor device structure comprising:

a plurality of semiconductor nanostructures on the substrate;

two epitaxial structures on the substrate, each of the semiconductor nanostructures between the epitaxial structures;

a gate stack wrapping around the semiconductor nanostructure; and

and a stressor structure between the gate stack and the substrate, the epitaxial structure extending beyond a top surface of the stressor structure.

2. according to clause 1,

and the gate stack wraps around each of the semiconductor nanostructures.

3. according to clause 1,

wherein the stressor structure is made of a semiconductor oxide material.

4. Clause 1,

and the epitaxial structure extends beyond a bottom surface of the stressor structure.

5. according to clause 1,

and a plurality of inner spacers, each of the inner spacers between the gate stack and the epitaxial structure of one of the epitaxial structures.

6. according to claim 5,

and one of the inner spacers is in direct contact with one of the stressor structure and the epitaxial structure.

7. according to item 5,

and the bottom inner spacer of the inner spacer surrounds the bottom of one of the epitaxial structures such that the entirety of the epitaxial structure is over the bottom inner spacer.

8. Item 5,

and an edge element between two of the inner spacers, wherein the edge element and the semiconductor nanostructure are made of the same material, and wherein the edge element is thinner than each of the semiconductor nanostructures.

9. Item 1,

and a semiconductor element between the stressor structure and the substrate, wherein the semiconductor element is made of a semiconductor material, and wherein the stressor structure is made of an oxide material of the semiconductor material.

10. Item 9,

and the semiconductor element is in direct contact with the stressor structure.

11. A semiconductor device structure comprising:

semiconductor fins on the substrate;

a plurality of channel structures stacked on the semiconductor fins;

a gate stack wrapping around each of the channel structures;

an epitaxial structure in contact with the channel structure; and

and a stressor structure between the substrate and the channel structure, wherein the stressor structure contains a semiconductor material other than oxygen and silicon.

12. Clause 11,

and an isolation structure surrounding the semiconductor fin and the stressor structure.

13. Clause 12,

and the stressor structure is in direct contact with the semiconductor fin, the isolation structure, and the gate stack.

14. Clause 11,

A semiconductor device structure, further comprising a semiconductor element between the stressor structure and the substrate, wherein an interface between the semiconductor element and the stressor structure is a convex surface facing the semiconductor element.

15. A method for forming a semiconductor device structure comprising:

forming a base layer over the semiconductor substrate;

forming a semiconductor stack over the base layer, the semiconductor stack having a plurality of alternating sacrificial layers and a plurality of semiconductor layers;

patterning the semiconductor stack and the base layer to form a fin structure;

forming an isolation structure to surround a lower portion of the fin structure, the upper surface of the isolation structure being higher than the upper surface of the base layer;

removing the sacrificial layer to release a plurality of semiconductor nanostructures constituted by the remainder of the semiconductor layer;

converting at least an upper portion of the base layer into a stressor structure; and

and forming a metal gate stack to wrap around each of the semiconductor nanostructures.

16. Clause 15,

forming a protective layer over the base layer before the semiconductor stack is formed; and

and partially removing the protective layer after the semiconductor nanostructure is formed such that the base layer is exposed.

17. Clause 16,

wherein the material of the protective layer and the semiconductor layer is the same, and the material of the base layer and the sacrificial layer are the same.

18. Clause 15,

wherein the stressor structure is formed by at least partially oxidizing the base layer.

19. Item 18,

and a lower portion of the base layer is not converted to the stressor structure.

20. Clause 15,

forming a recess exposing side surfaces of the semiconductor layer and the sacrificial layer by partially removing the fin structure;

forming an inner spacer to cover the side surface of the sacrificial layer; and

and forming a source/drain structure to at least partially fill the recess after the inner spacer is formed.

Claims (10)

A semiconductor device structure comprising:
a plurality of semiconductor nanostructures on the substrate;
two epitaxial structures on the substrate, each of the semiconductor nanostructures between the epitaxial structures;
a gate stack wrapping around the semiconductor nanostructure; and
and a stressor structure between the gate stack and the substrate, the epitaxial structure extending beyond a top surface of the stressor structure. According to claim 1,
and the gate stack wraps around each of the semiconductor nanostructures. According to claim 1,
wherein the stressor structure is made of a semiconductor oxide material. According to claim 1,
and the epitaxial structure extends beyond a bottom surface of the stressor structure. According to claim 1,
and a plurality of inner spacers, each of the inner spacers between the gate stack and the epitaxial structure of one of the epitaxial structures. According to claim 1,
and a semiconductor element between the stressor structure and the substrate, wherein the semiconductor element is made of a semiconductor material, and wherein the stressor structure is made of an oxide material of the semiconductor material. A semiconductor device structure comprising:
semiconductor fins on the substrate;
a plurality of channel structures stacked on the semiconductor fins;
a gate stack wrapping around each of the channel structures;
an epitaxial structure in contact with the channel structure; and
and a stressor structure between the substrate and the channel structure, wherein the stressor structure contains a semiconductor material other than oxygen and silicon. A method for forming a semiconductor device structure comprising:
forming a base layer over the semiconductor substrate;
forming a semiconductor stack over the base layer, the semiconductor stack having a plurality of alternating sacrificial layers and a plurality of semiconductor layers;
patterning the semiconductor stack and the base layer to form a fin structure;
forming an isolation structure to surround a lower portion of the fin structure, the upper surface of the isolation structure being higher than the upper surface of the base layer;
removing the sacrificial layer to release a plurality of semiconductor nanostructures constituted by the remainder of the semiconductor layer;
converting at least an upper portion of the base layer into a stressor structure; and
and forming a metal gate stack to wrap around each of the semiconductor nanostructures. 9. The method of claim 8,
forming a protective layer over the base layer before the semiconductor stack is formed; and
and partially removing the protective layer after the semiconductor nanostructure is formed such that the base layer is exposed. 9. The method of claim 8,
forming a recess exposing side surfaces of the semiconductor layer and the sacrificial layer by partially removing the fin structure;
forming an inner spacer to cover the side surface of the sacrificial layer; and
and forming a source/drain structure to at least partially fill the recess after the inner spacer is formed.

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