KR102263766B1 - Analog digital converting device for converting image signal - Google Patents

Abstract

The present invention provides an analog-to-digital converter having an analog-to-digital converter and a digital arithmetic unit. The analog-to-digital calculator converts an image signal input from the outside into a digital signal composed of a DC voltage and outputs it. The digital calculator is connected to the analog-to-digital converter, and calculates and outputs a difference between adjacent voltages among a plurality of voltages output from the analog-to-digital converter.

Description

Analog digital converting device for converting image signal}

The present invention relates to an analog-to-digital conversion apparatus, and more particularly, to an analog-to-digital conversion apparatus for converting an image signal into a digital signal.

An analog digital converter converts an analog signal into a digital signal. The analog-to-digital converter is essentially used in an apparatus for processing a digital signal, for example, an apparatus that receives an optical signal from the outside, such as an image sensor, converts it into a digital signal and processes it inside. That is, the image sensor includes a pixel array for receiving an optical signal, and an analog-to-digital converter for each column of the pixel array to read a large amount of data at high speed.

The image sensor adds a capacitor to remove noise, flicker noise, and analog digital offset voltage of the initial voltage of the pixel output, and stores the initial voltage of the pixel output and the offset voltage of the comparator in the added capacitor.

Reference document (Korean Patent Application Laid-Open No. 2011-0104178) discloses a converter for converting an analog signal into a digital signal by having a capacitor array.

An object of the present invention is to provide an analog-to-digital conversion device that does not include a separate capacitor to store an output voltage of a pixel and an offset voltage of a comparator.

The present invention in order to solve the above problems,

an analog-to-digital converter that converts an image signal input from the outside into a digital signal composed of a DC voltage and outputs the converted video signal; and a digital calculation unit connected to the analog-to-digital conversion unit to calculate and output a difference between adjacent voltages among a plurality of voltages output from the analog-to-digital conversion unit.

The analog-to-digital converter may include: a comparator having a first input terminal and a second input terminal to which the image signal is applied, and comparing the image signal with a voltage inputted to the second input terminal; a feedback unit connected between the output terminal of the comparator and the second input terminal and configured to feed back the output voltage of the comparator to the second input terminal according to a feedback control signal; a digital-to-analog converter connected to a first reference voltage, a second reference voltage, and the second input terminal, and selectively outputting the first reference voltage and the second reference voltage to the second input terminal; and a logic unit connected to the output terminal of the comparator and the digital-to-analog converter, and configured to cause the digital-to-analog converter to select one of the first reference voltage and the second reference voltage according to the comparison result of the comparator. desirable.

The digital-to-analog converter may include: a plurality of capacitors whose ends are connected to the second input terminal; and a plurality of switching elements respectively connected to the other ends of the plurality of capacitors, connected to the first reference voltage and the second reference voltage, and connected to the logic unit, wherein the plurality of switching elements are connected to the logic unit. It is preferable to connect the plurality of capacitors to the first reference voltage or the second reference voltage.

As described above, according to the present invention, the analog-to-digital conversion device does not include a separate capacitor to store the output voltage of the pixel and the offset voltage of the comparator. Accordingly, the area occupied by the separate capacitor and the convergence time of the pixel output voltage may be reduced. In addition, the digital-to-analog converter stores the initial voltage of the image signal output from the pixel and the offset voltage of the comparator. Due to this, the error voltage generated because the output voltage of the digital-to-analog converter does not sufficiently converge within a given time due to the limitation of the driving capability of the buffer for supplying the first reference voltage and the resistance of the transmission line for transmitting the first reference voltage is the logic. This is removed by negative operation, and accordingly, the time required for the digital-to-analog converter to store the initial voltage of the image signal output from the pixel and the offset voltage of the comparator may be reduced. Therefore, the analog-to-digital converter according to the present invention is easy to manufacture a small-area high-speed readout circuit for CIS incorporating a column parallel SAR analog-to-digital converter.

1 is a block diagram of an analog-to-digital conversion apparatus according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of the analog-to-digital converter shown in FIG. 1 .
3 is a block diagram of a column parallel SAR analog-to-digital converter.
FIG. 4 is a circuit diagram illustrating an example of a pixel that supplies an image signal to the analog-to-digital converter shown in FIG. 1 .
FIG. 5 is a waveform diagram of the signals shown in FIG. 2 .
6 to 9 are circuit diagrams for explaining an analog-to-digital conversion operation performed by the analog-to-digital converter shown in FIG. 2 .

Hereinafter, with reference to the accompanying drawings, an embodiment of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention. The same reference numerals among the reference numerals shown in the respective drawings indicate the same members.

1 is a block diagram of an analog-to-digital conversion apparatus according to an embodiment of the present invention. Referring to FIG. 1 , an analog-to-digital conversion apparatus 100 according to an embodiment of the present invention includes an analog-to-digital conversion unit 110 and a digital operation unit 120 .

The analog-to-digital converter 110 receives the image signal PIX_out input from the outside, for example, the image signal PIX_out output from the pixel (400 of FIG. 4) of the image sensor, converts it into a digital signal Dout, and outputs it do. The image signal PIX_out output from the pixel is an analog signal generated by converting light incident from the outside into an electric signal. The analog-to-digital converter 110 includes a Successive Approximation Register (SAR) analog-to-digital converter. Since the SAR analog-to-digital converter converts one bit to digital at one time, the conversion speed is fast and power consumption is small.

The digital calculator 120 calculates a difference between two adjacent digital signals among the digital signals Dout output from the analog-to-digital converter 110 . That is, the digital calculator 120 calculates the difference between the initial voltage and the signal voltage included in the image signal PIX_out output through the analog-to-digital converter 110 . The digital operation unit 120 is preferably composed of digital CDS logic that performs correlated double sampling (hereinafter, referred to as CDS). Since the analog-to-digital conversion apparatus 100 includes the digital CDS logic, noise, flicker noise, and offset of an initial voltage of a pixel of an image sensor, for example, a CMOS image sensor (CIS) may be removed.

FIG. 2 is a circuit diagram of the analog-to-digital converter 110 shown in FIG. 1 . Referring to FIG. 2 , the analog-to-digital converter 110 includes a comparator 111 , a feedback part 112 , a digital-to-analog converter 113 , and a logic part 114 .

The comparator 111 is connected to the pixel ( 400 in FIG. 4 ) and the digital operation unit 120 . Specifically, the comparator 111 has a first input terminal and a second input terminal. The first input terminal is connected to the pixel ( 400 in FIG. 4 ), the second input terminal is connected to the digital-to-analog converter 113 , and the output terminal of the comparator 111 is connected to the digital operation unit 120 . Accordingly, the comparator 111 compares the voltage of the image signal PIX_out output from the pixel ( 400 in FIG. 4 ) with the output voltage of the digital-to-analog converter 113 , and transmits the result to the digital operation unit 120 . .

The analog-to-digital converter 110 converts the initial voltage VRST and the signal voltage VSIG of the pixel ( 400 of FIG. 4 ) output from the pixel ( 400 of FIG. 4 ) into digital signals, respectively.

The feedback unit 112 is connected between the output terminal of the comparator 111 and the second input terminal. The feedback unit 112 is activated or deactivated in response to the feedback control signal EN_DAC_RST. When the feedback unit 112 is activated, the second input terminal of the comparator 111 is electrically connected to the output terminal, and when the feedback unit 112 is deactivated, the second input terminal of the comparator 111 is electrically connected to the digital-to-analog converter 113 . is connected to The feedback unit 112 includes a switch that is turned on or off in response to the feedback control signal EN_DAC_RST. For example, when the feedback control signal EN_DAC_RST is logic high, the switch is turned on, and when the feedback control signal EN_DAC_RST is logic low, the switch is turned off.

The digital-to-analog converter 113 is connected to the second input terminal of the comparator 111 , the feedback unit 112 , and the logic unit 114 . The digital-to-analog converter 113 includes a base capacitor C0, a plurality of capacitors C-2 ^N-1 C, and a plurality of switching elements S-2 ^N-1 S. . One end of the base capacitor C0 is connected to the second input terminal of the comparator 111, and the other end is grounded. One ends of the plurality of capacitors C to 2 ^N-1 C are connected to the second input terminal of the comparator 111 , and the other ends thereof are connected to the plurality of switching elements S to 2 ^N-1 S. The plurality of capacitors C to 2 ^N-1 C are connected in parallel to each other. One ends of the switching elements S to 2 ^N-1 S are connected to the plurality of capacitors C to 2 ^N-1 C, and the other ends thereof are the first reference voltage VREF and the second reference voltage, for example, the ground. It is connected to the voltage (GND). The switching elements S to 2 ^N-1 S are controlled by the logic unit 114 to connect a corresponding capacitor to the second reference voltage GND or the first reference voltage VREF. The switching elements S to 2 ^N-1 S may include one or more MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and are turned on or off under the control of the logic unit 114 .

The plurality of capacitors C to 2 ^{N - 1} C are sequentially connected to the first reference voltage VREF or the second reference voltage GND according to the output of the comparator 111 . For example, among the plurality of capacitors (C~ ^2N- 1C), from the rightmost capacitor ( ^2N- 1C) of FIG. 2 to the leftmost capacitor (C) of FIG. 2 sequentially to the first reference voltage (VREF) Connected.

The logic unit 114 is connected to the comparator 111 and the digital-to-analog converter 113 . The logic unit 114 controls the digital-to-analog conversion unit 113 according to the output of the comparator 111 . That is, the logic unit 114 connects the plurality of capacitors C to 2 ^N-1 C to the first reference voltage VREF according to the output of the comparator 111 . The logic unit 114 may be configured with Successive Approximation Register (SAR) logic.

As described above, the initial voltage VRST and the signal voltage VSIG of the pixel (400 in FIG. 4 ) output from the pixel ( 400 in FIG. 4 ) are input to the comparator 111 , and the digital-to-analog converter 113 . stores the initial voltage VRST of the pixel ( 400 in FIG. 4 ) and the offset voltage VOFF of the comparator 111 through the feedback loop of the comparator 111 formed through the feedback unit 112 .

As described above, the analog-to-digital conversion apparatus 100 according to the present invention does not include a separate capacitor for storing the initial voltage VRST of the pixel (400 in FIG. 4 ) and the offset voltage VOFF of the comparator 111 . .

Accordingly, the size of the analog-to-digital conversion apparatus 100 according to the present invention is reduced by the area occupied by the separate capacitor, and the convergence time of the output voltage of the pixel (400 in FIG. 4 ) can be reduced. In addition, the time required for the separate capacitor to store the initial voltage of the pixel ( 400 in FIG. 4 ) and the offset voltage of the comparator 111 can be reduced.

In addition, in storing the initial voltage of the pixel (400 in FIG. 4 ) and the offset voltage of the comparator 111 in the digital-to-analog converter 113 , the driving capability of the buffer (not shown) supplying the first reference voltage is The error voltage generated because the output voltage of the digital-to-analog converter 113 does not sufficiently converge within a given time due to the limit and the resistance of the transmission line transmitting the first reference voltage is removed by the operation of the digital operation unit 120, Accordingly, the time required for the digital-to-analog converter 113 to store the initial voltage of the pixel ( 400 in FIG. 4 ) and the offset voltage of the comparator 111 may be reduced. Therefore, the analog-to-digital converter according to the present invention is easy to manufacture a small area, high-speed readout circuit for CIS in which a column parallel SAR ADC is embedded.

3 is a block diagram of a column parallel SAR analog-to-digital converter 300 . As shown in FIG. 3 , the column parallel SAR analog-to-digital converter 300 includes a plurality of SAR analog-to-digital converters 300a to 300n. The plurality of SAR analog-to-digital converters 300a to 300n correspond to the analog-to-digital converter (110 in FIGS. 1 and 2), respectively.

In this way, a buffer (not shown) is used to supply the first reference voltage VREF to the plurality of SAR analog-to-digital converters 300a to 300n. In this case, the buffer should be able to simultaneously supply the first reference voltage VREF to the plurality of SAR analog-to-digital converters 300a to 300n. However, it may take a long time to initialize the output of the digital-to-analog converter 113 to the first reference voltage VREF due to the limitation of the driving capability of the buffer and the resistance of the transmission line for transmitting the first reference voltage VREF. can

Since the analog-to-digital conversion apparatus 100 according to the present invention does not include a separate capacitor for storing the initial voltage of the pixel (400 in FIG. 4 ) and the offset voltage of the comparator 111 , the column-parallel SAR analog-to-digital conversion apparatus The time taken to initialize the output of the analog-to-digital converter 110 provided in each of the plurality of analog-to-digital converters 300a to 300n of 300 to the first reference voltage VREF is reduced.

FIG. 4 is a circuit diagram illustrating an example of a pixel 400 that supplies an image signal PIX_out to the analog-to-digital converter shown in FIG. 1 . Referring to FIG. 4 , the pixel 400 includes a light receiving diode 416 , four MOS transistors 411 to 414 , and a current source 415 .

The light-receiving diode 416 receives light incident from the outside, converts it into an electric signal, and outputs it.

The four MOS transistors 411 to 414 include a MOS transistor 411 turned on when the control signal PXi is activated, a MOS transistor 413 turned on when the control signal SXi is activated, and a control signal TXi. and a MOS transistor 414 that is turned on when is activated, and a MOS transistor 412 that is turned on when an output signal of the MOS transistor 411 is activated. The MOS transistors 411 and 412 input the power supply voltage VDDP and output the power supply voltage VDDP when turned on.

An image signal PIX_out that is an output signal of the pixel 400 is output from the emitter of the MOS transistor 412 .

The current source 415 keeps the output current of the MOS transistor 412 constant.

FIG. 5 is a waveform diagram of the signals shown in FIG. 2 . An operation of the signals shown in FIG. 5 will be described with reference to FIGS. 2 and 4 .

When the control signal Sxi is activated to a logic high level and the control signal RXi is activated to a logic high level, the image signal PIX_out output from the pixel 400 is the initial voltage ( VRST), and when the control signal TXi is activated to a logic high level, the image signal PIX_out is output as a signal voltage VSIG generated by light. The initial voltage VRST and the signal voltage SIG are sequentially output from the pixel 400 and input to the comparator 111 . The image signal PIX_out output from the pixel 400 is input as the input voltage VC_IN of the comparator 111 .

As the image signal PIX_out is input to the first input terminal of the comparator 111 , the output voltage of the digital-to-analog converter 113 , that is, the voltage input to the second input terminal of the comparator 111 , is as shown in FIG. 5 . It has various types of waveforms.

6 to 9 are circuit diagrams for explaining an analog-to-digital conversion operation performed by the analog-to-digital converter 110 shown in FIG. 2 .

6 shows the circuit configuration of the analog-to-digital converter 110 when the digital-to-analog converter 113 is initialized before the first analog-to-digital conversion. When the digital-to-analog converter 113 is initialized before the first analog-to-digital conversion, the image signal PIX_out applied to the first input terminal of the comparator 111 is input as the initial voltage VRST. ^{At this time, the other terminals of the capacitors C to 2 N-1} C provided in the digital-to-analog converter 113 are all connected to the first reference voltage VREF. In this state, the feedback control signal EN_DAC_RST is activated as a logic high, and the feedback unit 112 is also activated. Accordingly, the output signal of the comparator 111 is applied to the second input terminal of the comparator 111 together with the output voltage of the digital-to-analog converter 113 . Accordingly, the voltage VDAC applied to the second input terminal of the comparator 111 becomes (VRST-VOFF+ΔV+VERR). Here, VOOF represents the offset voltage of the input terminal of the comparator 111, ΔV represents each artificially applied specific voltage, and VERR represents the first in the process of simultaneously initializing the ^{plurality of capacitors (C~2N-1C).} 1 The voltage VDAC does not sufficiently converge within a given time due to the limitation of the driving capability of the buffer (not shown) supplying the reference voltage VREF and the resistance of the transmission line transmitting the first reference voltage VREF. Indicates the error voltage.

7 shows the circuit configuration of the analog-to-digital conversion unit 110 after the first analog-to-digital conversion. ^{The capacitors C to 2 N-1} C of the digital-to-analog converter 113 are sequentially connected to the first reference voltage VREF or the second reference voltage GND according to the comparison result of the comparator 111 . Accordingly, the output voltage VDAC of the digital-to-analog converter 113 converges to (VRST-VOFF) and can be expressed by Equation 1 below.

[Equation 1]

≒VRST-VOFFVDAC=VRST-VOFF+ΔV+VERR-

≒VRST-VOFF

Here, D _1st represents the i-th output of the comparator 111 during the first analog-to-digital conversion.

Summarizing Equation 1, the first analog-to-digital conversion result can be expressed as Equation 2 below.

[Equation 2]

≒ΔV+VERR

≒ΔV+VERR

8 shows a circuit configuration of the analog-to-digital converter 110 when the digital-to-analog converter 113 is initialized before the second analog-to-digital conversion. When the digital-to-analog converter 113 is initialized before the second analog-to-digital conversion, the image signal PIX_out applied to the first input terminal of the comparator 111 is input as a signal voltage VSIG. ^{At this time, the other terminals of the capacitors C to 2 N-1} C provided in the digital-to-analog converter 113 are all connected to the first reference voltage VREF. In this state, the feedback control signal EN_DAC_RST is deactivated as a logic low, unlike the feedback control signal EN_DAC_RST illustrated in FIG. 6 , and the feedback unit 112 is also deactivated. Accordingly, due to the charge redistribution phenomenon, the output voltage VDAC of the digital-to-analog converter 113 becomes the same voltage (VRST-VOFF+ΔV+VERR) as the output voltage shown in FIG. 6 .

9 shows the circuit configuration of the analog-to-digital conversion unit 110 after the second analog-to-digital conversion. ^{The capacitors C to 2 N-1} C of the digital-to-analog converter 113 may be connected to the first reference voltage VREF or the second reference voltage according to the comparison result of the comparator 111 as in the first analog-to-digital conversion operation. (GND) is connected sequentially. Accordingly, the output voltage VDAC of the digital-to-analog converter 113 converges to (VSIG-VOFF) and can be expressed by Equation 3 below.

[Equation 3]

≒VSIG-VOFFVDAC=VRST-VOFF+ΔV+VERR-

≒VSIG-VOFF

Here, D _2nd represents the i-th output of the comparator 111 during the second analog-to-digital conversion.

Summarizing Equation 3, the second analog-to-digital conversion result can be expressed as Equation 4 below.

[Equation 4]

≒VRST-VSIG+ΔV+VERR

≒VRST-VSIG+ΔV+VERR

The logic unit 114 receives the output of the comparator 111 from the output (D _2nd ) of the comparator 111 generated as the second analog-to-digital conversion result to the output of the comparator 111 generated as the first analog-to-digital conversion result ( D _1st ) is subtracted. As a result, the output signal DCDS of the logic unit 114 may be expressed as in Equation 5 below using Equations 2 and 4.

[Equation 5]

=

-

≒VRST-VSIG

=

-

≒VRST-VSIG

Here, DCDS[i] represents the i-th output signal of the logic unit 114 . Accordingly, the final output signal DCDS of the logic unit 114 represents the difference between the initial voltage VRST of the output of the pixel 400 and the signal voltage VSIG.

In this way, the signal output from the analog-to-digital converter is a voltage artificially applied in the digital operation process of the logic unit 114 (??V), an offset voltage (VOFF) of the comparator 111, and a digital-to-analog converter ( In the initialization process of 113), the error voltage VERR generated because the output voltage of the digital-to-analog converter 113 is not sufficiently converged has a value from which it has been removed.

As described above, the analog-to-digital conversion apparatus 100 according to the present invention does not include a separate capacitor to store the output voltage of the pixel 400 and the offset voltage of the comparator 111 . Accordingly, the area occupied by the separate capacitor and the convergence time of the output voltage of the pixel 400 may be reduced. Also, the initial voltage of the image signal PIX_out output from the pixel 400 and the offset voltage of the comparator 111 are stored in the digital-to-analog converter 113 . Due to this, the digital-to-analog converter 113 within a given time due to the limitation of the driving capability of the buffer (not shown) for supplying the first reference voltage VREF and the resistance of the transmission line for transmitting the first reference voltage VREF. An error voltage generated because the output voltages of 'D' are not sufficiently converged is removed by the operation of the logic unit 114 , and accordingly, the digital-to-analog converter 113 is the initial voltage of the image signal PIX_out output from the pixel 400 . and the time required to store the offset voltage of the comparator 111 may be reduced. Therefore, the analog-to-digital converter 100 according to the present invention is easy to manufacture a small area high-speed readout circuit for CIS in which a column parallel SAR analog-to-digital converter is embedded.

Although the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims (11)

an analog-to-digital converter for converting an image signal into a digital signal; and
A digital operation unit for calculating a difference between an initial voltage and a signal voltage corresponding to the digital signal;
The analog-to-digital conversion unit,
a digital-to-analog converter including a plurality of capacitors selectively connected to the first reference voltage and the second reference voltage to output an output voltage;
a comparator for comparing the image signal and the output voltage; and
A feedback unit that is activated when the initial voltage is applied as the image signal, and transmits a voltage obtained by subtracting the offset voltage of the comparator from the initial voltage to the plurality of capacitors of the digital-to-analog converter; and
The plurality of capacitors of the digital-to-analog converter are sequentially connected to the first reference voltage or the second reference voltage according to the comparison result of the comparator, and when the initial voltage is applied as the image signal, it is transmitted through the feedback unit. An analog-to-digital converter for storing the initial voltage and the offset voltage. According to claim 1, wherein the analog-to-digital conversion unit,
Further comprising a logic unit connected to the output terminal of the comparator and the digital-to-analog converter, and configured to cause the digital-to-analog converter to select one of the first reference voltage and the second reference voltage according to the comparison result of the comparator An analog-to-digital conversion device characterized by According to claim 1,
The second reference voltage is an analog-to-digital conversion device, characterized in that the ground voltage. According to claim 1,
The image signal is an analog-to-digital conversion device, characterized in that the initial voltage of a pixel that converts light into an electrical signal, and a signal voltage that is converted by the light input from the outside by the pixel. According to claim 2, wherein the digital-to-analog converter,
and switching elements selectively connecting the plurality of capacitors to one of the first reference voltage and the second reference voltage according to the control of the logic unit. 6. The method of claim 5,
The image signal includes the initial voltage and the signal voltage, and the signal voltage is obtained by converting light input from the outside through a pixel,
and the voltage obtained by subtracting the offset voltage of the comparator from the initial voltage of the pixel when the initial voltage is applied as the image signal is stored in the plurality of capacitors. 7. The method of claim 6,
When the image signal is applied, the comparator sequentially compares the initial voltage and the signal voltage included in the image signal with the output voltage applied from the digital-to-analog converter, and outputs the comparison result. Device. The method according to claim 1, wherein at the time of initialization of the digital-to-analog conversion unit before the first analog-to-digital conversion,
the initial voltage is applied as the image signal,
The capacitors provided in the digital-to-analog converter are connected to the first reference voltage,
and the feedback unit is activated to transmit the voltage obtained by subtracting the offset voltage of the comparator from the initial voltage. 9. The method of claim 8, wherein after the first analog-to-digital conversion,
The plurality of capacitors provided in the digital-to-analog converter are sequentially connected to the first reference voltage or the second reference voltage according to a comparison result of the comparator. The method according to claim 1, wherein at the time of initialization of the digital-to-analog converter before the second analog-to-digital conversion,
the signal voltage is applied as the image signal;
The plurality of capacitors provided in the digital-to-analog converter are connected to the first reference voltage,
The analog-to-digital conversion device, characterized in that the feedback unit is deactivated. 11. The method of claim 10, wherein after the second analog-to-digital conversion,
The plurality of capacitors provided in the digital-to-analog converter are sequentially connected to a first reference voltage or a second reference voltage according to a comparison result of the comparator.

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