KR102242636B1 - Pulse-Width Modulation based sensor interface circuits - Google Patents

Abstract

The present invention discloses a pulse width modulation based sensor interface circuit. The sensor interface circuit of the present invention is connected to an oscillator unit that generates a square wave, and an RC circuit unit including a reference RC circuit and a sensing RC circuit in a differential structure that converts capacitance information into a voltage over time using the generated square wave, RC It is connected to the output terminal of the circuit part, and is connected to the output terminal of the high-pass filter part and the high-pass filter part that outputs the reference voltage and the detection voltage by filtering low-band noise among frequencies of the voltage converted by the reference RC circuit and the detection RC circuit, respectively, It detects whether or not the detection voltage reaches a preset threshold voltage, and is connected to the output terminal of the comparison circuit unit and the comparison circuit unit respectively outputting a duty cycle for the detected result, and the difference between the output duty cycles is calculated. It includes an output XOR gate.

Description

Pulse-Width Modulation based sensor interface circuits}

The present invention relates to an interface circuit, and more particularly, to a pulse width modulation-based sensor interface circuit that outputs a difference between a reference capacitance and a sense capacitance as a half-digital signal in a pulse width modulation format.

Conventional capacitive sensor interface circuits can be largely divided into analog interface circuits and semi-digital interface circuits.

In particular, the semi-digital interface circuit is simpler than the analog interface circuit in terms of power consumption and circuit complexity. The semi-digital interface circuit uses Period Modulation (PM) or Pulse Width Modulation (PWM) to provide each sensor's capacitance information with period (C to P) and pulse duty cycle (C). to D) half-digital signal.

Semi-digital interface circuits generally use a relaxation oscillator or a ring oscillator to supply a square wave signal, and single point calibration to reduce the effects of parasitic capacitance, power supply voltage, and threshold voltage. ) Method.

The design of the C to P interface circuit is simple, but a counter-based circuit, a frequency-to-voltage conversion circuit, or a PLL (Phase Locked Loop)-based circuit is required for frequency demodulation of the signal. In addition, the output frequency of the C to P circuit greatly affects the values of transconductance, parasitic capacitance and resistance of MOS (Metal Oxide Semiconductor) transistors, and is also affected by process and temperature changes.

The C to D interface circuit encodes the sensor capacitance change in the time domain to modulate the sensor's information into a duty cycle or pulse width. In addition, there is a method of directly connecting the sensor to a micro-controller. This structure does not require a signal conditioning circuit, but triggers the measurement of high input capacitance, output resistance and discharge time existing at the port pins of the microcontroller. There is a problem of reducing the resolution.

Korean Patent Application Publication No. 10-2016-0035556 (2016.03.31.)

An object of the present invention is to provide a pulse width modulation-based sensor interface circuit capable of low power consumption and filtering noise for a parasitic capacitor and a full band.

Another object of the present invention is to provide a pulse width modulation-based sensor interface circuit that minimizes the influence of processes, temperature, power supply voltage, and the like.

In order to achieve the above object, the pulse width modulation-based sensor interface circuit according to the present invention is connected to an oscillator unit that generates a square wave, and a reference RC circuit that converts capacitance information into a voltage over time using the generated square wave, and An RC circuit unit including a sensing RC circuit in a differential structure, connected to the output terminal of the RC circuit unit, and outputting a reference voltage and a sensing voltage by filtering low-band noise among frequencies of the voltage converted by the reference RC circuit and the sensing RC circuit, respectively. The high-pass filter unit is connected to the output terminal of the high-pass filter unit and detects whether the reference voltage and the sensing voltage reach a preset threshold voltage, respectively, and outputs a duty cycle for the detected result, respectively. And an XOR gate connected to the comparison circuit unit and the output terminal of the comparison circuit unit, each outputting a difference in the output duty cycle.

In addition, the RC circuit unit is characterized in that it operates as a low-pass filter to remove high-frequency noise.

In addition, the high-pass filter unit is characterized in that, by removing low-frequency noise from a frequency from which high-frequency noise is removed from the RC circuit unit, and outputting a frequency in a state in which noise for all bands is removed.

In addition, the reference RC circuit includes a reference capacitor serving as a reference and a first reference resistance serving as a reference, and the sensing RC circuit has a different capacity than the reference capacitor, and the sensing capacitor for sensing environmental information and the first It is characterized in that it includes a second reference resistance having the same resistance value as the resistance.

In addition, the reference RC circuit and the detection RC circuit may have different charging times to reach the threshold voltage due to a difference between the reference capacitor and the detection capacitor.

In addition, the comparison circuit unit may include a bias circuit for generating the threshold voltage, a first comparison circuit for comparing the threshold voltage and the reference voltage generated from the bias circuit, and outputting the compared result as a first duty cycle, and the bias circuit. And a second comparison circuit for comparing the threshold voltage generated from and the sensed voltage, and outputting the compared result as a second duty cycle.

In addition, the first comparison circuit and the second comparison circuit are designed based on an inverter capable of self-regulation to reduce a variation of the threshold voltage.

The pulse width modulation-based sensor interface circuit according to the present invention includes an oscillator unit for generating a square wave, a square wave connected to the oscillator unit, and a voltage with time A reference RC circuit that converts to, a first high pass filter that is connected to the reference RC circuit to receive the converted voltage, and outputs a reference voltage obtained by filtering low-band noise among the frequencies of the received voltage, and connects to the first high pass filter A first comparison circuit for receiving a reference voltage, comparing the received reference voltage and a preset threshold voltage, and outputting a first duty cycle for the compared result, and a square wave connected to the reference RC circuit in a differential structure A sensing RC circuit that receives and uses the received square wave to convert capacitance information of a sensing capacitor that has a different capacity from the reference capacitor and detects environmental information into a voltage over time, and is connected to the sensing RC circuit to convert A second high-pass filter for receiving the received voltage and outputting a detection voltage obtained by filtering low-band noise among the frequencies of the received voltage, and connected to the second high-pass filter to receive a detection voltage, and the received detection voltage and the threshold A second comparison circuit for comparing voltages and outputting a second duty cycle for the compared result, and a difference between the first duty cycle and the second duty cycle by being connected to the first comparison circuit and the second comparison circuit Includes an XOR gate that outputs

The pulse width modulation-based sensor interface circuit according to the present invention can consume power through an RC circuit having a differential structure including a high-pass filter, and can filter out parasitic capacitors and noise for the entire band.

In addition, the influence of process, temperature, power voltage, etc. can be minimized through a self-regulating inverter-based comparison circuit.

In addition, the sensitivity, dynamic range and nominal point of the sensor can be adjusted by adjusting the resistance value of the RC circuit, the threshold voltage of the comparison circuit, and the size of the reference capacitor.

Through this, it is possible to actively apply to various application fields, not limited application fields.

1 is a block diagram illustrating a sensor interface circuit according to an embodiment of the present invention.
2 is a circuit diagram illustrating a reference RC circuit and a first high-pass filter circuit according to an embodiment of the present invention.
3 is a circuit diagram illustrating a sensing RC circuit and a second high-pass filter circuit according to an embodiment of the present invention.
FIG. 4 is a diagram for explaining the equivalent rotation model of FIGS. 2 and 3.
5 is a circuit diagram illustrating a comparison circuit unit according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to elements of each drawing, it should be noted that the same elements are to have the same numerals as possible even if they are indicated on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function is apparent to those skilled in the art or may obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a block diagram illustrating a sensor interface circuit according to an embodiment of the present invention.

Referring to FIG. 1, the sensor interface circuit 100 outputs a difference between a reference capacitance and a sense capacitance as a half-digital signal in a PWM format. The sensor interface circuit 100 can consume low power and filters out parasitic capacitors and noise for the entire band. The sensor interface circuit 100 minimizes the influence of the process, temperature, power supply voltage, and the like. The sensor interface circuit 100 can adjust the sensitivity, dynamic range, and nominal point of the sensor by adjusting the resistance value of the RC circuit, the threshold voltage of the comparison circuit, and the size of the reference capacitor. The sensor interface circuit 100 includes an RC circuit unit including a reference RC circuit 20 and a sensing RC circuit 30, a high pass filter including a first high pass filter circuit 40 and a second high pass filter circuit. It includes a comparison circuit unit including the second, first comparison circuit 70 and the second comparison circuit 80 and the XOR gate 90, and further includes an oscillator unit 10.

The oscillator unit 10 generates a square wave. The oscillation unit 10 operates the RC circuit unit by supplying the generated square wave clock CLK to the reference RC circuit 20 and the sensing RC circuit 30, respectively. Preferably, the oscillator 10 may be a ring oscillator.

The RC circuit unit is connected to the oscillation unit 10 and includes a reference RC circuit 20 and a sensing RC circuit 30 in a differential structure. The reference RC circuit 20 receives a square wave from the oscillator unit 10 and converts _{the capacitance information of the reference capacitor (C ref} ) 21 as a reference into a voltage over time using the received square wave. The sensing RC circuit 30 receives a square wave from the oscillator unit 10 and has a different capacity from the reference capacitor 21 using the received square wave, and the sensing capacitor (C _sen ) 31 detects environmental information. Converts capacitance information into voltage over time. Here, the RC circuit unit has the same resistance values of the reference RC circuit 20 and the detection RC circuit 30. Through this, the time to reach the critical power to be sensed varies according to the capacitance of the reference capacitor 21 or the sensing capacitor 31 of the RC circuit unit. In addition, the RC circuit unit not only serves to convert capacitance information into a voltage over time, but also acts as a low pass filter to filter high-frequency noise.

The high-pass filter unit is connected to the output terminal of the RC circuit unit and filters low-band noise among the frequencies of the voltages converted by the reference RC circuit 20 and the sensing RC circuit 30. The high pass filter unit includes a first high pass filter circuit 40 and a second high pass filter circuit 50. The first high-pass filter circuit 40 is connected to the output terminal of the reference RC circuit 20 and outputs a reference voltage V _ref by filtering low-band noise among the frequencies of the voltage output from the reference RC circuit 20. The second high-pass filter circuit 50 is connected to the output terminal of the sensing RC circuit 30 and outputs a sensing voltage V _{sen obtained} by filtering low-band noise among the frequencies of the voltage output from the sensing RC circuit 30.

The comparison circuit unit is connected to the output terminal of the high-pass filter unit, detects whether the reference voltage and the detection voltage reach a preset threshold voltage, and outputs a duty cycle for the detected result, respectively. The comparison circuit unit includes a first comparison circuit 70 and a second comparison circuit 80. The first comparison circuit 70 is connected to the output terminal of the first high-pass filter circuit 40 to compare a reference voltage and a threshold voltage. Through this, the first comparison circuit 70 detects whether the reference voltage reaches the threshold voltage, and outputs the _{detected result as a first duty cycle D ref.} The second comparison circuit 80 is connected to the output terminal of the second high-pass filter circuit 50 to compare the sensed voltage and the threshold voltage. Through this, the second comparison circuit 80 detects whether the sensed voltage reaches the threshold voltage, and outputs the _{sensed result as a second duty cycle D sen.}

The XOR gate 90 is connected to the output terminal of the comparison circuit unit and detects a difference between the first duty cycle and the second duty cycle output from the first comparison circuit 70 and the second comparison circuit 80. The XOR gate 90 outputs the detected result. At this time, the XOR gate 90 may output the sensed result as a half-digital signal in a PWM format.

FIG. 2 is a circuit diagram illustrating a reference RC circuit and a first high-pass filter circuit according to an embodiment of the present invention, and FIG. 3 is a circuit diagram illustrating a sensing RC circuit and a second high-pass filter circuit according to an embodiment of the present invention. And FIG. 4 is a view for explaining the equivalent rotation model of FIGS. 2 and 3. 4(a) is a diagram showing a circuit diagram of the equivalent circuit model of FIGS. 2 and 3, and FIG. 4(b) is a diagram showing a voltage waveform for the equivalent circuit model of FIG. 4(a) over time to be.

1 to 4, the RC circuit unit includes a reference resistor R and a capacitor C, and further includes a MOS transistor. Here, the RC circuit unit can be divided into an RC circuit and a reset circuit. The high-pass filter circuit includes a filter capacitor C _f and a MOS transistor.

The reference RC circuit 20 includes a reference capacitor 21 and a first reference resistor 22, and includes a first P-channel MOS (PMOS) transistor 23 and a first N-channel MOS (NMOS) transistor 24. ). Here, the reference RC circuit 20 may be divided into an RC circuit including the reference capacitor 21 and the first reference resistor 22 and a reset circuit including the first NMOS transistor 24. The first high-pass filter circuit 40 includes a first filter capacitor 41 and a third NMOS transistor 42.

Specifically, in the first PMOS transistor 23, a source terminal is connected to a power terminal VDD, and a clock is applied to a gate terminal. One end of the first reference resistor 22 is connected to a drain terminal of the first PMOS transistor 23. In the reference capacitor 21, a (+) pole is connected to the other end of the first reference resistor 22, and a (-) pole is connected to the ground (GND). In the first NMOS transistor 24, a drain terminal is connected to the other end of the first reference resistor 22, a clock is applied to a gate terminal, and a source terminal is connected to ground. The first filter capacitor 41 has a (+) pole connected to the other end of the first reference resistor 22. In the third NMOS transistor 42, the drain terminal is connected to the negative pole of the first filter capacitor 41, the clock is applied to the gate terminal, and the source terminal is connected to the ground. At this time, the reference capacitor 21, the first NMOS transistor 24, and the third NMOS transistor 42 are connected in a parallel structure.

On the other hand, the reference RC circuit 20 and the first high-pass filter circuit 40, when the clock supplied from the oscillator unit 10 is 1, the first PMOS transistor 23 is turned on (ON) and the reference capacitor 21 ) Is charged, and at the same time, the first NMOS transistor 24 and the third NMOS transistor 42 are turned off. Through this, the reference RC circuit 20 and the first high-pass filter circuit 40 may output a reference voltage from which low-band noise is filtered.

The sensing RC circuit 30 includes a sensing capacitor 31 and a second reference resistor 32, and further includes a second PMOS transistor 33 and a second NMOS transistor 34. Here, the sensing RC circuit 30 may be divided into an RC circuit including the sensing capacitor 31 and the second reference resistor 32 and a reset circuit including the second NMOS transistor 34. The second high-pass filter circuit 50 includes a second filter capacitor 51 and a fourth NMOS transistor 52.

Specifically, the source terminal of the second PMOS transistor 33 is connected to the power supply terminal, and a clock is applied to the gate terminal. One end of the second reference resistor 32 is connected to the drain terminal of the second PMOS transistor 33. Here, the second reference resistance 32 has the same resistance value as the first reference resistance. In the sensing capacitor 31, the (+) pole is connected to the other end of the second reference resistor 32, and the (-) pole is connected to the ground. Here, the Kimji capacitor 31 has a different capacity than the reference capacitor 21 and detects environmental information. In the second NMOS transistor 34, a drain terminal is connected to the other end of the second reference resistor 32, a clock is applied to a gate terminal, and a source terminal is connected to ground. The second filter capacitor 51 has a (+) electrode connected to the other end of the second reference resistor 22. Here, the second filter capacitor 51 may be the same as the first filter capacitor 41. In the fourth NMOS transistor 52, the drain terminal is connected to the negative pole of the second filter capacitor 51, the clock is applied to the gate terminal, and the source terminal is connected to the ground. At this time, the sensing capacitor 31, the second NMOS transistor 34, and the fourth NMOS transistor 52 are connected in a parallel structure.

Meanwhile, the sensing RC circuit 30 and the second high-pass filter circuit 50 charge the sensing capacitor 31 by turning on the second PMOS transistor 33 when the clock supplied from the oscillator unit 10 is 1 At the same time, the second NMOS transistor 34 and the fourth NMOS transistor 52 are turned off.

At this time, since the reference RC circuit 20 and the detection RC circuit 30 have a differential structure using the difference between the reference capacitor 21 and the detection capacitor 31, the charging time to reach the threshold voltage is different from each other, and the parasitic capacitance The impact can be minimized.

In addition, the reference RC circuit 20 and the detection RC circuit 30 are generated from the first reference resistance 22 and the second reference resistance 32 through the first PMOS transistor 23 and the second PMOS transistor 33. Reduce the input reference noise. The reference RC circuit 20 and the detection RC circuit 30 operate as a low-pass filter to filter high-frequency noise. The first high pass filter circuit 40 and the second high pass filter circuit 50 include a first filter capacitor 41 and a third NMOS transistor 42 and a second filter capacitor 51 and a fourth NMOS transistor 52. Through this, it operates as a high-pass filter to filter low-frequency noise. At this time, the cutoff frequency of the low pass filter is affected by the off resistance of the first PMOS transistor 23 and the second PMOS transistor 33, and the cutoff frequency of the high pass filter is determined by the first high pass filter circuit 41 , The second high-pass filter circuit 51, the third NMOS transistor 42, and the fourth NMOS transistor 52 is affected by the off resistance. Accordingly, since the sensor interface circuit 100 operates like a band pass filter, it is possible to minimize the effect of noise on the entire band.

5 is a circuit diagram illustrating a comparison circuit unit according to an embodiment of the present invention.

Referring to FIGS. 1 and 5, the comparison circuit unit is designed based on an inverter capable of self-regulation so as to reduce variations in threshold voltage. The comparison circuit unit includes a first comparison circuit 70 and a second comparison circuit 80, and further includes a bias circuit 60.

The bias circuit 60 generates a threshold voltage. The bias circuit 60 includes a third PMOS transistor 61, a fourth PMOS transistor 62, a fifth PMOS transistor 63, a sixth PMOS transistor 64, a seventh PMOS transistor 65, and a fifth NMOS transistor. 66, a sixth NMOS transistor 67, a first bias resistor 68, and a second bias resistor 69.

Specifically, the source terminal of the third PMOS transistor 61 is connected to the power supply terminal, and an alpha signal is applied to the gate terminal. In the fourth PMOS transistor 62, a source terminal is connected to a power terminal, and an alpha signal is applied to a gate terminal. The fifth PMOS transistor 63 has a source terminal connected to a drain terminal of the fourth PMOS transistor 62, a gate terminal connected to a drain terminal of the third PMOS transistor 61, and a drain terminal connected to the drain terminal of the third PMOS transistor 61. It is connected to the drain end of.

The sixth PMOS transistor 64 has a source terminal connected to the drain terminal of the third PMOS transistor 61 and outputs a _{threshold voltage V bias to the gate terminal.} The seventh PMOS transistor 65 has a source terminal connected to the drain terminal of the sixth transistor 64 and outputs a threshold voltage to the drain terminal. The first bias resistor 68 has one end connected to the source terminal of the sixth PMOS transistor 64 and the other end connected to the gate terminal of the seventh PMOS transistor 65. The fifth NMOS transistor 66 outputs an intrinsic voltage to the drain terminal, and the gate terminal is connected to the gate terminal of the seventh PMOS transistor 65. In the sixth NMOS transistor 67, a drain terminal is connected to a source terminal of the fifth NMOS transistor 66, a threshold voltage is output to a gate terminal, and a source terminal is connected to ground. The second bias resistor 69 has one end connected to the other end of the first bias resistor 68 and the other end connected to the ground. Accordingly, the gate terminal of the seventh PMOS transistor 66, the gate terminal of the fifth NMOS transistor 66, the other terminal of the first bias resistor 68, and one end of the second bias resistance 69 are connected to each other.

The first comparison circuit 70 compares the threshold voltage and the reference voltage generated from the bias circuit 60, and outputs the compared result as a first duty cycle. The first comparison circuit 70 includes an eighth PMOS transistor 71, a ninth PMOS transistor 72, a seventh NMOS transistor 73, an eighth NMOS transistor 74, and a first AND gate 75. .

Specifically, the source terminal of the eighth PMOS transistor 71 is connected to the source terminal of the sixth PMOS transistor 64, and a threshold voltage is applied to the gate terminal. The source terminal of the ninth PMOS transistor 72 is connected to the drain terminal of the eighth PMOS transistor 71 and a reference voltage is applied to the gate terminal. The seventh NMOS transistor 73 has a drain terminal connected to the drain terminal of the ninth PMOS transistor 72, and a reference voltage is applied to the gate terminal. In the eighth NMOS transistor 74, a drain terminal is connected to a source terminal of the seventh NMOS transistor 73, a threshold voltage is applied to a gate terminal, and a source terminal is connected to ground. In the first AND gate 75, a drain terminal of the ninth PMOS transistor 72 and a source terminal of the seventh NMOS transistor 73 are connected to one of the input terminals, a clock is applied to the other, and a first duty is applied to the output terminal. The cycle is output.

The second comparison circuit 80 compares the threshold voltage and the reference voltage generated from the bias circuit 60, and outputs the compared result as a second duty cycle. The second comparison circuit 80 includes a tenth PMOS transistor 81, an eleventh PMOS transistor 82, a ninth NMOS transistor 83, a tenth NMOS transistor 84, and a second AND gate 85. .

Specifically, the source terminal of the tenth PMOS transistor 81 is connected to the source terminal of the sixth PMOS transistor 64, and a threshold voltage is applied to the gate terminal. In the eleventh PMOS transistor 82, the source terminal is connected to the drain terminal of the tenth PMOS transistor 81, and a sensing voltage is applied to the gate terminal. The drain terminal of the ninth NMOS transistor 83 is connected to the drain terminal of the eleventh PMOS transistor 82 and a sensing voltage is applied to the gate terminal. In the tenth NMOS transistor 84, the drain terminal is connected to the source terminal of the ninth NMOS transistor 83, the threshold voltage is applied to the gate terminal, and the source terminal is connected to the ground. In the second AND gate 85, a drain terminal of the 11th PMOS transistor 82 and a source terminal of the ninth NMOS transistor 83 are connected to one of the input terminals, a clock is applied to the other, and a second duty is applied to the output terminal. The cycle is output.

Here, the sixth PMOS transistor 64, the eighth PMOS transistor 71, and the tenth PMOS transistor 81 are connected in a parallel structure. Accordingly, the sixth NMOS transistor 67, the eighth NMOS transistor 74, and the tenth NMOS transistor 84 are also connected in a parallel structure.

On the other hand, the bias circuit 60 determines whether to turn on/off the third PMOS transistor 61 and the fourth PMOS transistor 62 through the alpha signal, thereby setting a bias that is a threshold voltage for 0.9 × VDD or 0.5 × VDD. It serves to generate and supply to the first comparison circuit 70 and the second comparison circuit (80). At this time, the fourth PMOS transistor 62 and the fifth PMOS transistor 63 diode-connected to drop a constant voltage supplied from the voltage terminal, and the two bias resistors 68 and 69 form a resistance divider to reduce the threshold voltage. Set.

The sixth PMOS transistor 64, the sixth NMOS transistor 67, the eighth PMOS transistor 71, the eighth NMOS transistor 74, the tenth PMOS transistor 81, and the tenth NMOS transistor 84 are deep tri It operates in the deep triode region and is regulated by the threshold voltage. The low voltage threshold voltage decreases the resistance of the sixth PMOS transistor 64, the eighth PMOS transistor 71, and the tenth PMOS transistor 81, and the sixth NMOS transistor 67 and the eighth NMOS transistor 74 And increasing the resistance of the tenth NMOS transistor 84 and simultaneously moving the switching threshold of the inverter including the seventh PMOS transistor 65 and the fifth NMOS transistor 66 to a high voltage. The operation for the high voltage threshold voltage is operated in reverse to the operation described above. When the inverter outputs of the first and second comparison circuits 70 and 80 reach a threshold voltage, their outputs are stabilized. In this case, the first comparison circuit 70 and the second comparison circuit 80 use the same threshold voltage to minimize deviations caused by idle, temperature, and the like.

If the reference voltage or the sensing voltage is less than the threshold voltage, the ninth PMOS transistor 72 and the seventh NMOS transistor 73 of the first comparison circuit 70 or the eleventh PMOS transistor 82 of the second comparison circuit 80 ) And the ninth NMOS transistor 83 outputs a '1' state, and when the reference voltage or the sense voltage is greater than the threshold voltage, the output is reversed as described above. In particular, when the clock of the oscillator unit 10 becomes '1', the outputs of the first AND gate 75 and the second AND gate 85 output a first duty cycle and a second duty cycle, and the clock is '0'. When', the outputs of the first AND gate 75 and the second AND gate 85 become '0'.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific preferred embodiments described above, and without departing from the gist of the present invention claimed in the claims, in the technical field to which the present invention pertains. Anyone of ordinary skill in the art can implement various modifications, as well as such modifications will be within the scope of the claims.

10: oscillator part 20: reference RC circuit
21: reference capacitor 22: first reference resistance
23: first PMOS transistor 24: first NMOS transistor
30: sensing RC circuit 31: sensing capacitor
32: second reference resistance 33: second PMOS transistor
34: second NMOS transistor 40: first high-pass filter circuit
41: first filter capacitor 42: third NMOS transistor
50: second high-pass filter circuit 51: second filter capacitor
52: fourth NMOS transistor 60: bias circuit
61: third PMOS transistor 62: fourth PMOS transistor
63: fifth PMOS transistor 64: sixth PMOS transistor
65: seventh PMOS transistor 66: fifth NMOS transistor
67: sixth NMOS transistor 68: first bias resistor
69: second bias resistance 70: first comparison circuit
71: eighth PMOS transistor 72: ninth PMOS transistor
73: seventh NMOS transistor 74: eighth NMOS transistor
75: first AND gate 80: second comparison circuit
81: tenth PMOS transistor 82: eleventh PMOS transistor
83: ninth NMOS transistor 84: tenth NMOS transistor
85: second AND gate 90: XOR gate
100: sensor interface circuit

Claims (8)

An RC circuit unit connected to an oscillator unit generating a square wave and including a reference RC circuit and a sensing RC circuit in a differential structure for converting a capacitance value into a voltage that changes with time using the generated square wave;
A high-pass filter unit connected to the output terminal of the RC circuit unit and outputting a reference voltage and a sensing voltage by filtering low-band noise among frequencies of the voltages converted by the reference RC circuit and the sensing RC circuit;
A comparison circuit unit connected to an output terminal of the high-pass filter unit, each sensing whether the reference voltage and the sensing voltage reach a preset threshold voltage, and outputting a duty cycle for the detected result, respectively; And
An XOR gate connected to an output terminal of the comparison circuit unit and outputting a difference in the output duty cycle;
Pulse width modulation-based sensor interface circuit comprising a. The method of claim 1,
The RC circuit unit,
A sensor interface circuit based on pulse width modulation, characterized in that it operates as a low-pass filter to remove high-frequency noise. The method of claim 2,
The high pass filter unit,
A pulse width modulation-based sensor interface circuit, characterized in that, by removing low-frequency noise from a frequency from which high-frequency noise has been removed from the RC circuit unit, the frequency is output in a state in which noise for the entire band is removed. The method of claim 1,
The reference RC circuit,
A reference capacitor as a reference; And
Including; a first reference resistance serving as a reference,
The sensing RC circuit,
A sensing capacitor having a capacity different from that of the reference capacitor and detecting environmental information to which a sensor is applied; And
A second reference resistance having the same resistance value as the first reference resistance;
Pulse width modulation-based sensor interface circuit comprising a. The method of claim 4,
The reference RC circuit and the detection RC circuit,
A pulse width modulation-based sensor interface circuit, characterized in that charging times to reach the threshold voltage are different due to a difference in capacities of the reference capacitor and the sensing capacitor. The method of claim 1,
The comparison circuit unit,
A bias circuit for generating the threshold voltage;
A first comparison circuit for comparing the threshold voltage and the reference voltage generated from the bias circuit, and outputting the compared result as a first duty cycle; And
A second comparison circuit for comparing the threshold voltage and the sensing voltage generated from the bias circuit, and outputting the compared result as a second duty cycle;
Pulse width modulation-based sensor interface circuit comprising a. The method of claim 1,
The comparison circuit unit,
A pulse width modulation-based sensor interface circuit, comprising an inverter to reduce variations in the threshold voltage. An oscillator unit generating a square wave;
A reference RC circuit connected to the oscillator unit to receive a square wave, and convert a capacitance value of a reference capacitor, which is a reference, into a voltage that changes over time using the received square wave;
A first high-pass filter connected to the reference RC circuit to receive the converted voltage, and output a reference voltage obtained by filtering low-band noise among the frequencies of the received voltage;
A first comparison circuit connected to the first high-pass filter to receive a reference voltage, compare the received reference voltage and a preset threshold voltage, and output a first duty cycle for the compared result;
It is connected to the reference RC circuit in a differential structure to receive a square wave, and by using the received square wave, the capacitance value of the sensing capacitor for sensing environmental information to which the sensor is applied has a different capacity from the reference capacitor A sensing RC circuit that converts into voltage;
A second high-pass filter connected to the sensing RC circuit to receive the converted voltage and output a sensing voltage obtained by filtering out low-band noise among the frequencies of the received voltage;
A second comparison circuit connected to the second high-pass filter to receive a detection voltage, compare the received detection voltage and the threshold voltage, and output a second duty cycle for the compared result; And
An XOR gate connected to the first comparison circuit and the second comparison circuit to output a difference between the first duty cycle and the second duty cycle;
Pulse width modulation-based sensor interface circuit comprising a.

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