KR102242351B1 - Display device - Google Patents

Abstract

An embodiment of the present invention relates to a display device capable of reducing the number of input/output pins of a timing controller. A display device according to an embodiment of the present invention includes a timing controller that receives driving timing information through an SCL signal and an SDA signal. The timing controller receives the SCL signal through a first pin and the SDA signal through a second pin, generates first and second timing control signals based on the SCL signal and the SDA signal, and the The first timing control signal is output through a first pin, and the second timing control signal is output through the second pin.

Description

Display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device.

As the information society develops, demands for display devices for displaying images are increasing in various forms, and in recent years, liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting diodes have been developed. Various display devices such as a diode display (OLED: Organic Light Emitting Diode) are being used.

The display device includes a display panel, a gate driver, a data driver, and a timing controller. The display panel includes data lines, gate lines, and a plurality of pixels formed at intersections between the data lines and the gate lines to receive data voltages of the data lines when gate signals are supplied to the gate lines. The pixels emit light with a predetermined brightness according to the data voltages. The gate driver supplies gate signals to the gate lines. The data driver includes source drive integrated circuits (hereinafter referred to as “IC”) that supply data voltages to the data lines. The timing controller controls the operation timing of the gate driver and the data driver.

When the power of the display device on, the timing controller receives the information stored in the EEPROM by a SCL (serial clock) signal and an SDA (serial data) via a signal EEPROM (electrically erasable programmable read-only memory) and I ² C communication . The timing controller outputs control signals for controlling the gate driver and the data driver based on information input from the EEPROM.

Recently, as high-resolution displays such as Ultra High Definition (UHD, 3840×2160) have been released, the number of control signals of the timing controller is also increasing. In this case, since the number of input/output pins of the timing controller increases, there is a problem that the cost of the timing controller increases due to an increase in the size of the timing controller.

An embodiment of the present invention provides a display device capable of reducing the number of input/output pins of a timing controller.

A display device according to an embodiment of the present invention includes a timing controller that receives driving timing information through an SCL signal and an SDA signal. The timing controller receives the SCL signal through a first pin and the SDA signal through a second pin, generates first and second timing control signals based on the SCL signal and the SDA signal, and the The first timing control signal is output through a first pin, and the second timing control signal is output through the second pin.

A display device according to another exemplary embodiment of the present invention includes a display panel, a gate driver, a data driver, a memory, and a timing controller. The display panel includes gate lines, data lines, and pixels provided in an intersection area between the gate lines and data lines. The gate driver supplies gate signals to the gate lines. The data driver supplies data voltages to the data lines. The memory stores timing information of a gate control signal for driving the gate driver and a data control signal for driving the data driver. The timing controller receives the timing information from the memory through an SCL signal through a first pin and an SDA signal through a second pin, and controls the gate control signal and the data based on the SCL signal and the SDA signal. A signal is generated, a first timing control signal of the gate control signal and the data control signal is output through the first pin, and a second timing control signal of the gate control signal and the data control signal is supplied to the second pin Output through

According to an embodiment of the present invention, the SCL signal and the SDA signal are input to the first and second pins during a first period, and the first and second timing control signals generated according to the SCL signal and the SDA signal are first applied during the second period. And output to the second pins. As a result, since the embodiment of the present invention can receive the SCL signal and the SDA signal using the first and second pins, as well as output the first and second timing control signals, the first and second timing Pins used for output of control signals can be deleted. That is, according to the exemplary embodiment of the present invention, since the number of input/output pins of the timing controller can be reduced, it is possible to prevent a problem in which the cost of the timing controller increases due to an increase in the size of the timing controller in a high resolution display device.

1 is an exemplary view showing a display device according to an exemplary embodiment of the present invention.
2 is an exemplary view showing a lower substrate, source drive ICs, source flexible films, a source circuit board, a control circuit board, and a timing controller, an EEPROM, and a power supply of a display device according to an embodiment of the present invention.
3 is an exemplary view showing the pixel of FIG. 1;
4 is another exemplary view showing the pixel of FIG. 1;
5 is a block diagram showing a memory, a timing controller, and a level shifter.
6 is a block diagram showing in detail the timing controller according to the first embodiment of the present invention.
7 is a flowchart showing an output of an input/output control signal of an input/output control unit of a timing controller according to an embodiment of the present invention.
8 is a waveform diagram showing an example of signals input/output through first and second pins of the timing controller of FIG. 6;
9 is a block diagram showing in detail a timing controller according to a second embodiment of the present invention.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. It is provided to completely inform the scope of the invention to the possessor, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same elements throughout the specification. In addition, in describing the present invention, when it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When'include','have','consists of' and the like mentioned in the present specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of two parts is described as'upper','upper of','lower of','next to','right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, when a temporal predecessor relationship is described as'after','following','after','before', etc.,'right' or'direct' It may also include cases that are not continuous unless this is used.

First, second, etc. are used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be a second component within the technical idea of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometrical relationship in which the relationship between each other is vertical, and is wider than within the range in which the configuration of the present invention can function It can mean having directionality.

The term “at least one” is to be understood as including all possible combinations from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” means that each of the first item, the second item, or the third item, as well as the first item, the second item, and the third item, It may mean a combination of all items that can be presented from more than one.

Each of the features of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or can be implemented together in an association relationship. May be.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a display device according to an exemplary embodiment of the present invention. 2 is an exemplary view showing a lower substrate, source drive ICs, source flexible films, a source circuit board, a control circuit board, and a timing controller, an EEPROM, and a power supply of a display device according to an exemplary embodiment of the present invention.

The display device according to the exemplary embodiment of the present invention may include any display device that supplies data voltages to pixels by line scanning that supplies gate signals to the gate lines G1 to Gn. For example, a display device according to an embodiment of the present invention includes a liquid crystal display, an organic light emitting display, a field emission display, and an electrophoresis display. display).

1 and 2, a display device according to an exemplary embodiment of the present invention includes a display panel 10, a gate driver 11, a data driver 20, a timing controller 30, a memory 40, and a level. Equipped with a shifter (50).

The display panel 10 includes an upper substrate and a lower substrate. A display area DA including data lines (D1 to Dm, m is a positive integer greater than or equal to 2), gate lines (G1 to Gn, n is a positive integer greater than or equal to 2), and pixels P on the lower substrate Is formed. The pixel P may be connected to any one of the data lines D1 to Dm and to any one of the gate lines G1 to Gn. Accordingly, when the gate signal is supplied to the gate line, the pixel P receives the data voltage of the data line and emits light with a predetermined brightness according to the supplied data voltage.

When the display device is implemented as a liquid crystal display device, each of the pixels P may include a transistor T, a pixel electrode 11, and a storage capacitor Cst as shown in FIG. 2. Transistor T is the kth (k is a positive integer satisfying 1≤k≤n) in response to the gate signal of the gate line Gk j (j is a positive integer satisfying 1≤j≤m) The data voltage of the data line Dj is supplied to the pixel electrode 11. Accordingly, each of the pixels P drives the liquid crystal of the liquid crystal layer 13 by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12. The transmittance amount of light incident from the backlight unit can be adjusted. The common electrode 12 receives a common voltage from the common voltage line VcomL, and the backlight unit is disposed under the display panel 10 to irradiate uniform light onto the display panel 10. In addition, the storage capacitor Cst is provided between the pixel electrode 11 and the common electrode 12 to maintain a constant voltage difference between the pixel electrode 11 and the common electrode 12.

When the display device is implemented as an organic light emitting display device, each of the pixels P includes an organic light emitting diode (OLED), a scan transistor (ST), a driving transistor (DT), and a storage capacitor (Cst) as shown in FIG. 3. can do. The scan transistor ST supplies the data voltage of the j-th data line Dj to the gate electrode of the driving transistor DT in response to the gate signal of the k-th gate line Gk. The driving transistor DT controls a driving current flowing from the high potential voltage line VDDL to the organic light emitting diode OLED according to the data voltage supplied to the gate electrode. The organic light emitting diode OLED is provided between the driving transistor DT and the low potential voltage line VSSL, and emits light with a predetermined brightness according to the driving current. The storage capacitor Cst may be provided between the gate electrode of the driving transistor DT and the high potential voltage line VDDL in order to maintain a constant voltage of the gate electrode of the driving transistor DT.

The gate driver 11 is connected to the gate lines G1 to Gn to supply gate signals. Specifically, the gate driver 11 receives the gate control signal GCS', generates gate signals according to the gate control signal GCS, and supplies them to the gate lines G1 to Gn.

The display panel 10 may be divided into a display area DA and a non-display area NDA. The display area DA is an area in which pixels P are provided and an image is displayed. The non-display area NDA is an area provided around the display area DA, and is an area in which an image is not displayed.

The gate driver 11 may be provided in the non-display area NDA in a gate driver in panel (GIP) method. 1 illustrates that the gate driver 11 is provided on one side of the display area DA, but is not limited thereto. For example, the gate driver 11 may be provided on both sides of the display area DA.

Alternatively, the gate driver 11 may include a plurality of gate drive integrated circuits (hereinafter referred to as “IC”), and the gate drive ICs may be mounted on gate flexible films. Each of the gate flexible films may be a tape carrier package or a chip on film. The gate flexible films can be attached to the non-display area (NDA) of the display panel 10 in a TAB (tape automated bonding) method using an anisotropic conductive flim. It can be connected to (G1~Gn).

The data driver 20 is connected to the data lines D1 to Dm. The data driver 20 receives digital video data DATA and a data control signal DCS from the timing controller 30, and converts the digital video data DATA into analog data voltages according to the data control signal DCS. do. The data driver 20 supplies analog data voltages to the data lines D1 to Dm. The data driver 20 may include one source drive IC or a plurality of source drive ICs.

Each of the source drive ICs 21 may be manufactured as a driving chip. Each of the source drive ICs 21 may be mounted on the source flexible film 60. Each of the source flexible films 60 may be implemented as a tape carrier package or a chip-on film, and may be bent or bent. Each of the source flexible films 60 may be attached to the non-display area of the display panel 10 in a TAB method by using an anisotropic conductive film, whereby the source drive ICs 21 are provided with data lines D1 to Dm. Can be connected to.

Further, the source flexible films 60 may be attached on a source printed circuit board 70. The source printed circuit boards 70 may be flexible printed circuit boards that can be bent or bent. One or a plurality of source printed circuit boards 70 may be provided.

The timing controller 30 receives video data DATA and timing signals TS from an external system board (not shown). The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. In addition, the timing controller 30 receives driving timing information from the memory 40 through a serial clock (SCL) signal SCL and a serial data (SDA) signal SDA.

The timing controller 30 controls the operation timing of the gate control signal GCS and the data driver 20 based on the timing signals TS and driving timing information. Generate a data control signal (DCS).

On the other hand, when the gate driver 11 is provided in the GIP method, the gate clock signals supplied to the gate driver 11 are generated by the level shifter 50 using an on clock signal and an off clock signal, or within the timing controller. It may be generated using an on-clock signal and an off-clock signal.

When the gate clock signals are generated by the level shifter 50, the gate control signal GCS may include a start signal, an on clock signal, and an off clock signal. The start signal is a signal for controlling the start of output of the gate driver 11. The on-clock signal and the off-clock signal are clock signals for generating gate clock signals supplied to the gate driver 11. For example, the gate clock signal may be raised by synchronizing with the rising edge or the falling edge of the on clock signal, and the gate clock signal may be polled by synchronizing with the rising or falling edge of the off-clock signal. The rising edge refers to a period in which the on-clock signal and the off-clock signal rise from the first logic voltage to the second logic voltage. The falling edge refers to a period in which the on-clock signal and the off-clock signal fall from the second logic voltage to the first logic voltage.

When gate clock signals are generated in the timing controller 30, the gate control signal GCS may include a start signal and gate clock signals. In this case, the gate clock signals are generated in the timing controller using the on clock signal and the off clock signal.

Alternatively, when the gate driver 11 is provided in the TAB method, the gate control signal GCS may include a gate start signal, gate shift clocks, and a gate enable signal.

The timing controller 30 supplies video data DATA and a data control signal DCS to the data driver 20. The timing controller 30 supplies the gate control signal GCS to the level shifter 50.

The memory 40 stores driving timing information for driving the display device, such as information required when the timing controller 30 generates the gate control signal GCS and the data control signal DCS. ^{When the display device is powered on, the memory 40 performs I 2} C communication with an electrically erasable programmable read-only memory (EEPROM) through a serial clock (SCL) signal and a serial data (SDA) signal, thereby timing driving timing information. It transmits to the controller 30. Accordingly, the timing controller 30 may generate a gate control signal GCS, a data control signal DCS, and the like according to the driving timing information. The memory 40 may be an electrically erasable programmable read-only memory (EEPROM).

When the gate control signal GCS includes a start signal, an on clock signal, and an off clock signal, the level shifter 50 generates gate clock signals using the on clock signal and the off clock signal. Also, the level shifter 50 changes the swing width of the start signal and the gate clock signals from the first logic voltage and the second logic voltage to the gate low voltage and the gate high voltage.

When the gate control signal GCS includes a start signal and a gate clock signal, or includes a gate start signal, a gate shift clock, and a gate output enable signal, the level shifter 50 performs a swing of the gate control signal GCS. The width is changed from the first logic voltage and the second logic voltage to the gate low voltage and the gate high voltage.

When the timing controller 30 generates the gate control signal GCS swinging at the gate low voltage and the gate high voltage, there is a problem that power consumption increases. Therefore, the timing controller 30 generates a gate control signal GCS that swings between the first logic voltage and the second logic voltage having a small swing width, and uses the level shifter 50 to generate the gate control signal GCS. Change the swing width.

The level shifter 50 supplies the gate control signal GCS' whose swing width is changed to the gate driver 11.

The timing controller 30, the memory 40, and the level shifter 50 may be mounted on the control printed circuit board 90 as shown in FIG. 2. The control printed circuit board 90 and the source printed circuit board 70 may be connected through a flexible circuit board 80 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

5 is a block diagram showing a memory, a timing controller, and a level shifter. In FIG. 5, first and second pins TP1 and TP2 of the timing controller 30, first and second pins MP1 and MP2 of the memory 40 connected to them, and a level shifter ( The first and second pins LP1 and LP2 of 50) are shown.

Referring to FIG. 5, the first pin TP1 of the timing controller 30 is connected to the first pin MP1 of the memory 40 and the first pin LP1 of the level shifter 50. The SCL signal SCL transmitted from the first pin MP1 of the memory 40 is input to the first pin TP1 of the timing controller 30. In addition, the second pin TP2 of the timing controller 30 is connected to the second pin MP2 of the memory 40 and the second pin LP2 of the level shifter 50. The SDA signal SDA transmitted from the second pin MP2 of the memory 40 is input to the second pin TP2 of the timing controller 30.

The timing controller 30 receives driving timing information of the memory 40 through the SCL signal SCL and the SDA signal SDA input to the first and second pins TP1 and TP2. The timing controller 30 may generate driving timing control signals such as the gate control signal GCS and the data control signal DCS according to the driving timing information.

Meanwhile, since the first pin LP1 of the level shifter 50 is also connected to the first pin MP1 of the memory 40, the SCL signal SCL is also input to the first pin LP1 of the level shifter 50. do. In addition, since the second pin LP2 of the level shifter 50 is also connected to the second pin MP2 of the memory 40, the SDA signal SDA is also input to the second pin LP2 of the level shifter 50. do. However, since the SCL signal SCL and the SDA signal SDA are signals independent of the operation of the level shifter 50, the level shifter 50 does not operate even when the SCL signal SCL and the SDA signal SDA are input. Does not.

The first timing control signal, which is one of the driving timing control signals, is output to the first pin LP1 of the level shifter 50 through the first pin TP1 of the timing controller 30. The second timing control signal, which is another one of the driving timing control signals, is output to the second pin LP2 of the level shifter 50 through the second pin TP2 of the timing controller 30. The level shifter 50 receives first and second timing control signals through the first and second pins LP1 and LP2. For example, the first timing control signal may be an on clock signal, and the second timing control signal may be an off clock signal. In this case, the level shifter 50 may generate gate clock signals according to the first and second timing control signals, and the gate clock signal through the clock output pins (CP1 to CPr, r is a positive integer greater than or equal to 2). Can be output to the gate driver 11.

Meanwhile, since the first pin MP1 of the memory 40 is also connected to the first pin LP1 of the level shifter 50, a first timing control signal is also input to the first pin MP1 of the level shifter 40. do. In addition, since the second pin MP2 of the memory 40 is also connected to the second pin LP2 of the level shifter 50, a second timing control signal is also input to the second pin MP2 of the memory 40. . However, since the first and second timing control signals are ^{signals irrelevant to the I 2} C communication, the memory 40 does not transmit any signals even when the first and second timing control signals are input.

As described above, the timing controller 30 according to the embodiment of the present invention not only receives the SCL signal and the SDA signal from the memory 40 through the first and second pins, but also drives the level shifter 50 First and second timing control signals corresponding to the timing control signals may be output. As a result, the timing controller 30 according to an embodiment of the present invention can reduce any two of pins receiving the SCL signal and the SDA signal and the pins outputting the driving timing control signals. Therefore, the embodiment of the present invention can reduce the number of input/output pins of the timing controller, thereby preventing a problem in which the cost of the timing controller increases due to an increase in the size of the timing controller in a high resolution display device.

6 is a block diagram showing in detail the timing controller according to the first embodiment of the present invention. Referring to FIG. 6, the timing controller 30 according to the first embodiment of the present invention includes an input/output control unit 31, a timing control signal supply unit 32, first and second OR gate circuits OR1 and OR2. The first to fourth transistors T1 to T4, an inverter INV2, and first and second pins TP1 and TP2 are included. In FIG. 6, for convenience of description, the input/output control unit 31 of the timing controller 30, the timing control signal supply unit 32, the first and second logic gate circuits OR1 and OR2, and first to fourth transistors ( It should be noted that only T1 to T4), the inverter INV2, and the first and second pins TP1 and TP2 are illustrated.

Referring to FIG. 6, the input/output controller 31 includes first and second input terminals IN1 and IN2 and an output terminal OUT1. Since the first input terminal IN1 of the input/output control unit 31 is connected to the first pin TP1, the SCL signal SCL is input to the first input terminal IN1. Since the second input terminal IN2 of the input/output control unit 31 is connected to the second pin TP2, the SDA signal SDA is input to the second input terminal IN2. The output terminal OUT1 of the input/output control unit 31 outputs the input/output control signal IOCS. The output terminal OUT1 of the input/output controller 31 is connected to the control electrodes of the first and second transistors T1 and T2 and the inverter INV1.

As shown in FIG. 7, the input/output control unit 31 increases the gate-off voltage Voff during the first period t1 in which the SCL signal SCL and the SDA signal SDA are input to the first and second pins TP1 and TP2. Outputs the input/output control signal (IOCS). The gate-off voltage Voff is a voltage capable of turning off the first to fourth transistors when supplied to the control electrodes of the first to fourth transistors. Each of the SCL signal SCL and the SDA signal SDA swings at the first logic voltage LV1 and the second logic voltage LV2 as shown in FIG. 7.

As shown in FIG. 7, when the input of the SCL signal SCL and the SDA signal SDA to the first and second pins TP1 and TP2 is completed, the input/output control unit 31 is Is a positive integer) outputs the input/output control signal IOCS of the gate-on voltage Von during the second period t2 after ms. The gate-on voltage Von is a voltage capable of turning on the first to fourth transistors when supplied to the control electrodes of the first to fourth transistors. The predetermined period of X ms can be appropriately set through prior experimentation.

The timing control signal supply unit 32 includes first and second input terminals IN3 and IN4 and first and second output terminals OUT2 and OUT3. Since the first input terminal IN3 of the timing control signal supply unit 32 is connected to the first pin TP1, the SCL signal SCL is input to the first input terminal IN3. Since the second input terminal IN4 of the timing control signal supply unit 32 is connected to the second pin TP2, the SDA signal SDA is input to the second input terminal IN4. The first output terminal OUT2 of the timing control signal supply unit 32 outputs the first timing control signal TCS1. The first output terminal OUT2 of the timing control signal supply unit 32 is connected to the first input terminal of the first OR gate circuit OR1. The second output terminal OUT3 of the timing control signal supply unit 32 outputs a second timing control signal TCS2. The second output terminal OUT3 of the timing control signal supply unit 32 is connected to the first input terminal of the second OR gate circuit OR2.

The timing control signal supply unit 32 applies the first logic voltage V1 to the first and second pins TP1 and TP2 during a first period t1 in which the SCL signal SCL and the SDA signal SDA are input. One timing control signal TCS1 and a second timing control signal TCS2 are output. When the input of the SCL signal SCL and the SDA signal SDA to the first and second pins TP1 and TP2 is completed, the timing control signal supply unit 32 During the second period t2, the first timing control signal TCS1 and the second timing control signal TCS2 of the second logic voltage V2 are output.

The first OR gate circuit OR1 performs an OR operation on the signal input to the first pin TP1 through the third transistor T3 and the signal output to the first output terminal OUT2 of the timing control signal supply unit 32. And print it out. The second OR gate circuit OR2 performs an OR operation on the signal input to the second pin TP2 through the fourth transistor T4 and the signal output to the second output terminal OUT3 of the timing control signal supply unit 32. And print it out.

The first transistor T1 is turned on by an output signal of the output terminal OUT1 of the input/output controller 31 to electrically connect the first pin TP1 and the output terminal of the first OR gate circuit OR1. . The first transistor T1 includes a control electrode, first and second electrodes, the control electrode is connected to the inverter INV1, the first electrode is connected to the output terminal of the first OR gate circuit OR1, The second electrode is connected to the first pin P1.

The second transistor T2 is turned on by the output signal of the output terminal OUT1 of the input/output controller 31 to electrically connect the second pin TP2 and the output terminal of the second OR gate circuit OR2. . The second transistor T2 includes a control electrode, first and second electrodes, the control electrode is connected to the inverter INV1, the first electrode is connected to the output terminal of the second OR gate circuit OR2, The second electrode is connected to the second pin P2.

The third transistor T3 is turned on by the output signal of the inverter INV1 to electrically connect the first pin TP1 and the input terminal of the first OR gate circuit OR1. The third transistor T3 includes a control electrode, first and second electrodes, the control electrode is connected to the inverter INV1, and the first electrode is connected to the second input terminal of the first OR gate circuit OR1. And the second electrode is connected to the first pin P1.

The fourth transistor T4 is turned on by the output signal of the inverter INV1 to electrically connect the second pin TP2 and the input terminal of the second OR gate circuit OR2. The fourth transistor T4 includes a control electrode, first and second electrodes, the control electrode is connected to the inverter INV1, and the first electrode is connected to the second input terminal of the second OR gate circuit OR2. And the second electrode is connected to the second pin P2.

The inverter INV1 is connected between the control electrodes of the third and fourth transistors T3 and T4 and the output terminal OUT1 of the input/output controller 31. The inverter INV1 inverts the input/output control signal IOCS output to the output terminal OUT1 of the input/output controller 31 and outputs it to the control electrodes of the third and fourth transistors T3 and T4. Turn-on of the first and second transistors T1 and T2 and turn-on of the third and fourth transistors T3 and T4 may be controlled by the inverter INV1 in reverse. That is, when the first and second transistors T1 and T2 are turned on, the third and fourth transistors T3 and T4 are turned off, and the first and second transistors T1 and T2 are turned on. When this is turned off, the third and fourth transistors T3 and T4 may be controlled to be turned on.

Hereinafter, a method of controlling input/output signals and input/output signals to the first and second pins TP1 and TP2 of the timing controller 30 according to the first embodiment of the present invention will be described in detail with reference to FIGS. 6 to 8. Take a look. In FIG. 8, S_P1 denotes a signal input/output to the first pin TP1, and S_P2 denotes a signal input/output to the second pin TP2.

First, during the first period t1, the SCL signal SCL and the SDA signal SDA from the memory 40 start to be input to the first and second pins TP1 and TP2 of the timing controller 30. . The input/output control unit 31 of the timing controller 30 is connected to the first and second pins TP1 and TP2 to receive the SCL signal SCL and the SDA signal SDA. The SCL signal SCL and the SDA signal SDA swing at the first logic voltage LV1 and the second logic voltage LV2 as shown in FIG. 7. When the SCL signal SCL and the SDA signal SDA are input, the input/output control unit 31 outputs the input/output control signal IOCS of the gate-off voltage Voff to the output terminal OUT1. (S101, S102 in Fig. 7)

The first and second transistors T1 and T2 are turned off by the input/output control signal IOCS of the gate-off voltage Voff. Due to the turn-off of the first transistor T1, the output terminal of the first OR gate circuit OR1 and the first pin TP1 are electrically blocked, and the second transistor T2 is turned off. The OR gate circuit OR2 and the second pin TP2 are electrically cut off.

The input/output control signal IOCS of the gate-off voltage Voff is inverted by the inverter INV1 and is supplied to the control electrodes of the third and fourth transistors T3 and T4 as the gate-on voltage Von. The third and fourth transistors T3 and T4 are turned on. Due to the turn-on of the third transistor T3, the second input terminal of the first OR gate circuit OR1 and the first pin TP1 are electrically connected. Due to the turn-on of the fourth transistor T4, the second input terminal of the second OR gate circuit OR2 and the second pin TP2 are electrically connected.

Due to the turn-on of the third and fourth transistors T3 and T4, the timing control signal supply unit 32 is electrically connected to the first and second pins TP1 and TP2. The timing control signal supply unit 32 is connected to the first and second pins TP1 and TP2 to receive the SCL signal SCL and the SDA signal SDA. The timing control signal supply unit 32 generates first and second timing signals TCS1 and TCS2 according to the driving timing information input from the SCL signal SCL and the SDA signal SDA. The timing control signal supply unit 32 outputs the first timing control signal TCS1 to the first output terminal OUT2 and outputs the second timing control signal TCS2 to the second output terminal OUT2.

The first OR gate circuit OR1 performs an OR operation on the SCL signal SCL input to the input terminals and the first timing control signal TCS1 and outputs the OR to the output terminal. However, since the first transistor T1 is turned off and the output terminal of the first OR gate circuit OR1 is not connected to the first pin TP1, no signal is output to the first pin TP1.

The second OR gate circuit OR2 performs an OR operation on the SDA signal SDA input to the input terminals and the second timing control signal TCS2 and outputs the OR to the output terminal. However, since the second transistor T2 is turned off and the output terminal of the second OR gate circuit OR2 is not connected to the second pin TP2, no signal is output to the second pin TP2.

As described above, in the embodiment of the present invention, when the SCL signal SCL and the SDA signal SDA are input during the first period t1, the input/output control signal IOCS of the gate-off voltage Voff is output. . The first and second transistors T1 and T2 are turned off by the input/output control signal IOCs of the gate-off voltage Voff to each of the output terminals of the first and second OR gates OR1 and OR2. And each of the first and second pins TP1 and TP2 are electrically cut off. In addition, the third and fourth transistors T3 and T4 are turned on by the input/output control signal IOCs of the gate-on voltage Von inverted by the inverter, so that the first and second OR gates OR1, Each of the input terminals of OR2) and the first and second pins TP1 and TP2 are electrically connected. As a result, the embodiment of the present invention may receive the SCL signal SCL and the SDA signal SDA through the first and second pins TP1 and TP2 during the first period t1.

Second, when the input of the SCL signal SCL and the SDA signal SDA from the memory 40 is completed, the input/output control unit 31 outputs the input/output control signal IOCS of the gate-on voltage Von after X ms. do. X ms is the SCL signal SCL and SDA signal SDA input to the first and second pins TP1 and TP2 during the first period t1 and the first and second pins ( The first and second timing control signals TCS1 and TCS2 output to the TP1 and TP2 may be appropriately set through a preliminary experiment so that they do not overlap each other. (S103, S104 in Fig. 7)

The first and second transistors T1 and T2 are turned on by the input/output control signal IOCS of the gate-on voltage Von. Due to the turn-on of the first transistor T1, the output terminal of the first OR gate circuit OR1 and the first pin TP1 are electrically connected, and the second transistor T2 is turned on. The OR gate circuit OR2 and the second pin TP2 are electrically connected.

The input/output control signal IOCS of the gate-on voltage Von is inverted by the inverter INV1 and is supplied to the control electrodes of the third and fourth transistors T3 and T4 as the gate-off voltage Voff. The third and fourth transistors T3 and T4 are turned off. Due to the turn-off of the third transistor T3, the second input terminal of the first OR gate circuit OR1 and the first pin TP1 are electrically cut off. Due to the turn-off of the fourth transistor T4, the second input terminal and the second pin TP2 of the second OR gate circuit OR2 are electrically cut off.

Due to the turn-off of the third and fourth transistors T3 and T4, the timing control signal supply unit 32 is not connected to the first and second pins TP1 and TP2. The timing control signal supply unit 32 outputs the first timing control signal TCS1 generated according to the SCL signal SCL and the SDA signal SDA to the first output terminal OUT2 during the first period t1, The second timing control signal TCS2 is output to the second output terminal OUT2.

The first OR gate circuit OR1 performs an OR operation and outputs the signal input from the first pin TP1 and the first timing control signal TCS1. The output terminal of the first OR gate circuit OR1 is connected to the first pin TP1 due to the turn-on of the first transistor T1. Due to the turn-off of the third transistor T3, the second input terminal of the first OR gate circuit OR1 is not connected to the first pin TP1. Therefore, the first OR gate circuit OR1 outputs the first timing control signal TCS1 to the first pin TP1.

The second OR gate circuit OR2 performs an OR operation and outputs the signal input from the second pin TP2 and the second timing control signal TCS2. Due to the turn-on of the second transistor T2, the output terminal of the second OR gate circuit OR2 is connected to the second pin TP2. Due to the turn-off of the fourth transistor T4, the second input terminal of the second OR gate circuit OR2 is not connected to the second pin TP2. Therefore, the second OR gate circuit OR2 outputs the second timing control signal TCS2 to the second pin TP2.

As described above, in the embodiment of the present invention, when the input of the SCL signal SCL and the SDA signal SDA from the memory 40 is completed, the input/output control signal IOCs of the gate-on voltage Von is completed after X ms. Prints. The first and second transistors T1 and T2 are turned on by the input/output control signal IOCS of the gate-on voltage Von to each of the output terminals of the first and second OR gates OR1 and OR2. And each of the first and second pins TP1 and TP2 are electrically connected to each other. In addition, the third and fourth transistors T3 and T4 are turned on by the input/output control signal IOCs of the gate-on voltage Von inverted by the inverter, so that the first and second OR gates OR1, Each of the second input terminals of OR2) and the first and second pins TP1 and TP2 are blocked. As a result, the embodiment of the present invention may output the first and second timing signals TCS1 and TCS2 to the first and second pins TP1 and TP2 during the second period t2.

Consequently, the embodiment of the present invention receives the SCL signal SCL and the SDA signal SDA through the first and second pins TP1 and TP2 during the first period t1, and the SCL signal SCL and the SDA signal The first and second timing control signals TCS1 and TCS2 generated according to (SDA) are applied to the first and second pins during a second period t2 starting after X ms after the first period t1 ends. Output as (TP1, TP2). As a result, the embodiment of the present invention can receive the SCL signal SCL and the SDA signal SDA using the first and second pins TP1 and TP2, as well as the first and second timing control signals. Since (TCS1, TCS2) can be output, pins used for outputting the first and second timing control signals TCS1 and TCS2 can be deleted. That is, according to the exemplary embodiment of the present invention, since the number of input/output pins of the timing controller can be reduced, it is possible to prevent a problem in which the cost of the timing controller increases due to an increase in the size of the timing controller in a high resolution display device.

9 is a block diagram showing in detail a timing controller according to a second embodiment of the present invention. 9, the timing controller 30 according to the second embodiment of the present invention includes an input/output control unit 31, a timing control signal supply unit 32, first and second multiplexers (MUX1, OR2), and first and second multiplexers. It includes second transistors T1 and T2, an inverter INV2, and first and second pins TP1 and TP2. The input/output control unit 31, the timing control signal supply unit 32, and the first and second transistors T1 and T2 shown in FIG. 9 are substantially the same as those described in connection with FIG. 6. Accordingly, detailed descriptions of the input/output control unit 31, the timing control signal supply unit 32, and the first and second transistors T1 and T2 shown in FIG. 9 will be omitted.

The first multiplexer MUX1 includes an SCL signal SCL input to the first pin P1 and a first output terminal OUT2 of the timing control signal supply unit 32 according to the inversion signal of the input/output control signal IOCS. Any one of the first timing control signals TCS1 output as) is output. For example, when the inversion signal of the input/output control signal IOCS is the gate-on voltage Von, the first multiplexer MUX1 outputs the SCL signal SCL input to the first pin P1, and When the inversion signal of the input/output control signal IOCS is the gate-off voltage Voff, the first timing control signal TCS1 is output.

The second multiplexer MUX2 includes an SDA signal SDA input to the second pin P2 and a second output terminal OUT3 of the timing control signal supply unit 32 according to the inversion signal of the input/output control signal IOCS. Any one of the second timing control signals TCS2 output as) is output. For example, the second multiplexer MUX2 outputs the SDA signal SDA input to the second pin P2 when the inversion signal of the input/output control signal IOCS is the gate-on voltage Von, When the inversion signal of the input/output control signal IOCS is the gate-off voltage Voff, the second timing control signal TCS2 is output.

The inverter INV2 is connected between the first and second multiplexers MUX1 and MUX2 and the output terminal OUT1 of the input/output controller 31. The inverter INV2 inverts the input/output control signal IOCs output to the output terminal OUT1 of the input/output control unit 31 and outputs the output to the first and second multiplexers MUX1 and MUX2.

Meanwhile, a method of controlling input/output signals and input/output signals to the first and second pins TP1 and TP2 of the timing controller 30 according to the second embodiment of the present invention illustrated in FIG. 9 is illustrated in FIGS. Since it is substantially the same as described above in conjunction with 8, it is omitted.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: gate driver
20: data driver 21: source drive IC
30: timing controller 31: input/output control unit
32: timing control signal supply unit 40: memory
50: level shifter 60: source soft film
70: source printed circuit board 80: control printed circuit board
90: flexible circuit board

Claims (9)

Equipped with a timing controller that receives driving timing information through the SCL signal and the SDA signal,
The timing controller receives the SCL signal through a first pin and the SDA signal through a second pin, generates first and second timing control signals based on the SCL signal and the SDA signal, and the A display device that outputs the first timing control signal through a first pin and outputs the second timing control signal through the second pin. The method of claim 1,
A display device in which the SCL signal and the SDA signal are input to the first and second pins during a first period, and first and second timing control signals are output to the first and second pins during a second period. The method of claim 2,
A display device in which the second period starts after the first period ends and X (X is a positive integer) ms after the end of the first period. The method of claim 1,
And a memory for storing the driving timing information and outputting the driving timing information to the timing controller through the SCL signal and the SDA signal. The method of claim 4,
A display panel including gate lines, data lines, and pixels formed in crossing regions of the gate lines and data lines;
A gate driver supplying gate signals to the gate lines; And
A display device further comprising a data driver supplying data voltages to the data lines. The method of claim 5,
A display device further comprising a level shifter configured to output clock signals having a swing width of a gate low voltage and a gate high voltage based on the first and second timing control signals. The method of claim 5,
A display device further comprising a level shifter for changing a voltage swing width of the first and second timing control signals from a first logic voltage and a second logic voltage to a gate low voltage and a gate high voltage. The method of claim 6 or 7,
The timing controller outputs the first and second timing control signals to the level shifter through the first and second pins. A display panel including gate lines, data lines, and pixels formed in crossing regions of the gate lines and data lines;
A gate driver supplying gate signals to the gate lines;
A data driver supplying data voltages to the data lines;
A memory for storing timing information of a gate control signal for driving the gate driver and a data control signal for driving the data driver; And
The timing information is received from the memory through a first pin through an SCL signal and a second pin through the SDA signal, generating the gate control signal and the data control signal based on the SCL signal and the SDA signal, And outputting a first timing control signal of the gate control signal and the data control signal through the first pin, and outputting a second timing control signal of the gate control signal and the data control signal through the second pin. A display device having a timing controller.

Images