KR102222934B1 - Method and apparatus for memory allocation in a multi-core processor system, and recoding medium therefor - Google Patents

Abstract

In the present invention, a method and apparatus for allocating a memory in a multi-core processor system, and a recording medium therefor are disclosed. Specifically, in a memory allocation method for shared data in a multi-core processor system, receiving data information and memory access time information for each core, based on the data information and memory access time information for each core Creating a data-memory table by calculating the number of data access times and memory access times for each core, determining a minimum value of the memory access time for each data based on the data-memory table, the determined minimum value and the memory access for each data It may include sorting the difference between times in descending order, and sequentially allocating data to the memory according to the sorted order.

Description

[Method and apparatus for memory allocation in a multi-core processor system, and recoding medium therefor}

The present invention relates to a method and apparatus for allocating a memory in a multi-core processor system, and to a recording medium therefor, and more particularly, a method and apparatus for optimizing memory allocation for shared data in a multi-core processor system, and a recording medium therefor. It is about.

Regarding the existing data integrity securing method, it relates to an apparatus and method for securing the integrity of data through the use of copying shared data in a data processing system, and specifically, information on shared data in an object code processor. An apparatus and method for securing data integrity by acquiring and allocating a copy symbol of shared data to a memory in a linker have been disclosed. However, the existing method suggested a method of securing the integrity of the data through the use of copying shared data, but the method to minimize the overhead of accessing the memory when using the copy of shared data was not suggested, resulting in an optimized result for the use of core and memory. Does not derive.

In order to solve the above problem, there is a need for a method of minimizing memory access time for each core by acquiring information on a task and core accessing each shared data.

US Patent No. 8,464,236, registered on June 11, 2013 (Name: DATA CONSISTENCY IN DATA PROCESSING SYSTEMS)

An object of the present invention is to provide an apparatus and method for minimizing memory access time by storing shared data in an appropriate location in copying use of shared data for data integrity in a multi-core processor system. It is for sake.

The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems that are not mentioned will be clearly understood by those of ordinary skill in the technical field to which the present invention belongs from the following description. I will be able to.

According to an aspect of the present invention, in a method of allocating a shared data memory in a multi-core processor system, receiving data information and memory access time information for each core, the data information and memory access time for each core Creating a data-memory table by calculating the number of data access times and memory access times for each core based on information, determining a minimum value of the memory access time for each data based on the data-memory table, the determined minimum value and the Arranging the difference between the memory access times for each data in descending order, and sequentially allocating data to the memory according to the sorted order.

Another aspect of the present invention is an apparatus for allocating shared data in a multi-core processor system, receiving data information and memory access time information for each core, and receiving the data information and memory access time for each core A data-memory table is created by calculating the number of data access times and memory access times for each core based on the information, and a minimum value of the memory access time for each data is determined based on the data-memory table, and the determined minimum value and the data access time are A memory allocation control unit that sorts differences between memory access times in descending order, and a connection unit that sequentially allocates data to the memory according to the sorted order.

Another aspect of the present invention is a storage recording medium recording a memory allocation program for shared data in a multi-core processor system, receiving data information and memory access time information for each core, the data information And generating a data-memory table by calculating the number of data access times and memory access times for each core based on the memory access time information for each core, determining a minimum value of the memory access time for each data based on the data-memory table. A memory allocation program comprising: sorting the difference between the determined minimum value and the memory access time for each data in descending order, and sequentially allocating data to the memory according to the sorted order.

Preferably, the data information may include a period of a task associated with data and core information to which the task is allocated.

Preferably, when allocating the data to the memory, it may be determined whether the size of the memory is smaller than a memory threshold.

Preferably, when the size of the memory is smaller than the memory threshold, the data may be allocated to a memory whose memory access time is minimum.

Preferably, if the size of the memory is equal to or greater than the memory threshold value, the data may be allocated to a memory having a second priority in the memory access time.

According to an embodiment of the present invention, in a multi-core processor system, an apparatus for controlling memory allocation of shared data receives information on shared data, and determines a storage location of shared data according to access time information according to the storage location. Set.

Through this, the delay time can be reduced by minimizing the memory access overhead, and the system can be optimized by reducing the amount of increase in the load.

In addition, in a data processing system based on a multi-core processor, it is possible to optimize memory use through appropriate distribution of shared data to a plurality of memories.

The effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art from the following description. .

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included as part of the detailed description to aid in understanding of the present invention, provide embodiments of the present invention, and together with the detailed description, the technical features of the present invention are described.
1 shows memory allocation of data during multi-core migration.
2 is a diagram illustrating a memory allocation apparatus for shared data in a multi-core processor system according to an embodiment of the present invention.
3 is a diagram illustrating a method of optimizing memory allocation for shared data in a multi-core processor system according to an embodiment of the present invention.
4 is a diagram illustrating a method of optimizing memory allocation for shared data in a multi-core processor system according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE INVENTION The detailed description to be disclosed below together with the accompanying drawings is intended to describe exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The following detailed description includes specific details to provide a thorough understanding of the present invention. However, one of ordinary skill in the art appreciates that the invention may be practiced without these specific details.

In some cases, in order to avoid obscuring the concept of the present invention, well-known structures and devices may be omitted, or may be illustrated in a block diagram form centering on core functions of each structure and device.

Throughout the specification, when a part is said to "comprising or including" a certain component, it means that other components may be further included rather than excluding other components unless specifically stated to the contrary. do. In addition, terms such as "?? unit", "?? group", and "module" described in the specification mean a unit that processes at least one function or operation, which is implemented by hardware or software or a combination of hardware and software. Can be. In addition, "a or an", "one", "the" and similar related words are different from the present specification in the context of describing the present invention (especially in the context of the following claims). Unless indicated or clearly contradicted by context, it may be used in the sense of including both the singular and the plural.

Specific terms used in the following description are provided to aid understanding of the present invention, and the use of these specific terms may be changed in other forms without departing from the technical spirit of the present invention.

FIG. 1 shows of data during multi-core migration.

1 is a diagram illustrating an operation of a single-core based electronic control unit (ECU). Currently, single-core-based ECUs are reaching the limit of the core load ratio due to the limitation of computing power. Due to the high load factor of the core, it is difficult to apply a new control logic to a controller in a vehicle.

As a result, vehicle developers have increased their interest in vehicle multi-core technology, and are developing and researching multi-core software to solve the above problem. The multi-core-based electronic control device can reduce the load on the core through parallel execution of tasks, and thus solve the problem of applying a new control logic.

In the development of such a vehicle multi-core system, it is very important to ensure data integrity. However, when the integrity of data is secured by copying shared data, access overhead occurs depending on the storage location of the shared data, which increases the delay time. This increase in delay time causes an increase in the load of each core.

It is possible to optimize the data processing system by minimizing the amount of increase in the load. Existing technologies provide a method of securing data integrity, but it cannot be said to be the most optimized system because it cannot provide a method of minimizing the overhead and delay time that occurs when accessing shared data for copy use.

When copying shared data to ensure integrity, it is possible to minimize and optimize the amount of increase in core load by minimizing memory access time.

Accordingly, in order to solve the problems of the prior art, the present invention provides an apparatus and method for minimizing memory access time by storing shared data in an appropriate location in copying and using shared data for data integrity.

In order to solve the above problem, the present invention proposes an apparatus for controlling memory allocation of shared data, which receives information of shared data and sets a storage location of the shared data according to access time information according to the storage location.

In other words, the present invention proposes a memory allocation optimization method for shared data in a multi-core processor system, and for this purpose, a memory allocation control device for shared data for memory allocation optimization and a memory allocation algorithm for minimizing data access overhead. do. The memory allocation control device creates a data-memory table by inputting the number of data accesses per core and memory access time per core. In addition, the memory allocation control device distributes appropriate shared data and optimizes memory use through the generated table and memory allocation algorithm.

The present invention provides an apparatus and a method for minimizing a memory access time by storing shared data in an appropriate location in copy use of shared data for data integrity. This will be described in more detail with reference to the drawings below.

2 is a diagram illustrating a memory allocation apparatus for shared data in a multi-core processor system according to an embodiment of the present invention.

The memory allocation apparatus 200 for shared data in the multi-core processor system according to the present invention shown in FIG. 2 represents functional elements that are functionally divided, and any one or more components may be physically integrated or separated from each other. May be.

Referring to FIG. 2, the memory allocation device 200 may include a memory allocation control unit 210 and a linker 220.

The memory allocation control unit 210 generates optimal memory storage location information (ie, data-memory table) for each shared data.

More specifically, the memory allocation control unit 210 receives the memory access time 201 and shared data information 202 for each core, calculates the total access time for each memory, and generates a data-memory table.

Here, the memory access time information 201 for each core is data measured in an actual embedded system, and the shared data information 202 is the cycle of the task accessing (associated) each data and the task is allocated. Contains the core information.

The memory allocation control unit 210 receives memory access time information 201 and shared data information 202 for each core, calculates the number of data accesses and memory access time for each core using the input information, and based on the calculated result. Create a memory-data table.

In addition, the memory allocation control unit 210 determines a minimum value of the memory access time for each data based on the memory-data table information. In addition, the memory allocation control unit 210 calculates a difference between the selected minimum value and the memory access time for each data. In addition, the memory allocation control unit 210 extracts the difference order value of the minimum value among the calculated results for each data (ie, the difference between the determined minimum value and the memory access time for each data) and sorts it in descending order.

The LINKER 220 creates an executable file 203 by allocating each shared data to an optimal memory location based on the memory-data table information generated by the memory allocation control unit 210. That is, memory is sequentially allocated for each data according to the order in which it is sorted in descending order.

At this time, the LINKER 220 may determine whether the size of the memory is smaller than a threshold value when allocating data to the memory. If the size of the memory is smaller than the memory threshold value during data memory allocation, the LINKER 220 may allocate the corresponding data to a memory whose memory access time is minimum. On the other hand, when the amount of allocable data in the memory is exceeded (that is, when the size of the memory is equal to or greater than the memory threshold when data is allocated), the LINKER 220 accesses the data to the memory. You can allocate it to memory where time is the second priority.

The LINKER 220 may determine whether memory has been allocated for all data, and may repeat the above-described process until all data has been allocated memory.

3 is a diagram illustrating a method of optimizing memory allocation for shared data in a multi-core processor system according to an embodiment of the present invention.

3 shows an example of a memory allocation method for minimizing data access overhead proposed by the present invention.

Referring to FIG. 3, the memory allocation apparatus receives data-related information (ie, shared data information) (S301), and also receives memory access time information for each core (S302).

Here, the data-related information (ie, shared data information) includes a period of a task accessing (associated with) each data and core information to which the task is allocated.

The memory allocation device generates a data-memory table by calculating the number of data access times and memory access times for each core using the received information (S303).

The memory allocation apparatus determines a minimum value of the memory access time for each data using the generated table (S304), and calculates a difference between the selected minimum value and the memory access time for each data (S305).

The memory allocation device extracts the difference rank value of the minimum value among the calculated results for each data (i.e., the difference between the determined minimum value and the memory access time for each data), sorts it in descending order (S306), and sequentially stores each data into memory. Is assigned (S307).

In this case, the memory allocating apparatus may determine whether the size of the memory is smaller than the threshold value when allocating data in memory (S508).

If the size of the memory is smaller than the memory threshold value during data memory allocation, the memory allocating device may allocate the corresponding data to a memory whose memory access time is the minimum (S309).

On the other hand, when the amount of allocable data in the memory is exceeded (that is, when the size of the memory is equal to or greater than the memory threshold when the data is allocated), the memory allocation device allocates the data to the memory with the second priority in the memory access time It can be done (S310).

The memory allocating apparatus may determine whether memory has been allocated for all data (S311), and may repeat steps S307 to S310 above until all data is allocated memory.

4 is a diagram illustrating a method of optimizing memory allocation for shared data in a multi-core processor system according to an embodiment of the present invention.

4 is an example of data allocation using memory access time information and data information for each core.

Table 1 of FIG. 4 is a table of the number of times each core accesses data, and Table 2 of FIG. 4 is a table of times when each core accesses a memory.

By thinking of each of the two tables as a matrix and multiplying them, the memory allocation control unit can generate a data-memory table as shown in Table 3 of FIG. 4. When the algorithm of the present invention is applied to the generated table, the memory allocation control unit can sequentially arrange data and memory information as shown in Table 4 of FIG. 4. In Table 3 of FIG. 4, when the shared data D1 is allocated to the memory M1, the access time is 22 * 10 + 12 * 20 = 460. In the same way, when each data is allocated to each memory, the number of accesses is obtained as shown in Table 3. At this time, the priority of each data to be stored in the memory is obtained by considering the capacity limit of each memory. First, in the example of Table 3, when D1 is allocated to M1, the access time is shortest, so the efficiency is the best. Similarly, when D2 is assigned to M2 and D3 is assigned to M1, the efficiency is best. At this time, D1 and D3 are preferably allocated to M1. However, since the memory capacity is limited, the priority of data to be stored in M1 is required. In the method proposed in the present invention, priority is given in consideration of a difference between the time of the data to be allocated with the next priority outside the area where each data is to be stored with the highest priority. For example, it is efficient to store D1 in M2 in a second order other than M1. At this time, it takes a total access time of 560, which reduces the time efficiency of 100 (560-460) compared to when stored in M1. Likewise, it is efficient to store D3 in M2 in the order of M1 out-of-order. At this time, it takes a total access time of 260, and the time efficiency of 40 (260-220) decreases compared to when stored in M1. Considering the decrease in time efficiency of 100 and 40, since the time decrease efficiency of D1 is greater, the priority of M1 placement of D1 is higher than that of D3. If the placement priority is determined in the same way, they are sorted in descending order as shown in Table 4.

Thereafter, the LINKER may allocate data to each memory using the information in Table 4 of FIG. 4. It is most advantageous in terms of optimization that the data D1 of FIG. 4 is allocated to the memory M1 of FIG. 4, and it can be predicted that a system optimized for the core and the memory can be designed when the present invention is applied.

The embodiments described above are those in which constituent elements and features of the present invention are combined in a predetermined form. Each component or feature should be considered optional unless explicitly stated otherwise. Each component or feature may be implemented in a form that is not combined with other components or features. In addition, it is also possible to constitute an embodiment of the present invention by combining some components and/or features. The order of operations described in the embodiments of the present invention may be changed. Some configurations or features of one embodiment may be included in other embodiments, or may be replaced with corresponding configurations or features of other embodiments. It is obvious that the embodiments may be configured by combining claims that do not have an explicit citation relationship in the claims or may be included as new claims by amendment after filing.

The embodiment according to the present invention may be implemented by various means, for example, hardware, firmware, software, or a combination thereof. In the case of implementation by hardware, an embodiment of the present invention is one or more ASICs (application specific integrated circuits), DSPs (digital signal processors), DSPDs (digital signal processing devices), PLDs (programmable logic devices), FPGAs ( field programmable gate arrays), processors, controllers, microcontrollers, microprocessors, etc.

In the case of implementation by firmware or software, an embodiment of the present invention may be implemented in the form of a module, procedure, or function that performs the functions or operations described above. The software code can be stored in a memory and driven by a processor. The memory may be located inside or outside the processor, and may exchange data with the processor through various known means.

It is apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential features of the present invention. Therefore, the above detailed description should not be construed as restrictive in all respects, but should be considered as illustrative. The scope of the present invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the present invention are included in the scope of the present invention.

The memory allocation method for shared data according to the present invention can be applied to various multi-core processor systems.

200: memory allocation device
201: Memory access time information for each core
202: data information
203: executable file
210: memory allocation control unit
220: connection

Claims (7)

In the memory allocation method of shared data in a multi-core (multi-core) processor system,
Receiving data information indicating the number of data accesses for each core and memory access time information for each core;
Generating a data-memory table by considering the first table including the data information and the second table including the memory access time information for each core as a matrix, and multiplying the first table and the second table with each other ;
Determining a minimum value of a memory access time for each data based on the data-memory table;
Sorting the difference between the determined minimum value and the memory access time for each data in descending order; And
And sequentially allocating data to the memory according to the sorted order. The method of claim 1,
The data information includes a period of a task associated with data and information on a core to which the task is allocated. The method of claim 1,
When allocating the data to the memory, determining whether the size of the memory is smaller than a memory threshold. The method of claim 3,
When the size of the memory is less than the memory threshold, the data is allocated to a memory whose memory access time is minimum. The method of claim 3,
When the size of the memory is equal to or greater than the memory threshold value, the data is allocated to a memory whose memory access time is a difference priority. In the memory allocation apparatus for shared data in a multi-core (multi-core) processor system,
By receiving data information and memory access time information for each core, and calculating the number of data accesses and memory access time for each core based on the data information and the memory access time information for each core, a data-memory table is created, and the data- A memory allocation control unit that determines a minimum value of a memory access time for each data based on a memory table, and arranges a difference between the determined minimum value and the memory access time for each data in descending order; And
Apparatus comprising a connection unit for sequentially allocating data to the memory according to the sorted order. In a recording medium storing a memory allocation program of shared data in a multi-core processor system,
Receiving data information indicating the number of data accesses for each core and memory access time information for each core;
Generating a data-memory table by considering the first table including the data information and the second table including the memory access time information for each core as a matrix, and multiplying the first table and the second table with each other ;
Determining a minimum value of a memory access time for each data based on the data-memory table;
Sorting the difference between the determined minimum value and the memory access time for each data in descending order; And
A computer-readable recording medium recording a memory allocation program comprising the step of sequentially allocating data to a memory according to the sorted order.

Images