KR102221212B1 - Array substrate and manufacturing method thereof - Google Patents

Abstract

The array substrate includes a pixel electrode and a common electrode line on the insulating layer, and a connection electrode connected to the common electrode through a contact hole on the common electrode line, so that the common electrode line can be easily connected to the common line through the connection electrode. I can.

Description

Array substrate and manufacturing method thereof TECHNICAL FIELD

The present invention relates to an array substrate and a method of manufacturing the same.

A display device is a device that displays an image or information. Among the display devices, a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

In the liquid crystal display, a data voltage is supplied from a source drive to a liquid crystal display panel based on a timing control signal provided from a timing controller, and an image is displayed.

A liquid crystal display panel includes an array substrate on which a plurality of thin film transistors are arrayed, a color filter substrate on which a plurality of color filters corresponding to each thin film transistor are arranged, and a liquid crystal layer disposed between the substrates.

In the array substrate, in addition to the thin film transistor, many layers must be patterned, and thus the number of masks increases.

One mask process requires a pre-cleaning process, a photo process, an exposure process, a developing process and a post process. In addition, an alignment process is required between these processes.

Therefore, as the number of masks increases, detailed processes increase exponentially.

Recently, various process methods for reducing the number of masks have been developed, but it is difficult to reduce the number of masks to a satisfactory number.

In addition, there is a problem in that misalignment occurs due to difficult alignment control due to process constraints used in each mask process.

It is an object of the present invention to solve the above and other problems.

Another object of the present invention is to provide an array substrate with a reduced number of masks and a method of manufacturing the same.

Another object of the present invention is to provide an array substrate that prevents misalignment and a method of manufacturing the same.

In order to achieve the above or other objects, according to an aspect of the present invention, the array substrate includes a pixel electrode and a common electrode line on an insulating layer, and a connection electrode connected to the common electrode through a contact hole on the common electrode line. , It is possible to easily connect the common electrode line to the common line through the connection electrode.

The method of manufacturing an array substrate is to form an alignment key and a planarization layer on the data line, source electrode, and drain electrode, but not on the alignment key, so that an opaque conductive film is formed on the alignment key. Even if it is formed and it is difficult to identify an alignment key during an alignment process, alignment is possible through the presence or absence of a planarization layer, thereby preventing misalignment.

The effect of the terminal according to the present invention will be described as follows.

According to at least one of the embodiments of the present invention, while the flattening layer is formed in the display area, the flattening layer is not formed in the non-display area, so that even if it is difficult to identify an alignment key due to an opaque metal film in a post process There is an advantage in that the occurrence of misalignment can be prevented when the photosensitive layer for forming the photosensitive pattern is patterned due to a step difference due to the presence or absence of the organic layer in the area and the non-display area.

According to at least one of the embodiments of the present invention, a semiconductor layer and a data line are formed at the same time, a planarization layer and a common electrode are formed at the same time, and a connection electrode for connecting the common electrode line to the common line is formed at the same time as the pixel electrode. By doing so, there is an advantage in that the number of mask processes can be reduced and the process can be simplified.

Further scope of the applicability of the present invention will become apparent from the detailed description below. However, since various changes and modifications within the spirit and scope of the present invention can be clearly understood by those skilled in the art, specific embodiments such as the detailed description and preferred embodiments of the present invention should be understood as being given by way of example only.

1 is a plan view illustrating an array substrate of a liquid crystal display panel according to the present invention.
2 is a cross-sectional view illustrating an array substrate of a liquid crystal display panel according to the present invention.
3 to 7 are diagrams illustrating a method of manufacturing an array substrate of a liquid crystal display panel according to the present invention.

Hereinafter, exemplary embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but identical or similar elements are denoted by the same reference numerals regardless of reference numerals, and redundant descriptions thereof will be omitted. The suffixes "module" and "unit" for components used in the following description are given or used interchangeably in consideration of only the ease of preparation of the specification, and do not have meanings or roles that are distinguished from each other by themselves. In addition, in describing the embodiments disclosed in the present specification, when it is determined that a detailed description of related known technologies may obscure the subject matter of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are for easy understanding of the embodiments disclosed in the present specification, and the technical idea disclosed in the present specification is not limited by the accompanying drawings, and all modifications included in the spirit and scope of the present invention It should be understood to include equivalents or substitutes.

1 is a plan view illustrating an array substrate of a liquid crystal display panel according to the present invention.

The liquid crystal display panel according to the present invention may include an array substrate, a color filter substrate, and a liquid crystal layer formed between the substrates.

A plurality of pixels P may be defined by the intersection of the plurality of gate lines 11 and the plurality of data lines 23 on the array substrate. Each pixel P may include a thin film transistor connected to the gate line 11 and the data line 23 and a pixel electrode 45 connected to the thin film transistor. The pixel electrodes 45 formed on each pixel P may be spaced apart from each other.

A common electrode 37 for supplying a common voltage may be provided separately from the pixel electrode 45.

The liquid crystal display panel according to the present invention may be driven by a horizontal electric field method (IPS: In-Plane Switching).

To this end, a horizontal electric field is generated by the data voltage applied to the pixel electrode 45 and the common voltage applied to the common electrode 37, and the liquid crystal molecules of the liquid crystal layer are displaced by this horizontal electric field, and by this displacement An image can be displayed by adjusting the light transmittance.

Referring to FIG. 1, a gate line 11 may be disposed along a first direction, eg, a horizontal direction, and a data line 23 may be disposed along a second direction, eg, a vertical direction. The gate line 11 and the data line 23 may be disposed to cross each other.

The gate electrode 13 may be disposed extending from the first side of the gate line 11. In addition, the source electrode 24 may be disposed extending from the first side of the data line 23, and the drain electrode 33 may be disposed to be spaced apart from the source electrode 24. The source electrode 24 and the drain electrode 33 may be disposed on the gate electrode 13.

Although not shown, a semiconductor layer may be disposed between the gate electrode 13 and the source electrode 24/drain electrode 33. Accordingly, a thin film transistor including the gate electrode 13, the semiconductor layer, and the source electrode 24/drain electrode 33 may be formed. In such a thin film transistor, the semiconductor layer 18 is activated according to a scan signal applied to the gate electrode 13 through the gate line 11, and accordingly, the data voltage applied to the source electrode 24 through the data line 23 It can be supplied to the drain electrode 33 via the semiconductor layer 18. The data voltage supplied to the drain electrode 33 may be supplied to the pixel electrode 45 electrically connected to the drain electrode 33.

If the gate electrode 13 is not disposed, the gate line 11 itself serves as the gate electrode 13, and in this case, the source electrode 24 and the drain electrode 33 are on the gate line 11 It can also be placed.

The lower gate electrode 19 may be disposed extending from the second side of the gate line 11. The data lower electrode 29 may be disposed extending from the second side of the data line 23.

The upper gate electrode 21 may be electrically connected to the lower gate electrode 19 through the gate contact hole 17. The gate contact hole 17 may be formed so that the lower gate electrode 19 and the upper gate electrode 21 are disposed on different layers to connect them. The gate pad portion 15 may be formed by the lower gate electrode 19 and the upper gate electrode 21. The gate driving circuit may be electrically connected to the gate pad unit 15, specifically, the gate upper electrode 21. Accordingly, the scan signal supplied from the gate driving circuit may be supplied to the gate line 11 and the gate electrode 13 through the gate pad unit 15.

The data upper electrode 31 may be electrically connected to the data lower electrode 29 through the data contact hole 27. The data contact hole 27 may be formed so that the data lower electrode 29 and the data upper electrode 31 are disposed on different layers to connect them. The data pad part 25 may be formed by the data lower electrode 29 and the data upper electrode 31. The data driving circuit may be electrically connected to the data pad unit 25, specifically, the data upper electrode 31. Accordingly, the scan signal supplied from the data driving circuit may be supplied to the data line 23 and the source electrode 24 through the data pad unit 25.

The alignment key 20 may be disposed adjacent to the gate pad unit 15. The alignment key 20 may be disposed on the same layer as the gate line 11, the gate electrode 13, and the lower gate electrode 19. The alignment key 20 may serve as a reference key for aligning the photosensitive layer to a specific region of the photosensitive layer as an exposure source of the exposure apparatus when patterning the photosensitive layer by an exposure process.

The liquid crystal display panel may be divided into a display area and a non-display area. The display area is an area that displays an image, and the non-display area is an area that does not display an image. A plurality of pixels each including the thin film transistor and the pixel electrode 45 may be included in the display area. The gate pad part 15, the data pad part 25, and the alignment key 20 may be disposed in the non-display area.

The pixel may include a thin film transistor and a pixel electrode 45. The pixel electrode 45 may be electrically connected to the drain electrode 33 of the thin film transistor through the pixel contact hole 35. The pixel contact hole 35 may be formed so that the drain electrode 33 and the pixel electrode 45 are disposed on different layers to connect them.

The pixel electrode 45 may include a plurality of pixel electrode bars 41 to 44 along the second direction. Each of the pixel electrode bars 41 to 44 may be spaced apart from each other.

A portion of each of the pixel electrode bars 41 to 44 may have a bent shape. For example, each of the pixel electrode bars 41 to 44 may be bent to have an acute angle around a reference line in a first direction, for example, a horizontal direction when viewed from right to left. The data line 23 may also have a bent shape corresponding to each of the pixel electrode bars 41 to 44. In this way, when each of the pixel electrode bars 41 to 44 is bent, the displacement of the liquid crystal molecules due to the horizontal electric field is further increased, and in particular, recovery of the liquid crystal molecules is facilitated, so that the image quality can be improved.

Although not shown, the common electrode 37 may be disposed under each of the pixel electrode bars 41 to 44. The common electrode 37 may be integrally disposed on all the pixels P. That is, the common electrode 37 is not spaced apart from each pixel P like the pixel electrode 45 and may be integrally disposed in all pixels. Accordingly, the common electrode 37 may be disposed not only on the pixel but also on the gate line 11, the data line 23, and the thin film transistor disposed adjacent to the boundary between the pixels. In contrast, the pixel electrode 45 may not be disposed on the gate line 11, the data line 23, and the thin film transistor, but may be disposed on the pixel.

The common electrode line 47 may be disposed on the gate line 11. Although not shown, a pad portion (not shown) of the common electrode 37 connected to the common electrode line 47 may be disposed separately from the gate pad. By arranging the common electrode line 47 on the gate line 11, the aperture ratio of the pixel can be improved.

The connection electrode 50 electrically connects the common electrode line 47 to the common electrode 37. That is, the first side of the connection electrode 50 may be electrically connected to the common electrode line 47, and the second side of the connection electrode 50 may be electrically connected to the common electrode 37 through the jumping contact hole 49. have. The jumping contact hole 49 may be formed to connect the common electrode 37 and the common electrode line 47 by being disposed on different layers.

The jumping contact hole 49 may be adjacent to the gate line 11 or may be positioned on a part of the gate line 11. In addition, the jumping contact hole 49 may be disposed adjacent to the common electrode line 47. In this way, the jumping contact hole 49 is disposed adjacent to the common electrode line 47, so that the connection electrode 50 connected to the common electrode 37 from the common electrode line 47 through the jumping contact hole 49 The length of the can be minimized.

Since the size of the connection electrode 50 is at least larger than the width of the common electrode line 47, the connection electrode 50 may cover the common electrode line 47 along the width direction of the common electrode line 47. . The connection electrode 50 may directly contact the top and side surfaces of the common electrode line 47. Accordingly, the common voltage applied to the common electrode line 47 may be supplied to the common electrode 37 through the connection electrode 50.

2 is a cross-sectional view illustrating an array substrate of a liquid crystal display panel according to the present invention.

FIG. 2 is a cross-sectional view of an array substrate of the liquid crystal display panel of FIG. 1 taken along lines I-I, II-II', and lines III-III.

Referring to FIG. 2, a gate line 11, a gate electrode 13, a lower gate electrode 19, and an alignment key 20 may be disposed on a substrate 10.

The gate electrode 13 may be a part of the thin film transistor, and the gate lower electrode 19 may be a part of the gate pad part 15.

The gate electrode 13 may be disposed extending from the first side of the gate line 11, and the gate lower electrode 19 may be disposed extending from the second side of the gate line 11. The alignment key 20 may be spaced apart from the gate line 11, the gate electrode 13, and the lower gate electrode 19.

Each of the gate line 11, the gate electrode 13, the lower gate electrode 19, and the alignment key 20 may include first to third conductive patterns 101, 103, and 105. The second conductive patterns 103a, 103b, and 103c are disposed on the first conductive patterns 101a, 101b, and 101c, and the third conductive patterns 105a, 105b, and 105c are the second conductive patterns 103a, 103b, and 103c. ) Can be placed on.

Each of the first to third conductive patterns 101, 103, and 105 may have the same size, but is not limited thereto. In this way, since the first to third conductive patterns 101, 103, and 105 have the same size, the first to third conductive patterns 101, 103, and 105 are simultaneously formed by a single etching process to simplify the process. Can be.

The first conductive patterns 101a, 101b, and 101c include, for example, MoTi, the second conductive patterns 103a, 103b, and 103c include, for example, Cu, and the third conductive patterns 105a, 105b, and 105c are, for example, ITO. It may include, but is not limited thereto. The first conductive patterns 101a, 101b, and 101c may enhance adhesion to the substrate 10. The second conductive patterns 103a, 103b, and 103c have excellent electrical characteristics to facilitate signal flow. The third conductive patterns 105a, 105b, and 105c prevent corrosion of the second conductive patterns 103a, 103b, and 103c by the etching solution during the patterning process of the common electrode line 47, as described later in the process. Can give.

The first insulating layer 12 may be disposed on the gate line 11, the gate electrode 13, the lower gate electrode 19, and the alignment key 20. The first insulating layer 12 may be formed of an inorganic material such as SiOx or SiNx, but is not limited thereto.

A semiconductor layer 18, a data line 23, a source electrode 24, a drain electrode 33, and a data lower electrode 29 may be disposed on the first insulating layer 12.

The semiconductor layer 18 may be disposed on the gate electrode 13, and the source electrode 24, the drain electrode 33, and the data lower electrode 29 may be disposed on the semiconductor layer 18 to be spaced apart from each other. The source electrode 24 may be disposed to extend from the first side of the data line 23, and the data lower electrode 29 may be disposed to extend from the second side of the data line 23.

The semiconductor layer 18 may include any one of amorphous silicon (a-Si), polysilicon (p-Si), low-temperature polysilicon (LTPS), and oxide.

Each of the data lower electrodes 29 may include a semiconductor pattern 113a and a conductive pattern 115a. The semiconductor pattern 113a may be formed of the same material as the semiconductor layer 18, and the conductive pattern 115a may be formed of the same material as the data line 23, the source electrode 24, and the drain electrode 33.

The conductive pattern 115a, the data line 23, the source electrode 24, and the drain electrode 33 are each a gate line 11, a gate electrode 13, a lower gate electrode 19, and an alignment key 20. Like each, the first to third conductive patterns 101, 103, and 105 may be included. The first conductive patterns 101a, 101b, and 101c include, for example, MoTi, the second conductive patterns 103a, 103b, and 103c include, for example, Cu, and the third conductive patterns 105a, 105b, and 105c are, for example, ITO. It may include, but is not limited thereto.

The first insulating layer 12 may electrically insulate the gate line 11 and the data line 23 intersecting each other.

The second insulating layer 14 is disposed on the data line 23, the source electrode 24, the drain electrode 33, the data lower electrode 29, the gate lower electrode 19, and the alignment key 20. I can. Specifically, the second insulating layer 14 is disposed on the first insulating layer 12 corresponding to the lower gate electrode 19 and the alignment key 20, and the data line 23 and the source electrode 24 , May be disposed on the drain electrode 33 and the data lower electrode 29.

The second insulating layer 14 may be formed of an inorganic material such as SiOx or SiNx, but is not limited thereto.

The planarization layer 16 may be disposed on the second insulating layer 14 corresponding to the display area including the plurality of pixels P. The planarization layer 16 is not disposed on the gate lower electrode 19, the data lower electrode 29, and the alignment key 20 disposed in the non-display area.

The planarization layer 16 may be formed of an organic material such as photo acryl, but is not limited thereto. The planarization layer 16 has a flat top surface to prevent disconnection of a pattern or layer on the planarization layer 16, and between the common electrode 37 and the pixel electrode 45 disposed on the planarization layer. The image quality can be improved by generating a uniform horizontal electric field.

The planarization layer 16 may have a pixel contact hole 35. The pixel contact hole 35 may be formed to penetrate from the lower surface of the planarization layer 16 to the upper surface. The pixel contact hole 35 may be disposed on a part of the drain electrode 33. The pixel contact hole 35 may be formed to electrically connect the pixel electrode 45 to be described later to the drain electrode 33 of the thin film transistor.

The second insulating layer 14 may compensate for low adhesion between the planarization layer 16 and the data line 23, the source electrode 24, the drain electrode 33, and the data lower electrode 29. That is, since the second insulating layer 14 has excellent adhesion to the data line 23, the source electrode 24, the drain electrode 33, and the data lower electrode 29, the second insulating layer 14 is interposed. The furnace planarization layer 16 is strongly attached to the data line 23, the source electrode 24, the drain electrode 33, and the data lower electrode 29 to prevent peel-off of the planarization layer 16. Can be.

A common electrode 37 may be disposed on the planarization layer 16. The common electrode 37 may be disposed on the entire display area, that is, on the plurality of pixels P.

The common electrode 37 may be formed of, for example, a transparent conductive material such as ITO, but is not limited thereto.

A third insulating layer 39 may be disposed on the common electrode 37. In addition, the third insulating layer 39 may be disposed on the second insulating layer 14 corresponding to the lower gate electrode 19, the alignment key 20, and the lower data electrode 29.

The third insulating layer 39 may be formed of an inorganic material such as SiOx or SiNx, but is not limited thereto.

The third insulating layer 39 may have a jumping contact hole 49. Although the jumping contact hole 49 is not shown, the aperture ratio of the pixel may be secured by being disposed adjacent to the gate line 11 or on a part of the gate line 11.

The pixel electrode 45 and the common electrode line 47 may be disposed on the third insulating layer 39. That is, the pixel electrode 45 and the common electrode line 47 may be disposed on the same layer. Since the pixel electrode 45 and the common electrode line 47 are not disposed on different layers, the thickness of the array substrate can be reduced.

The pixel electrode 45 may include a plurality of pixel electrode bars 41 to 44 spaced apart from each other. A portion of the pixel electrode 45 may be electrically connected to the drain electrode 33 of the thin film transistor through the pixel contact hole 35.

When the semiconductor layer 18 is activated by a scan signal supplied to the gate electrode 13 through the gate line 11, the data line 23, the source electrode 24, the semiconductor layer 18, and the drain electrode ( The data voltage supplied to 33) may be applied to the pixel electrode bars 41 to 44 of the pixel electrode 45.

A horizontal electric field may be generated by a data voltage applied to the pixel electrode bars 41 to 44 and a common voltage applied to the common electrode 37. In addition, since the common electrode 37 is disposed under the pixel electrode bars 41 to 44, a vertical electric field may also be generated. In this way, since a horizontal electric field and a vertical electric field are generated together between the pixel electrode bars 41 to 44 and the common electrode 37, the displacement of the liquid crystal molecules is further increased while the displacement of the liquid crystal molecules can be more precisely controlled. Picture quality can be significantly improved.

The pixel electrode 45 may be formed of a transparent conductive material such as ITO.

The common electrode line 47 may be disposed adjacent to the pixel electrode 45. In addition, the common electrode line 47 may be disposed adjacent to the jumping contact hole 49. The jumping contact hole 49 may be disposed between the pixel electrode 45 and the common electrode line 47.

The common electrode line 47 may be one metal selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, and Cu, or an alloy thereof, and may be formed as a single layer or multiple layers. Since the common electrode line 47 is opaque, it may be disposed on the gate line 11 so as not to interfere with the aperture ratio of the pixel.

The common voltage supplied to the common electrode line 47 may be applied to the common electrode 37 through the connection electrode 50 and the jumping contact hole 49.

The connection electrode 50 may be disposed on the third insulating layer 39 to connect the common electrode line 47 and the common electrode 37. The connection electrode 50 may directly contact the common electrode line 47 and may contact the common electrode 37 through the jumping contact hole 49.

In this way, since the connection electrode 50 is not connected through a contact hole formed in a separate insulating layer and directly contacts the common electrode line 47, the thickness of the array substrate may be reduced.

The connection electrode 50 may be formed of a transparent conductive material such as ITO. The connection electrode 50 may be formed of the same material as the pixel electrode 45, but is not limited thereto.

Meanwhile, the gate upper electrode 21 and the data upper electrode 31 may be disposed on the third insulating layer 39.

The upper gate electrode 21 may be electrically connected to the lower gate electrode 19 through the gate contact hole 17. Accordingly, the gate pad portion 15 may be formed by the lower gate electrode 19 and the upper gate electrode 21.

The data upper electrode 31 may be electrically connected to the data lower electrode 29 through the data contact hole 27. Accordingly, the data pad portion 25 may be formed by the data lower electrode 29 and the data upper electrode 31.

3 to 7 are diagrams illustrating a method of manufacturing an array substrate of a liquid crystal display panel according to the present invention.

1st mask process

3 shows a first mask process of forming a gate line, a gate electrode, a lower gate electrode, and an alignment key.

3A, a first conductive film 101, a second conductive film 103, and a third conductive film 105 are sequentially formed on the substrate 10, and a third conductive film 105 A photosensitive film may be formed thereon. The photosensitive layer may be exposed using an exposure process to form a photosensitive pattern 107 on the third conductive layer 105.

The first conductive film 101 includes, for example, MoTi, the second conductive film includes, for example, Cu, and the third conductive film, for example, may include ITO, but is not limited thereto. The first conductive layer 101 may enhance adhesion to the substrate 10. The second conductive layer 103 has excellent electrical characteristics to facilitate signal flow. As described later in the process, the third conductive layer 103 may prevent the second conductive layer 103 from being corroded by the etching solution during the patterning process of the common electrode line 47.

Using the photosensitive pattern 107 as a mask, the third conductive film 105, the second conductive film 103, and the first conductive film 101 are sequentially patterned, and the gate line 11 is formed as shown in FIG. 3B. , A gate electrode 13, a lower gate electrode 19, and an alignment key 20 may be formed.

Each of the gate line 11, the gate electrode 13, the lower gate electrode 19, and the alignment key 20 includes first conductive patterns 101a, 101b, and 101c formed from the first conductive layer 101, and the second Second conductive patterns 103a, 103b, and 103c formed from the conductive layer 103 and third conductive patterns 105a, 105, and 105c formed from the third conductive layer 105 may be included.

Since the first to third conductive patterns 101, 103, and 105 are collectively formed by the same photosensitive pattern 107, the etching process can be simplified.

As the first to third conductive patterns 101, 103, and 105 are collectively formed, the sizes of the first to third conductive patterns 101, 103, and 105 are the same.

2nd mask process

4 shows a second mask process of forming a semiconductor layer, a data line, a source electrode, a drain electrode, and a data lower electrode.

As shown in FIG. 4A, an insulating film 111, a semiconductor film 113, and a conductive film are formed on the gate line 11, the gate electrode 13, the gate lower electrode 19, and the alignment key 20. 115) may be sequentially formed, and a photosensitive layer may be formed on the conductive layer 115. The photosensitive layer may be exposed using an exposure process to form a photosensitive pattern 117 on the conductive layer 115.

The insulating layer 111 may be formed of an inorganic material such as SiOx or SiNx, but is not limited thereto. The semiconductor layer 112 may include any one of amorphous silicon (a-Si), polysilicon (p-Si), low-temperature polysilicon (LTPS), and oxide. The conductive layer 113 may include first to third conductive layers 101, 103, and 105 as shown in FIG. 3A. The first conductive layer 101 includes, for example, MoTi, the second conductive layer 103 pattern includes, for example, Cu, and the third conductive layer 105 may include, for example, ITO. Not limited.

Using the photosensitive pattern 117 as a mask, the conductive film 115 and the semiconductor film 113 are patterned in order, and as shown in FIG. 4B, the data line 23, the source electrode 24, and the drain electrode 33 are formed. And a data lower electrode 29 may be formed. The insulating layer 111 may be the first insulating layer 12. Since the third conductive pattern 105, which is the uppermost layer of the drain electrode 33, is formed of ITO, when the conductive film (133 in FIG. 6B) is patterned in a subsequent process by the third layer 105, it is removed by the etching solution. Corrosion of the second conductive pattern 103 disposed under the 3 conductive pattern 105 may be prevented.

The semiconductor layer 18, the data line 23, the source electrode 24, the drain electrode 33, and the data lower electrode 29 are simultaneously formed by the same photosensitive pattern 117, so that the process can be simplified.

In the present invention, since the semiconductor layer 18 and the source electrode 24/drain electrode 33 are simultaneously formed by the second mask process, the process can be simplified.

3rd mask process

5 shows a third mask process of forming a common electrode.

5A, an insulating film 121 and an organic film 123 are formed on the semiconductor layer 18, the data line 23, the source electrode 24, the drain electrode 33, and the data lower electrode 29. ) And the conductive layer 125 may be sequentially formed, and a photosensitive layer may be formed on the conductive layer 125. The photosensitive layer may be exposed using an exposure process to form a first photosensitive pattern 127 on the conductive layer.

The insulating layer 121 may be formed of an inorganic material such as SiOx or SiNx, but is not limited thereto. The organic layer 123 may be formed of an organic material such as photo acryl, but is not limited thereto. The conductive layer 125 may be formed of a transparent conductive material such as ITO, but is not limited thereto.

As shown in FIG. 5B, the conductive layer 125 and the organic layer 123 may be sequentially patterned using the first photosensitive pattern 127 as a mask. Since the organic layer 123 has a faster etching rate than the conductive layer 125, the organic layer 123 under the conductive layer 125 may be overetched. The pixel contact hole 35 may be formed by etching the organic layer 123. In this case, the insulating layer 121 may be the second insulating layer 14.

The organic layer 123 having the pixel contact hole 35 may become the planarization layer 16.

Both the conductive layer 125 and the organic layer 123 corresponding to the non-display area may be removed to expose the second insulating layer 14.

In particular, both the conductive layer 125 and the organic layer 123 on the alignment key 20 may be removed. That is, the organic layer 125 and the conductive layer 123 are formed in the display area, whereas the organic layer 125 and the conductive layer 123 are removed in the non-display area. 6a), although the alignment key 20 is difficult to identify by the metal layer 133, the photosensitive pattern 127 is formed due to a step difference due to the presence or absence of the organic layer 125 in the display area and the non-display area. When the photosensitive layer is patterned, the occurrence of misalignment can be prevented.

5C, the top and side surfaces of the first photosensitive pattern 127 are etched to form a second photosensitive pattern 129, and a part of the top surface of the conductive layer 125 around the pixel contact hole 35 is It can be exposed.

The exposed conductive layer 125 may be etched and removed using the second photosensitive pattern 129 as a mask. Accordingly, the common electrode 37 may be formed on the planarization layer 16.

The common electrode 37 may be formed over the entire display area including the plurality of pixels P. Since the common electrode 37 is formed in a plate shape rather than a pattern, a separate etching process is not required and only a deposition process is required, so that the process can be simplified.

4th mask process

6 shows a fourth mask process of forming a common electrode line.

6A, an insulating layer 131 and a metal layer 133 may be formed on the common electrode 37, and a photosensitive layer may be formed on the metal layer 133. The photosensitive layer may be exposed using an exposure process to form a first photosensitive pattern 135 on the metal layer.

An alignment process may be performed before the photosensitive layer is exposed. The substrate 10 may be moved based on the alignment key 20 for the alignment process. However, since an opaque metal layer 133 is formed on the alignment key 20, it may be difficult to identify the alignment key 20.

In the present invention, while the planarization layer 16 is not formed in the non-display area including the alignment key 20, the planarization layer 16 is formed in the display area. Since alignment is possible by a step difference, misalignment due to difficulty in identifying the alignment key 20 can be prevented.

The insulating layer 131 may be formed of an inorganic material such as SiOx or SiNx, but is not limited thereto. The metal film 133 may be one metal selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, and Cu, or an alloy thereof, and may be formed as a single layer or multiple layers.

As shown in FIG. 6B, the metal layer 133 and the insulating layer 131 are sequentially patterned using the first photosensitive pattern 135 as a mask to expose the drain electrode 33 of the thin film transistor. A pixel contact hole 35 may be formed in a region where the drain electrode 33 is exposed. In this case, the insulating layer 131 may be the third insulating layer 39.

The second and third insulating layers 14 and 39 corresponding to the gate lower electrode 19 and the data lower electrode 29 disposed in the non-display area may also be patterned. The gate contact hole 17 may be formed by patterning the second and third insulating layers 14 and 39 corresponding to the lower gate electrode 19. The data contact hole 27 may be formed by patterning the second and third insulating layers 14 and 39 corresponding to the data lower electrode 29.

The metal layer 133 and the insulating layer 131 corresponding to a partial region of the common electrode 37 may be patterned using the first photosensitive pattern 135 as a mask to form a jumping contact hole 49. A partial area of the common electrode 37 may be exposed by the jumping contact hole 49.

As shown in FIG. 6C, an ashing process may be performed, so that the first photosensitive pattern 135 may be patterned to form a second photosensitive pattern 137. The second photosensitive pattern 137 may be formed on the metal layer 133 corresponding to the gate line 11.

The metal layer 133 is patterned using the second photosensitive pattern 137 as a mask, so that the metal layer 133 other than the metal layer 133 on the gate line 11 may be removed as shown in FIG. 6D. have. The metal layer 133 left on the gate line 11 may become the common voltage line 47.

All of the metal layers 133 formed on the insulating layer 131 corresponding to the non-display area may also be removed.

As described above, each of the drain electrode 33, the gate lower electrode 19, and the data lower electrode 29 may include first to third conductive patterns 101, 103, and 105 shown in FIG. 3A. . The third conductive pattern 105, which is an uppermost layer among the first to third conductive patterns 101, 103, and 105, may include ITO, but is not limited thereto.

When the metal layer 133 for forming the common electrode line 47 is patterned using the second photosensitive pattern 137 as a mask, the drain electrode 33, the gate lower electrode 19, and the data lower electrode are formed by an etching solution. (29) Each of the second conductive patterns 103 may be corroded. In the present invention, for example, a third conductive pattern 105 that prevents corrosion of the second conductive pattern 103 including ITO is formed on the second conductive pattern 103 including Cu. When the metal layer 133 is patterned by the pattern 105, the second conductive pattern 103 may be prevented from being corroded by an etching solution used.

In addition, in the present invention, the jumping contact hole 49 and the common electrode line 47 are simultaneously formed by the fourth mask process, thereby simplifying the process.

5th mask process

7 shows a fifth mask process of forming a pixel electrode and a connection electrode.

As shown in FIG. 7A, a conductive film 141 is formed on the third insulating layer 39 on the non-display area and the common voltage line 47 on the display area, and a photosensitive film is formed on the conductive film 141 Can be. The photosensitive layer may be exposed using an exposure process to form a photosensitive pattern 143 on the metal layer.

The conductive layer 141 may be formed of a transparent conductive material such as ITO, but is not limited thereto.

The conductive layer 141 may be patterned using the photosensitive pattern 143 as a mask, so that the pixel electrode 45 and the connection electrode 50 may be formed.

A portion of the pixel electrode 45 may contact the drain electrode 33 of the thin film transistor through the pixel contact hole 35.

The pixel electrode 45 may include a plurality of pixel electrode bars 41 to 44. Each of the pixel electrode bars 41 to 44 may be spaced apart from each other.

A horizontal electric field and a vertical electric field may be generated between the plurality of pixel electrode bars 41 to 44 and the common electrode 37. The liquid crystal molecules are displaced to a greater extent and more precisely controlled by the horizontal electric field and the vertical electric field, so that image quality can be improved.

The connection electrode 50 may directly contact the common electrode line 47 and may contact the common electrode 37 through the jumping contact hole 49.

The connection electrode 50 may contact both the top and side surfaces of the common electrode line 47.

The connection electrode 50 may be disposed adjacent to the pixel electrode 45.

In the present invention, since the pixel electrode 45 and the connection electrode 50 are simultaneously formed by the fifth mask process, the process can be simplified.

The above detailed description should not be construed as restrictive in all respects and should be considered as illustrative. The scope of the present invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the present invention are included in the scope of the present invention.

10: substrate 11: gate line
12: first insulating layer 13: gate electrode
14: second insulating layer 15: gate pad portion
16: planarization layer 17: gate contact hole
18: semiconductor layer 19: lower gate electrode
20: alignment key 21: gate upper electrode
23: data line 24: source electrode
25: data pad part 27: data contact hole
29: data lower electrode 31: data upper electrode
33: drain electrode 35: pixel contact hole
37: common electrode 39: third insulating layer
41 to 44: pixel electrode bar 45: pixel electrode
47: common electrode line 49: jumping contact hole
50: connecting electrode

Claims (10)

Board;
A gate line on the substrate;
A data line on the gate line crossing the gate line;
A thin film transistor connected to the gate line and the data line;
A planarization layer disposed on the thin film transistor and including a first contact hole;
A common electrode on the planarization layer;
An insulating layer disposed on the common electrode and including a second contact hole;
A pixel electrode and a common electrode line in the same layer on the insulating layer; And
One side is connected to the common electrode line, the other side includes a connection electrode connected to the common electrode,
The connection electrode directly contacts an upper surface and a side surface of the common electrode line, and is connected to the common electrode through the second contact hole. The method of claim 1,
The pixel electrode includes a plurality of pixel electrode bars, and is connected to the thin film transistor through the first contact hole. The method of claim 1,
The common electrode line is disposed on the gate line,
The second contact hole is an array substrate disposed between the pixel electrode and the common electrode line. The method of claim 1,
The array substrate includes a display area and a non-display area,
A gate pad portion extending from the gate line in the non-display area;
A data pad part extending from the data line; And
An array substrate on which an alignment key on the same layer as the gate line is disposed. Forming a gate line, a gate electrode, and an alignment key using a first mask process;
Forming a semiconductor layer, a data line, a source electrode, and a drain electrode on the gate line, the gate electrode, and the alignment key by using a second mask process;
Forming a planarization layer having a first contact hole on the data line, a source electrode, and a drain electrode by using a third mask process and a common electrode on the planarization layer;
Forming an insulating layer having a second contact hole on the common electrode and a common electrode line on the insulating layer by using a fourth mask process; And
Including the step of forming a pixel electrode and a connection electrode using a fifth mask process,
The pixel electrode is connected to the drain electrode through the first contact hole,
The method of manufacturing an array substrate in which the planarization layer is not formed on the alignment key. The method of claim 5,
The method of manufacturing an array substrate in which the connection electrode is connected to the common electrode through the second contact hole on the common electrode line. The method of claim 5,
The pixel electrode is a method of manufacturing an array substrate including a plurality of pixel electrode bars. The method of claim 5,
Forming a lower gate electrode together with the gate line;
Forming a data lower electrode together with the data line; And
Further comprising forming a gate upper electrode and a data upper electrode together with the pixel electrode,
The gate lower electrode and the gate upper electrode constitute a gate pad part,
The method of manufacturing an array substrate in which the data lower electrode and the data upper electrode constitute a data pad part. The method of claim 8,
Each of the drain electrode, the gate lower electrode, and the data lower electrode includes a plurality of conductive patterns,
A method of manufacturing an array substrate, wherein a first layer, which is an uppermost layer of the plurality of conductive patterns, includes ITO, and a second layer disposed under the first layer includes Cu. The method of claim 4,
An array substrate in which the planarization layer is not disposed on the alignment key.

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