KR102217167B1 - Display device - Google Patents

Abstract

The present invention relates to a display device having a charge sharing function, and a data driver occupies a first data line group only when polarities of data voltages supplied to data lines belonging to the first data line group are reversed. The second data line group is charged and shared only when the polarities of the data voltages supplied to the data lines belonging to the second data line group are reversed. The charge share timing of the first data line group is controlled differently from the charge share timing of the second data line group. This charge share control method makes it possible to significantly reduce power consumption without deteriorating image quality in a display device.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device having a charge sharing function.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices such as are being developed. The liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is formed for each pixel.

Liquid crystal display devices include a liquid crystal display panel, a backlight unit that irradiates light to the liquid crystal display panel, a source drive integrated circuit (Integrated Circuit, hereinafter referred to as "IC") for supplying data voltage to the data lines of the liquid crystal display panel, and liquid crystal. A gate drive IC for supplying a gate pulse (or scan pulse) to the gate lines (or scan lines) of the display panel, a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, etc. Equipped.

In addition to the R (Red) sub-pixel, G (Green) sub-pixel, and B (Blue) sub-pixel to each of the pixels, a liquid crystal display device in which a W (White) sub-pixel is added is being developed. Hereinafter, a display device in which pixels are divided into RGBW sub-pixels is referred to as a "RGBW type display device". The W sub-pixel may lower the brightness of the backlight unit by increasing the brightness of each of the pixels, thereby lowering the power consumption of the liquid crystal display.

Various methods for reducing the source drive IC have been attempted to reduce the cost of a large-screen, high-resolution display device, but image quality defects such as differences in luminance between lines appear due to uneven charging of pixels and unbalanced polarity distribution. Recently, the power consumption of the display device has improved, but there is a need to further lower the power consumption.

The present invention provides a display device capable of lowering power consumption without deteriorating image quality.

The display device of the present invention includes a display panel, a data driver, and a gate driver.

The display panel includes data lines, a plurality of gate lines orthogonal to the data lines, and a pixel array for reproducing an input image. The data driver supplies a data voltage to the data lines, and the gate driver supplies a gate pulse synchronized with the data voltage to the gate lines.

The data driver will charge share the first data line group only when the polarities of the data voltages supplied to the data lines belonging to the first data line group are reversed, and to the data lines belonging to the second data line group. The second data line group is occupied only when the polarity of the supplied data voltage is reversed. The charge share timing of the first data line group is controlled differently from the charge share timing of the second data line group.

In the present invention, in a display device including a first data line group and a second data line group having different charge share timings, the data voltage supplied to the data lines belonging to the first data line group is reversed. The data line group is charged and shared only when the polarities of the data voltages supplied to the data lines belonging to the second data line group are reversed. As a result, the present invention can significantly lower power consumption without deteriorating image quality.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
2 to 4 are diagrams showing a pixel array charging sequence according to an embodiment of the present invention.
5 is a waveform diagram showing the polarities of data voltages supplied to pixels through four adjacent data lines.
6 is a waveform diagram showing an output waveform of a source drive IC, an output waveform of a gate driver, and an amount of charge of a pixel for implementing the pixel array charging sequence as shown in FIGS. 2 to 4.
FIG. 7 is a diagram illustrating a batch gamma compensation curve of color data for compensating for a difference in charging of pixels as in FIG. 5.
8 is a waveform diagram showing a high-impedance switching method and a charge share method.
9 is a circuit diagram showing a source drive IC according to the first embodiment of the present invention.
10 is a waveform diagram showing a polarity control signal for controlling the charge share method of the present invention.
11 is a waveform diagram showing polarity, output timing, and charge share timing of data voltages applied to first and third data lines.
12 is a waveform diagram showing polarity, output timing, and charge share timing of data voltages applied to second and fourth data lines.
13 is a waveform diagram showing charge share timing according to an embodiment of the present invention.
14 is a diagram illustrating a comparison of a voltage fluctuation amount, a frequency of a data voltage, and a dynamic power consumption in the charge share method, the conventional high impedance method, and the charge count method according to the present invention.
FIG. 15 is a diagram comparing a conventional high impedance method and a charge share method, and a charge share method of the present invention in the white color of the experimental image pattern in FIG. 14.
FIG. 16 is a view comparing the conventional high impedance method and the charge share method, and the charge share method of the present invention in the red color of the experimental image pattern in FIG. 14.
FIG. 17 is a view comparing the conventional high impedance method and the charge share method, and the charge share method of the present invention in the green color of the experimental image pattern in FIG. 14.
FIG. 18 is a view comparing the conventional high impedance method and the charge share method, and the charge share method of the present invention in the blue color of the experimental image pattern in FIG. 14.
FIG. 19 is a diagram comparing the conventional high impedance method and the charge share method, and the charge share method of the present invention in the cyan color of the experimental image pattern in FIG. 14.
FIG. 20 is a view comparing the conventional high impedance method and the charge share method, and the charge share method of the present invention in the yellow color of the experimental image pattern in FIG. 14.
FIG. 21 is a diagram comparing the conventional high impedance method and the charge share method, and the charge share method of the present invention in the Magenta color of the experimental image pattern in FIG. 14.
22 is a circuit diagram showing a source drive IC according to a second embodiment of the present invention.
23 is a circuit diagram showing a source drive IC according to a third embodiment of the present invention.

The display device of the present invention may be implemented as a flat panel display device capable of implementing colors such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), and a plasma display panel (PDP). Hereinafter, embodiments of the present invention will be described centering on a liquid crystal display device, but it should be noted that the present invention is not limited to the liquid crystal display device. For example, the arrangement of RGBW sub-pixels of the present invention is applicable to an organic light emitting diode display.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

Referring to FIG. 1, the display device of the present invention includes a display panel 100 on which a pixel array is formed, and a display panel driving circuit for writing data of an input image to the display panel 100. A backlight unit for uniformly irradiating light to the display panel 100 may be disposed under the display panel 100.

In order to reduce the number of source drive ICs, this display device is implemented as double rate driving (DRD) type pixels in which two horizontally adjacent sub-pixels share one data line (x-axis or low-line direction). . The DRD type pixel array can reduce the number of source drive ICs by half. In the DRD type display device, the operating frequency of the source drive IC is doubled.

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by an intersection structure of the data lines S1 to Sm and the gate lines G1 to Gn.

The lower substrate of the display panel 100 includes data lines S1 to Sm, gate lines G1 to Gn, TFTs, a pixel electrode 1 connected to the TFT, and a storage connected to the pixel electrode 1 Includes a capacitor (Storage Capacitor, Cst). Each of the pixels adjusts the transmission amount of light by using liquid crystal molecules driven by a voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. Display an image of video data.

A color filter array including a black matrix and a color filter is formed on the upper substrate of the display panel 100. The common electrode 2 is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as a mode, it may be formed on the lower substrate together with the pixel electrode. A polarizing plate is attached to each of the upper and lower substrates of the display panel 100 and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The display device of the present invention can be implemented with various liquid crystal display devices such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display. Transmissive liquid crystal display devices and transflective liquid crystal display devices require a backlight unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes data of an input image to pixels. Data written to the pixels includes R data, G data, B data and W data. The display panel driving circuit includes a data driver 102, a gate driver 104, a timing controller 20, and a gamma correction unit 22.

The data driver 102 includes a plurality of source drive ICs. The output channels of the source drive ICs are connected to the data lines S1 to Sm of the pixel array. The source drive ICs receive digital video data of an input image from the timing controller 20. The digital video data transmitted to the source drive ICs includes R data, G data, B data, and W data. The source drive ICs convert RGBW digital video data of an input image into a positive/negative gamma compensation voltage under the control of the timing controller 20 and output a positive/negative data voltage. The output voltage of the data driver 102 is supplied to the data lines D1 to Dm.

Each of the pixels includes an R sub-pixel, a G sub-pixel, a B sub-pixel, and a W sub-pixel. Two horizontally adjacent subpixels share one data line as shown in FIGS. 3 to 19 to charge the time-divided data voltages through the data line. Due to the shared structure of the data lines, the number of source drive ICs required for driving the pixel array can be reduced by reducing the number of data lines by 1/2 compared to the general pixel array structure at the same resolution.

Each of the source drive ICs may invert the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 20 by an inversion period of 2 horizontal periods or more and N/2 (N is the vertical resolution of the display panel) horizontal period or less. . 4 to 13 illustrate an example in which the data voltage is inverted in 2 horizontal periods (2H) by the source drive IC, but is not limited thereto. In the case of a DRD type display device, four data voltages successively outputted from the source drive IC for two horizontal periods are sequentially charged to four subpixels of two lines sharing the same data line.

In response to the polarity control signal POL, the source drive ICs maintain the same polarity of the 4 data voltages to be charged to the 4 sub-pixels during 2 horizontal periods (Fig. 5, 2H), and the polarity of the data voltages in 2 horizontal periods. Reverse. Accordingly, the source drive ICs continuously output 8 data voltages during 4 horizontal periods (FIGS. 5 and 4H) as shown in FIGS. 5 and 6, but invert the polarity of the data voltage once during 2 horizontal periods. In the present invention, since the polarity inversion period of the data voltage is long, the number of transitions of the data voltage is small. As a result, it is possible to reduce power consumption and heat generation of the source drive ICs of the present invention. As another embodiment, the source drive ICs may further reduce the number of transitions of the data voltage by inverting the polarity of the data voltage to be supplied to the pixels in a period of 4 horizontal periods under the control of the timing controller 20.

The display device of the present invention writes W data to the W sub-pixels during two horizontal periods in which data voltages having the same polarity are successively outputted, and then writes data of different colors to the sub-pixels of different colors. After the W data voltage is first charged to the W subpixel, the data voltage may be charged to the RGB subpixels in the order of R data, B data, and G data, or in the order of B data, R data and G data. When the data voltages of the same polarity are continuously charged to the subpixels through the same data line, the charging amount of the data voltage of the earliest data voltage is relatively small compared to the data voltages thereafter. For this reason, according to the present invention, W data, which does not cause color distortion, is first charged to the W sub-pixel even if the amount of charging of the pixel is small among the RGBW data voltages of the same polarity.

In the example of FIG. 3, the W subpixel W11 is disposed on a row line L1 by Kth (K is a positive integer of 0) + 1 of the display panel 100, and the R subpixel R31 ) Is disposed on the K+3th row L3 of the display panel 100. The B sub-pixel B21 is disposed on the K+2th row line L2 of the display panel 100. The G subpixel B41 is disposed on the K+3th row line L4 of the display panel 100.

The W sub-pixel W11 is supplied through the J-th (J is a positive integer) data line S1 in response to the first gate pulse supplied through the I-th (I is a positive integer) gate line G3. And a first TFT T11 supplying the W data voltage to the first pixel electrode P11 in the W subpixel W11. The gate of the first TFT T11 is a gate connected to the I-th gate line G3 to which the first gate pulse is supplied, a drain connected to the J-th data line S1, and a source connected to the pixel electrode P11. Includes.

The R sub-pixel R31 applies the R data voltage supplied through the J-th data line S1 to the second pixel electrode in the R sub-pixel in response to a second gate pulse supplied through the I+2 gate line G5. It includes a second TFT (T12) to be supplied to (P22). The gate of the second TFT T12 is connected to the gate connected to the I+2 gate line G5 to which the second gate pulse is supplied, the drain connected to the J-th data line S1, and the pixel electrode P12. Includes the sourced.

The B sub-pixel applies the B data voltage supplied through the J-th data line S1 to the third pixel electrode P13 in the B sub-pixel in response to the third gate pulse supplied through the I+3 gate line G6. And a third TFT (T13) supplied to the device. The gate of the third TFT T13 is connected to the gate connected to the I+3 gate line G6 to which the third gate pulse is supplied, the drain connected to the J-th data line S1, and the pixel electrode P13. Includes the sourced.

The G sub-pixel applies the G data voltage supplied through the J-th data line S1 to the fourth pixel electrode P14 in the G sub-pixel in response to the fourth gate pulse supplied through the I+4 gate line G7. And a fourth TFT (T14) supplied to the device. The gate of the fourth TFT (T14) is connected to the gate connected to the I+4th gate line (G7) to which the fourth gate pulse is supplied, the drain connected to the Jth data line (S1), and the pixel electrode (P14). Includes the sourced.

The source drive IC inverts the polarity of the data voltage in 2 horizontal periods, but the pixel array includes pixels whose data voltage is inverted in units of 1 dot along the horizontal and vertical directions (x, y), and data in units of 2 dots. It includes pixels whose voltage polarity is reversed. One dot means one sub-pixel. Accordingly, in the display device of the present invention, by controlling the polarity of the pixel array in the form of dot inversion, it is possible to prevent a difference in brightness and flicker that may be seen when the same polarity is concentrated in a line or block form. The reason why the output data polarity inversion period of the source drive IC and the polarity inversion period of the pixel array are different is that the gate pulses are non-sequentially applied to the gate lines of the pixel array due to the pixel array structure as shown in FIG. 3-4.

The source drive IC performs charge share on the first data line group only when the polarities of the data voltages supplied to the data lines belonging to the first data line group are reversed, and data belonging to the second data line group The second data line group is charged only when the polarities of the data voltages supplied to the lines are reversed. The charge share timing of the first data line group and the charge share timing of the second data line group are set differently as shown in FIGS. 5 and 10. In FIG. 10, "POLCS" refers to a charge share timing performed only when the polarity of the data voltage is reversed.

When the data lines are arranged in the order of a first data line (S1), a second data line (S2), a third data line (S3), and a fourth data line (S4) from the left, the first data line group is It includes first and third data lines S1 and S3. The second data line group includes second and fourth data lines S2 and S4.

The charge share timing of the first data line group is different from the charge share timing of the second data line group. In the example of FIGS. 5 and 10, the first data line group includes first and third data lines S1 and S3 whose polarities of the data voltages are simultaneously inverted. The second data line group includes second and fourth data lines S2 and S4 whose polarities of the data voltages are simultaneously inverted. When the first and third data lines S1 and S3 to which data voltages of inverted polarities are applied are short circuited, the first data line group is charged and shared so that the first and third data lines ( The voltages of S1 and S3) are averaged. When the second and fourth data lines S2 and S4 to which data voltages of inverted polarities are applied are short-circuited, the second data line group is charged and shared to the second and fourth data lines S2 and S4 The voltage of is averaged.

The gate driver 104 sequentially supplies gate pulses to the gate lines G1 to Gn under the control of the timing controller 20. The gate pulse output from the gate driver 104 is synchronized with the positive/negative video data voltage to be charged to the pixels. The gate driver 104 may be directly formed on the lower substrate of the display panel 100 together with the pixel array in the same manufacturing process to reduce IC cost.

The output channels of the gate driver 104 and the gate lines G1 to Gn of the pixel array are connected 1:1 through link lines LNK as shown in FIG. 3. In order to supply the gate pulses to the pixel array in a non-sequential manner without changing the output channel of the gate driver 104, at least some of the link lines LNK cross as shown in FIGS. 3 and 4. Accordingly, the gate driver 104 sequentially outputs the gate pulses from the first output channel, but the gate pulses are non-sequentially applied to the gate lines 14 of the pixel array. The display device of the present invention connects the gate driver 104 to the gate lines G1 to Gn of the pixel array through intersecting link lines LNK, so that the gate pulse is transferred to the gate line without changing the gate driver 14. It can be supplied non-sequentially to the fields (G1 to Gn).

A parasitic capacitance exists in a portion where the link wirings LNK intersect, so that the gate lines may be electrically coupled. This parasitic capacitance can be minimized by an organic protective film covering the TFTs and wirings of the pixel array. This is because the dielectric constant of the organic passivation layer is low and the organic passivation layer may be formed thick.

The timing controller 20 converts RGB data of the input image received from the host system 24 into RGBW data and transmits the converted data to the data driver 102. An interface for data transmission between the timing controller 20 and the source drive ICs of the data driver 102 may use a mini LVDS (low-voltage differential signaling) interface or an EPI (Embedded Panel Interface) interface. EPI interface is a Korean patent application filed by the applicant of the present application 10-2008-0127458 (2008-12-15), US application 12/543,996 (2009-08-19), Korean patent application 10-2008-0127456 (2008-12) -15), US application 12/461,652 (2009-08-19), Korean patent application 10-2008-0132466 (2008-12-23), US application 12/537,341 (2009-08-07), etc. Can be applied as

The timing controller 20 receives timing signals synchronized with the input image data from the host system 24. Timing signals include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), a dot clock (DCLK), and the like. The timing controller 20 controls operation timings of the data driver 102 and the gate driver 104 based on timing signals Vsync, Hsync, DE, and DCLK received together with pixel data of an input image. The timing controller 20 includes a polarity control signal (POL) for controlling the polarity of the pixel array, and a source output enable signal (Source) for controlling the output timing and charge share timing of the data driver 102. Output Enable, SOE) occurs. The timing controller 2 may transmit the polarity control signal POL and the source output enable signal SOE to each of the source drive ICs of the data driver 102. The Mini LVDS interface transmits the polarity control signal (POL) and the source output enable signal (SOE) through separate control wiring. The EPI interface encodes the polarity control signal (POL) and the source output enable signal (SOE) in the control data packet transmitted between the clock training pattern and RGBW data packets for CDR (Clok and Data Recovery). It transmits to each of the source drive ICs.

The polarity inversion timing of the data voltage varies according to the data lines S1 to Sm as shown in FIGS. 5 and 10. The polarities of the data voltages applied to the first and third data lines S1 and S3 are opposite to each other, and the data voltages have the same inversion timing. The polarity inversion timing of the data voltage applied to the first and third data lines S1 and S3 is different from that of the data voltage applied to the second and fourth data lines S2 and S4. The polarities of the data voltages applied to the second and fourth data lines S2 and S4 are opposite to each other, and the data voltages have the same inversion timing. The polarity control signal POL is a first polarity control signal POL (S1) and a second data line S2 for controlling the polarity of the data voltage applied to the first data line S1 as shown in FIGS. 5 and 10. A second polarity control signal (POL(S2)) that controls the polarity of the data voltage applied to the third data line (S3), and a third polarity control signal (POL(S3)) that controls the polarity of the data voltage applied to the third data line (S3). , And a fourth polarity control signal POL(S4) that controls the polarity of the data voltage applied to the fourth data line S4. The second polarity control signal POL(S2) has a phase difference compared to the first polarity control signal POL(S1) by a predetermined time, for example, one horizontal period (1H), and the third polarity control signal POL(S3) ) Is an inversion signal of the first polarity control signal POL(S1). The fourth polarity control signal POL(S4) is an inversion signal of the second polarity control signal POL(S2). The source drive IC selects the positive data voltage in response to the first logic value of the polarity control signal (POL(S1) to POL(S4)), and selects the polarity control signal (POL(S1) to POL(S4)). 2 Select the negative data voltage in response to the logic value. The first logic value of the polarity control signals POL(S1) to POL(S4) may be a high logic level voltage, and the second logic value may be a low logic level voltage. .

The source output enable signal SOE is a first source output enable signal (FIG. 11, SOE1) that controls the output timing and charge share timing of the data voltages supplied to the first and third data lines S1 and S3. And, a second source output enable signal (SOE2 in FIG. 12) that controls an output timing and a charge share timing of a data voltage supplied to the second and fourth data lines S2 and S4. The source drive IC performs charge share in response to the first logical value of the source output enable signals SOE1 and SOE2, and outputs the data voltage in response to the second logical value of the source output enable signals SOE1 and SOE2. can do. The first logic value of the source output enable signals SOE1 and SOE2 may be a high logic level voltage, and the second logic value may be a low logic level voltage.

The timing controller 20 may convert RGB data of an input image into RGBW data using a white gain calculation algorithm. Any known white gain calculation algorithm is possible. For example, Korean Patent Application No. 10-2005-0039728 (2005. 05. 12), Korean Patent Application No. 10-2005-0052906 (2005. 06. 20), Korean Patent Application No. 10-2005 previously filed by the applicant of the present application The white gain calculation algorithms proposed in -0066429 (2007. 07. 21) and Korean Patent Application No. 10-2006-0011292 (2006. 02. 06) can be applied.

The gamma correction unit 22 uses a look-up table (LUT) storing a gamma compensation curve as shown in FIG. 7 to compensate for differences in charging characteristics of pixels for each color. Modulate. The lookup table receives an input gray level of the input image data, selects an output gray level corresponding to the input gray level, and modulates the input gray level to adjust the luminance of each gray level of the data. In FIG. 7, the x-axis is output gradation and the y-axis is luminance. The gamma correction unit 22 receives RGB data from the timing controller 20 to increase a data value of a color having a low filling amount, while lowering a data value of a color having a high filling amount. The gamma correction unit 22 may be built into the timing controller 20 or the host system 24.

The host system 24 may be any one of a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

2 to 4 are diagrams showing a pixel array charging sequence according to an embodiment of the present invention. 5 is a waveform diagram showing polarities of data voltages supplied to pixels through the J to J+3 data lines S1 to S4. 6 is a waveform diagram showing an output waveform of a source drive IC, an output waveform of a gate driver, and a charge amount of a pixel.

2 to 6, the source drive IC outputs four data voltages having the same polarity in the order of a W data voltage, an R data voltage, a B data voltage, and a G data voltage. Accordingly, the W data voltage is first charged to the W sub-pixel, and then the data voltage is charged to the RGB sub-pixels in the order of R data, B data, and G data.

In Fig. 6, "SIC" denotes a source drive IC. “S1 (Odd Data)” represents RGBW data output through the first data line S1. "S2 (Even Data)" denotes RGBW data output through the second data line S2. "POL" is a polarity control signal that is generated by the timing controller 20 and defines the polarity of the data voltage according to its logic value.

The source drive IC outputs data voltages having the same polarity for two horizontal periods (2H) in order of W data, R data, B data and G data. The gate driver 104 sequentially outputs a gate pulse synchronous to the W data voltage, a gate pulse synchronous to the R data voltage, a gate pulse synchronous to the B data voltage, and the gate pulse synchronous to the G data voltage. Due to the structure of the intersecting link lines LNK, the W sub-pixel W11 of the first row line L1, the R sub-pixel R31 of the third row line L3, as shown in FIGS. 2 and 3, The RGBW data voltages having the same polarity are charged to the RGBW sub-pixels in the order of the B sub-pixel B21 of the second row line L2 and the G sub-pixel G41 of the fourth row line L2.

When the RGBW data voltage is the same, the W sub-pixel is a weakly charged and charged sub-pixel, and the R sub-pixel is a medium charged sub-pixel with a higher data voltage than the W sub-pixel. The B sub-pixel and the G sub-pixel are strongly charged sub-pixels with the same charge amount and more charge than the R sub-pixel. There is little difference between the charging amount of the R sub-pixel and the charging amount of the B/G sub-pixel. Looking at the polarity distribution in the sub-pixels of the same color, the present invention does not shift the common voltage Vcom by balancing the positive polarity (+) and the negative polarity (-) in the horizontal and vertical directions as shown in FIG. 4. Therefore, it is possible to implement image quality without horizontal crosstalk and no luminance difference between lines.

If W sub-pixels having a small amount of charge are located close together, a difference in luminance may be recognized in that part, but the present invention prevents the problem of luminance deterioration due to W sub-pixels by increasing the distance between W sub-pixels by 2 dots or more. I can. Accordingly, the display device of the present invention can reduce power consumption by adding W sub-pixels for each pixel, and achieves image quality without color distortion and luminance difference between lines by making charging characteristics and polarity distribution uniform in RGB sub-pixels. I can.

In FIG. 6, as can be seen from the charge amount of the W sub-pixels, the data voltage whose polarity is reversed compared to the previous data voltage decreases the charge amount of the sub-pixel. Accordingly, the polarity reversal timing of the data voltages supplied to the pixels through the odd-numbered data lines S1 and S3 and the polarity reversal of the data voltages supplied to the pixels through the even-numbered data lines S2 and S4 If the viewpoints are the same, the filling amount of all sub-pixels in the same row line is lowered, so that a difference in luminance between the row lines is seen. The source drive IC is the polarity of the data voltages supplied to the odd-numbered data lines S1 and S3 under the control of the timing controller 20 and the polarity of the data voltages supplied to the even-numbered data lines S2 and S4. Different timing of reversal. Accordingly, according to the present invention, a difference in luminance between the column lines C1 to C8 can be prevented by differently changing the polarity inversion timing between adjacent column lines in the display device. The polarity reversal timing of the data voltages supplied to the odd-numbered data lines S1 and S3 differs by 1 horizontal period (1H) compared to the polarity reversal of the data voltages supplied to the even-numbered data lines S2 and S4. There may be.

If the amount of charge is different between sub-pixels of the same color, the gamma characteristic of the color cannot be collectively compensated. On the other hand, in the present invention, since the filling amount of sub-pixels of the same color is the same, gamma characteristics can be collectively compensated for each color. As shown in FIG. 7, the gamma curve of the W data to be written to the W sub-pixels is set higher than that of data of other colors, so that a low charging amount of the W sub-pixels can be collectively compensated. The gamma curve of the R data to be written to the R subpixels is lower than the gamma curve of the W data and higher than the gamma curves of the B and G data. Since the filling amount of the B and G sub-pixels is the same, the gamma curves of the B and G data are the same.

The order of charging the pixel array as shown in FIGS. 2 to 5 is different from the order of data input of an input image. For this reason, the timing controller 20 needs to change the data of the input image line by line in accordance with the pixel array charging order in the process of rearranging the data of the input image. In FIG. 6, "S" synchronized with the second gate pulse is not data of an input image, but dummy data generated in the timing controller 20. The dummy data S is data that is not written to the pixel array. The dummy data S is inserted between the data of the input image and transmitted to the source drive IC in the data rearrangement process of the timing controller 20 according to the data charging order of the pixel array, but the pixels to which the dummy data is written in the pixel array none.

Source drive ICs include digital-to-analog conversion (DAC), which converts digital video data to positive/negative gamma compensation voltage and outputs positive/negative data voltage. And buffers that supply the output of the DAC to the data lines S1 to Sm. The DAC is a PDAC (Positive DAC) that converts digital video data to a positive gamma compensation voltage and outputs a positive data voltage, and a NDAC (Negative DAC) that converts digital video data to a negative gamma compensation voltage and outputs a negative data voltage. DAC).

The buffer is connected between the output channels of the DAC. Whenever the data voltage changes, a current is generated in the buffer, and when the polarity of the data voltage is changed, the amount of fluctuation of the data voltage increases, so that more current is generated in the buffer. Accordingly, the power consumption of the source drive IC increases as the frequency of the data voltage increases and the amount of fluctuation of the data voltage increases.

In order to reduce the power consumption of the source drive IC, a high impedance (Hi-Z) switching method as shown in the upper drawing of FIG. 8 may be applied. In the high impedance switching method, when the polarity of the data voltage Vdata is changed, the output channels of the source drive IC are controlled in a high impedance (Hi-Z) state. This method is a method of blocking the current path between the output channels of the source dry IC and the data lines S1 to Sm. This method can reduce the frequency and voltage fluctuation of the data voltage Vdata when the data voltages of the same polarity are consecutive, but the voltage fluctuation increases when the polarity is changed.

As another method for reducing power consumption of the source drive IC, a charge share method as shown in the figure below of FIG. 8 may be applied. The charge share method averages the voltages of the data lines S1 to Sm by short circuiting the adjacent data lines S1 to Sm immediately before the data voltage changes. The data lines include data lines to which a positive data voltage (+Vdata) is supplied and data lines to which a negative data voltage (-Vdata) is supplied. Accordingly, when the data lines are shorted by performing a charge share, the voltage of the data lines becomes an average voltage between the positive data voltage and the negative data voltage. This method can reduce the amount of fluctuation of the data voltage Vdata when the polarity of the same data voltage Vdata is changed, but a current is generated in the buffer every time the data voltage changes.

In FIG. 8, if the voltage fluctuation amount is 2 and the frequency of the data voltage is 1/4 in the high impedance switching method, the voltage fluctuation amount is 1 and the frequency of the data voltage is 1 in the charge share method.

In the present invention, in order to further reduce power consumption of the source drive IC, charge share (POLCS) is performed only when the polarity of the data voltage is reversed as shown in FIG. 10. To this end, as shown in FIGS. 9, 22, and 23, the output channels (OUT1 & OUT3, OUT2 & OUT 4) whose polarity of the data voltage is simultaneously inverted in the source drive IC can be connected and the output channels can be short-circuited at the same time. Circuit is required.

9 is a circuit diagram showing a source drive IC according to the first embodiment of the present invention. 10 is a waveform diagram showing a charge share method of the present invention. 9 and 10 show buffers and switches between the DAC and the output channels OUT1 to OUT4 in the source drive IC. Source drive IC shift registers, latches, and DACs are omitted.

9 and 10, the source drive IC includes a plurality of buffers P1, P2, N3, and N4, a plurality of switches, and a plurality of output channels OUT1 to OUT4.

The buffers P1, P2, N3, and N4 are P buffers P1 and P2 that supply the positive data voltage (+Vdata) input from the PDAC to the output channels, and the negative data voltage input from the NDAC ( -Vdata) to the output channels and N buffers N3 and N4. The first P buffer P1 includes first data Data1 to be supplied to the first data line S1 through the first output channel OUT1, and the third data line S3 through the third output channel OUT3. The positive data voltage (+Vdata) of the third data Data3 to be supplied to) is output. The second P buffer P2 includes second data Data2 to be supplied to the second data line S2 through the second output channel OUT2 and the fourth data line S4 through the fourth output channel OUT4. The positive data voltage (+Vdata) of the fourth data Data4 to be supplied to) is output. The first N buffer N3 includes first data Data1 to be supplied to the first data line S3 through the first output channel OUT1 and the third data line S3 through the third output channel OUT3. The negative data voltage (-Vdata) of the third data Data3 to be supplied to) is output. The second N buffer N4 includes second data Data2 to be supplied to the second data line S2 through the second output channel OUT2 and the fourth data line S4 through the fourth output channel OUT4. A negative data voltage (-Vdata) of the fourth data Data4 to be supplied to) is output.

The switches include a multiplexer (MUX) for data distribution, switches for supplying data voltage (SW1 to SW4), and switches for charge share (SW5, SW6).

The multiplexer includes switches (SA1, SB1, SA3, SB3, SC2, SD2, SC4, SD4, hereinafter referred to as "MUX switch") for distributing the data voltage output through one buffer to a plurality of output channels. . The multiplexer selects the polarity of the data voltages (+Vdata, -Vdata) in response to the polarity control signals POL(S1), POL(S2), POL(S3), and POL(S4) shown in FIG. 10.

The first MUX switch SA1 connected to the first P buffer P1 outputs the first output terminal of the first P buffer P1 in response to the first logic value of the first polarity control signal POL(S1). Connect to channel OUT1. The second MUX switch SB1 connected to the first P buffer P1 outputs the output terminal of the first P buffer P1 to a third in response to the first logic value of the first polarity control signal POL(S1). Connect to channel OUT3. The first and second MUX switches SA1 and SB1 are turned off when the first polarity control signal POL(S1) is a second logic value.

The third MUX switch SC2 connected to the second P buffer P2 outputs the second output terminal of the second P buffer P2 in response to the first logic value of the second polarity control signal POL(S2). Connect to channel OUT2. The fourth MUX switch SD2 connected to the second P buffer P2 outputs the fourth output terminal of the second P buffer P2 in response to the first logic value of the second polarity control signal POL(S2). Connect to channel OUT4. The third and fourth MUX switches SC2 and SD2 are turned off when the second polarity control signal POL(S2) is a second logic value.

The fifth MUX switch SB3 connected to the first N buffer N3 outputs the first output terminal of the first N buffer N3 in response to the second logic value of the third polarity control signal POL(S3). Connect to channel OUT1. The sixth MUX switch SA3 connected to the first N buffer N3 outputs the output terminal of the first N buffer N3 to a third in response to the second logic value of the third polarity control signal POL(S3). Connect to channel OUT3. The fifth and sixth MUX switches SB3 and SA3 are turned off when the third polarity control signal POL(S3) is a first logic value.

The seventh MUX switch SD4 connected to the second N buffer N4 outputs the fourth output terminal of the second N buffer N2 in response to the second logic value of the fourth polarity control signal POL(S4). Connect to channel OUT4. The eighth MUX switch SC4 connected to the second N buffer N4 outputs the output terminal of the second N buffer N2 to the fourth in response to the second logic value of the fourth polarity control signal POL(S4). Connect to channel OUT4. The seventh and eighth MUX switches SD4 and SC4 are turned off when the fourth polarity control signal POL(S4) is a first logic value.

The data voltage supply switches SW1 to SW4 are disposed between the multiplexer and the output channel to transmit the positive data voltage (+Vdata) and the negative data voltage (-Vdata) from the multiplexer to the output channels OUT1 to OUT4. Supply. Each of the data voltage supply switches SW1 to SW4 includes an input terminal connected to two MUX switches and an output terminal connected to one output channel. The first and third data voltage supply switches SW1 and SW3 apply positive/negative data voltages to the first and negative data voltages in response to the second logic value of the first source output enable signal SOE1 as shown in FIG. 11. It is supplied to the third output channels OUT1 and OUT3. The second and fourth data voltage supply switches SW2 and SW4 apply the positive/negative data voltage to the second and negative data voltages in response to the second logic value of the second source output enable signal SOE2 as shown in FIG. 12. It is supplied to the fourth output channels OUT2 and OUT4.

The charge share switches (SW5, SW6, hereinafter referred to as "CS switch") connect output channels in which the polarity of the data voltage changes simultaneously when the polarity of the data voltage changes.

The first CS switch SW5 is connected to the first and third output channels OUT1 and OUT3 connected to the data lines of the first data line group. The first CS switch SW5 is turned on at the first charge share timing to occupy the data lines S1 and S3 of the first data line group. The first charge share timing is controlled by the first source output enable signal SOE1 as shown in FIG. 11. The first CS switch SW5 connects the first and third output channels OUT1 and OUT3 in response to the first logic value of the first source output enable signal SOE1 to share the charge of the first data line group. Conduct.

The second CS switch SW6 is connected to the first and third output channels OUT1 and OUT3 connected to the data lines S2 and S4 of the second data line group. The second CS switch SW6 is turned on at the first charge share timing to occupy the data lines S2 and S4 of the second data line group. The second charge share timing is controlled by the second source output enable signal SOE2 as shown in FIG. 12. The second CS switch SW6 connects the second and fourth output channels OUT2 and OUT4 in response to the first logic value of the second source output enable signal SOE2 to share the charge of the second data line group. Conduct.

The buffers and output channels shown in FIGS. 9 and 10 are divided into four cases as shown in Table 1 below, and the operation states can be classified.

Output channel # OUT1 OUT2 OUT3 OUT4
CASE 1
Output polarity + + - - buffer P1 P2 N3 N4 ON switch SA1, SW1 SC2, SW2 SA3, SW3 SC4, SW4
CASE 2
Output polarity - - + + buffer N3 N4 P1 P2 ON switch SB3, SW1 SD4, SW2 SB1, SW3 SD2, SW4
CASE 3
Output polarity + - - + buffer P1 N4 N3 P2 ON switch SA1, SW1 SD4, SW2 SA3, SW3 SD2, SW4
CASE 4
Output polarity - + + - buffer N3 P2 P1 N4 ON switch SB3, SW1 SC2, SW2 SB1, SW3 SC4, SW4

In the present invention, a charge share (POLCS) is performed only when the polarity of the data voltage is reversed, thereby reducing the amount of voltage fluctuation when the polarity is changed as shown in FIG. 13 and lowering the frequency of the data voltage, thereby reducing the power consumption of the source drive IC as shown in FIG. Compared to the impedance method (Hi-Z) or the charge count method, it can be significantly lowered. Such a charge share method can reduce the amount of fluctuation of the W data voltage to reduce the rising time of the W data voltage, thereby increasing the amount of charging of the W sub-pixel.

14 is a comparison of a voltage fluctuation amount, a frequency of a data voltage, and a dynamic power consumption in the charge share method of the present invention, the conventional high impedance method, and the charge count method. The dynamic power consumption is voltage fluctuation × frequency. In FIG. 14, White, Red, Green, Blue, Yellow, and Magenta represent the colors of the experimental image pattern. As can be seen from FIG. 14, the charge share method of the present invention can significantly lower power consumption compared to the conventional high impedance method and the charge share method in white and cyan colors, and the power consumption level of the conventional method in other colors or Further improved power consumption reduction effect can be obtained.

FIG. 15 is a view comparing the conventional high impedance method (Hi-Z) and the charge share method (CS), and the charge share method of the present invention in the white color of the experimental image pattern in FIG. 14. 16 is a view comparing the conventional high impedance method (Hi-Z) and the charge share method (CS), and the charge share method of the present invention in the red color of the experimental image pattern in FIG. 14. FIG. 17 is a view comparing the conventional high impedance method (Hi-Z) and the charge share method (CS), and the charge share method of the present invention in the green color of the experimental image pattern in FIG. 14. FIG. 18 is a diagram comparing a conventional high impedance method (Hi-Z) and a charge share method (CS), and a charge share method of the present invention in the blue color of the experimental image pattern in FIG. 14. FIG. 19 is a view comparing the conventional high impedance method (Hi-Z) and the charge share method (CS), and the charge share method of the present invention in the cyan color of the experimental image pattern in FIG. 14. FIG. 20 is a view comparing the conventional high impedance method (Hi-Z) and the charge share method (CS), and the charge share method of the present invention in the yellow color of the experimental image pattern in FIG. 14. FIG. 21 is a diagram comparing the conventional high impedance method (Hi-Z) and the charge share method (CS), and the charge share method of the present invention in the Magenta color of the experimental image pattern in FIG. 14. In FIGS. 15 to 21,'+' is a positive data voltage and'-' is a negative data voltage. 'X' is dummy data.

22 is a circuit diagram showing a source drive IC according to a second embodiment of the present invention. In Fig. 22, shift registers, latches, DACs, and the like of the source drive IC are omitted.

Referring to FIG. 22, the source drive IC includes a plurality of buffers P1, P2, N3, and N4, a plurality of switches, and a plurality of output channels OUT1 to OUT4.

The buffers P1, P2, N3, and N4 are P buffers P1 and P3 that supply the positive data voltage (+Vdata) input from the PDAC to the output channels, and the negative data voltage input from the NDAC ( It includes N buffers N2 and N4 supplying -Vdata) to the output channels. The P buffers P1 and P3 and the N buffers N2 and N4 may be alternately arranged in the shape shown in FIG. 22. The first P buffer P1 includes first data Data1 to be supplied to the first data line S1 through the first output channel OUT1, and the second data line S2 through the second output channel OUT2. The positive data voltage (+Vdata) of the third data Data3 to be supplied to the third data line S3 through the second data Data2 and the third output channel OUT3 is output. The first N buffer N2 includes first data Data1 to be supplied to the first data line S3 through the first output channel OUT1, and the second data line S2 through the second output channel OUT2. A negative data voltage (-Vdata) of the third data Data3 to be supplied to the third data line S3 through the second data Data2 and the third output channel OUT3 is output. The second P buffer P3 includes second data Data2 to be supplied to the second data line S2 through the second output channel OUT2, and the third data line S3 through the third output channel OUT3. The positive data voltage (+Vdata) of the third data Data3 to be supplied to the fourth data line S4 and the fourth data Data4 to be supplied to the fourth data line S4 through the fourth output channel OUT4 is output. The second N buffer N4 includes second data Data2 to be supplied to the second data line S2 through the second output channel OUT2, and the third data line S3 through the third output channel OUT3. The negative data voltage (-Vdata) of the fourth data Data4 to be supplied to the fourth data line S4 through the third data Data3 to be supplied to the device and the fourth output channel OUT4 is output.

The switches include a multiplexer (MUX) for data distribution, switches for data voltage supply (SW1 to SW4), switches for charge share (SW5, SW6), and the like.

The multiplexer (MUX) includes MUX switches (SA1 to SA4, SB1 to SB4, and SC1 to SC4) for distributing a data voltage output through one buffer to a plurality of output channels. The multiplexer (MUX) selects the polarity of the data voltage (+Vdata, -Vdata) in response to the polarity control signals (POL(S1), POL(S2), POL(S3), POL(S4)) shown in FIG. do. One buffer is connected to the three output channels through a multiplexer (MUX). Accordingly, the source drive IC of this embodiment can further reduce the number of necessary buffers compared to the source drive IC shown in FIG. 9.

The data voltage supply switches SW1 to SW4 are disposed between the multiplexer and the output channel to transmit the positive data voltage (+Vdata) and the negative data voltage (-Vdata) from the multiplexer to the output channels OUT1 to OUT4. Supply. Each of the data voltage supply switches SW1 to SW4 includes an input terminal connected to two MUX switches and an output terminal connected to one output channel. The first and third data voltage supply switches SW1 and SW3 apply positive/negative data voltages to the first and negative data voltages in response to the second logic value of the first source output enable signal SOE1 as shown in FIG. 11. It is supplied to the third output channels OUT1 and OUT3. The second and fourth data voltage supply switches SW2 and SW4 apply the positive/negative data voltage to the second and negative data voltages in response to the second logic value of the second source output enable signal SOE2 as shown in FIG. 12. It is supplied to the fourth output channels OUT2 and OUT4.

The CS switches SW5 and SW6 connect output channels in which the polarity of the data voltage changes simultaneously when the polarity of the data voltage changes. The first CS switch SW5 is connected to the first and third output channels OUT1 and OUT3 in response to a first logic value of the first source output enable signal SOE1 as shown in FIG. 11. 3 Connect the output channels OUT1 and OUT3 to perform charge share. The second CS switch SW6 is connected to the second and fourth output channels OUT2 and OUT4 in response to the first logic value of the second source output enable signal SOE2 as shown in FIG. 12. 4 Charge share is performed by connecting the output channels OUT2 and OUT4.

Operation states of the buffers and output channels shown in FIG. 22 may be divided as shown in Table 2 below.

Output channel # OUT1 OUT2 OUT3 OUT4
CASE 1
Output polarity + + - - buffer P1 P3 N2 N4 ON switch SA1, SW1 SA3, SW2 SC2, SW3 SC4, SW4
CASE 2
Output polarity - - + + buffer N2 N4 P1 P3 ON switch SB2, SW1 SA4, SW2 SC1, SW3 SC2, SW4
CASE 3
Output polarity + - - + buffer P1 N2 N4 P3 ON switch SA1, SW1 SB2, SW2 SB4, SW3 SC3, SW4
CASE 4
Output polarity - + + - buffer N2 P1 P3 N4 ON switch SA2, SW1 SB1, SW2 SB3, SW3 SC4, SW4

23 is a circuit diagram showing a source drive IC according to a third embodiment of the present invention. In Fig. 23, shift registers, latches, DACs, etc. of the source drive IC are omitted.

Referring to FIG. 23, the source drive IC includes a plurality of buffers P1, P2, N3, and N4, a plurality of switches, and a plurality of output channels OUT1 to OUT4.

The buffers P1, P2, N3, and N4 are P buffers P1 and P3 that supply the positive data voltage (+Vdata) input from the PDAC to the output channels, and the negative data voltage input from the NDAC ( It includes N buffers N2 and N4 supplying -Vdata) to the output channels. The P buffers P1 and P3 and the N buffers N2 and N4 may be alternately arranged in the shape as shown in FIG. 23. The first P buffer P1 includes first data Data1 to be supplied to the first data line S1 through the first output channel OUT1, and the third data line S3 through the third output channel OUT3. The positive data voltage (+Vdata) of the third data Data3 to be supplied to) is output. The first N buffer N2 includes first data Data1 to be supplied to the first data line S3 through the first output channel OUT1 and the third data line S3 through the second output channel OUT2. The negative data voltage (-Vdata) of the third data Data3 to be supplied to) is output. The second P buffer P3 includes second data Data2 to be supplied to the second data line S2 through the third output channel OUT3 and the fourth data line S4 through the fourth output channel OUT4. The positive data voltage (+Vdata) of the fourth data Data4 to be supplied to) is output. The second N buffer N4 includes second data Data2 to be supplied to the second data line S2 through the second output channel OUT2 and the fourth data line S4 through the fourth output channel OUT4. A negative data voltage (-Vdata) of the fourth data Data4 to be supplied to) is output.

The switches include a multiplexer (MUX) for data distribution, switches for data voltage supply (S1 to S4), switches for charge share (S5, S6), and the like.

The multiplexer (MUX) includes MUX switches (SA1, SB1, SA3, SB3, SC2, SD2, SC4, SD4) for distributing a data voltage output through one buffer to a plurality of output channels. The multiplexer (MUX) selects the polarity of the data voltage (+Vdata, -Vdata) in response to the polarity control signals (POL(S1), POL(S2), POL(S3), POL(S4)) shown in FIG. do.

The data voltage supply switches SW1 to SW4 are disposed between the multiplexer and the output channel to transmit the positive data voltage (+Vdata) and the negative data voltage (-Vdata) from the multiplexer to the output channels OUT1 to OUT4. Supply. Each of the data voltage supply switches S1 to S4 includes an input terminal connected to two MUX switches and an output terminal connected to one output channel. The first and second data voltage supply switches SW1 and SW2 apply positive/negative data voltages to the first and second logic values in response to the second logic value of the first source output enable signal SOE1 as shown in FIG. 11. It is supplied to the second output channels OUT1 and OUT2. The third and fourth data voltage supply switches SW3 and SW4 may change the positive/negative data voltage to the third and negative data voltages in response to the second logic value of the second source output enable signal SOE2 as shown in FIG. 12. It is supplied to the fourth output channels OUT3 and OUT4.

The CS switches SW5 and SW6 connect output channels in which the polarity of the data voltage changes simultaneously when the polarity of the data voltage changes. The first CS switch SW5 is connected to the first and second output channels OUT1 and OUT2 and in response to the first logic value of the first source output enable signal SOE1 as shown in FIG. 2 Connect the output channels OUT1 and OUT2 to perform charge share. The second CS switch SW6 is connected to the third and fourth output channels OUT3 and OUT4, and in response to the first logic value of the second source output enable signal SOE2 as shown in FIG. 4 Charge share is performed by connecting the output channels OUT3 and OUT4.

As shown in FIG. 23, buffers of the source drive IC may be arranged in the order of P1, N2, P3, and N4 from the left, and output channels from the left, OUT1, OUT2, OUT3, and OUT4. In this case, in order to reverse the polarity of the data voltages supplied to the data lines in the form of FIGS. 5 and 10, the second output channel OUT crosses the second and third data lines S2 and S3. ) May be connected to the third data line S3 and the third output channel OUT3 may be connected to the second data line S2. Most of the source drive ICs currently applied are manufactured in the structure shown in FIG. 23. Accordingly, in order to implement the polarity control as shown in FIGS. 5 and 10 without changing the structure of the source drive IC, a method of crossing some of the data lines as shown in FIG. 23 is preferable. Parasitic capacitance may exist at the intersection of the data lines S2 and S3, but the parasitic capacitance can be minimized by using an organic protective layer.

Operation states of the buffers and output channels illustrated in FIG. 23 may be divided as shown in Table 3 below.

Output channel # OUT1 OUT2 OUT3 OUT4
CASE 1
Output polarity + - + - buffer P1 N2 P3 N4 ON switch SA1, SW1 SD2, SW2 SB3, SW3 SC4, SW4
CASE 2
Output polarity - + - + buffer N2 P1 N4 P3 ON switch SC2, SW1 SB1, SW2 SD4, SW3 SA3, SW4
CASE 3
Output polarity + - - + buffer P1 N2 N4 P3 ON switch SA1, SW1 SD2, SW2 SD4, SW3 SA3, SW4
CASE 4
Output polarity - + + - buffer N2 P1 P3 N4 ON switch SC2, SW1 SB1, SW2 SB3, SW3 SC4, SW4

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: display panel 102: data driver
104: gate driver 20: timing controller

Claims (17)

A display panel including a plurality of data lines, a plurality of gate lines orthogonal to the data lines, and a pixel array;
A data driver supplying a data voltage to the data lines; And
A gate driver for supplying a gate pulse synchronized with the data voltage to the gate lines,
In the display panel, neighboring sub-pixels share one data line,
When the data lines are arranged in the order of a first data line, a second data line, a third data line, and a fourth data line from the left,
The first data line group includes the first and third data lines,
A second data line group includes the second and fourth data lines,
The data driver occupies the first data line group only when the polarity of the data voltages supplied to the data lines belonging to the first data line group is inverted and shares the data lines belonging to the second data line group. The second data line group is charged and shared only when the polarity of the supplied data voltage is reversed,
A display device in which a charge share timing of the first data line group is different from a charge share timing of the second data line group. The method of claim 1,
During a period in which data voltages having the same polarity are continuously output from the data driver, the white sub-pixels of the display panel charge the white data voltage, and then other sub-pixels other than the white sub-pixels charge different data voltages. Display device. delete The method of claim 1,
And a timing controller that controls operation timing of the data driver and the gate driver, and generates a polarity control signal and a source output enable signal,
The polarity control signal may include a first polarity control signal for controlling a polarity of a data voltage applied to the first data line;
A second polarity control signal for controlling a polarity of a data voltage applied to the second data line;
A third polarity control signal for controlling a polarity of a data voltage applied to the third data line; And
A fourth polarity control signal for controlling a polarity of a data voltage applied to the fourth data line,
The second polarity control signal has a phase difference with respect to the first polarity control signal by a preset time,
The third polarity control signal is an inversion signal of the first polarity control signal,
The fourth polarity control signal is an inversion signal of the second polarity control signal,
The data driver selects a positive data voltage in response to a first logic value of the polarity control signals, and selects a negative data voltage in response to a second logic value of the polarity control signals. The method of claim 4,
The source output enable signal is
A first source output enable signal for controlling output timing and charge share timing of data voltages supplied to data lines belonging to the first data line group; And
A second source output enable signal for controlling an output timing and a charge share timing of a data voltage supplied to data lines belonging to the second data line group,
The data driver performs a charge share in response to a first logic value of the source output enable signals, and outputs a data voltage in response to a second logic value of the source output enable signals. The method of claim 5,
The data driver includes a plurality of buffers, a plurality of switches, and a plurality of output channels,
The buffers are
First and second P buffers supplying a positive data voltage to the output channels,
First and second N buffers for supplying negative data voltage to the output channels,
The first P buffer outputs a positive data voltage of first data to be supplied to the first data line through a first output channel and third data to be supplied to the third data line through a third output channel, ,
The second P buffer outputs second data to be supplied to the second data line through a second output channel, and a positive data voltage of fourth data to be supplied to the fourth data line through a fourth output channel. ,
The first N buffer outputs negative data voltages of the first data and the third data,
The second N buffer outputs negative data voltages of the second data and the fourth data. The method of claim 6,
The switches include a multiplexer for distributing data using a plurality of MUX switches, a plurality of switches for supplying a data voltage, and switches for a charge share,
The above charge share switches
A first switch connecting the first and third output channels to perform charge sharing; And
And a second switch configured to perform charge sharing by connecting the second and fourth output channels. The method of claim 5,
The data driver includes a plurality of buffers, a plurality of switches, and a plurality of output channels,
The buffers are
First and second P buffers supplying a positive data voltage to the output channels,
First and second N buffers for supplying negative data voltage to the output channels,
The first P buffer includes first data to be supplied to the first data line through a first output channel, second data to be supplied to the second data line through a second output channel, and the third output channel. Output a positive data voltage of the third data to be supplied to the third data line,
The first N buffer outputs negative data voltages of the first data, the second data, and the third data,
The second P buffer outputs a positive data voltage of the second data, the third data, and fourth data to be supplied to the fourth data line through a fourth output channel,
The second N buffer outputs a negative data voltage of the second data, the third data, and the fourth data. The method of claim 8,
The switches include a multiplexer for distributing data using a plurality of MUX switches, a plurality of switches for supplying a data voltage, and switches for a charge share,
The above charge share switches
A first switch connecting the first and third output channels to perform charge sharing; And
And a second switch configured to perform charge sharing by connecting the second and fourth output channels. The method of claim 5,
The data driver includes a plurality of buffers, a plurality of switches, and a plurality of output channels,
The buffers are
First and second P buffers supplying a positive data voltage to the output channels,
First and second N buffers for supplying negative data voltage to the output channels,
The first P buffer outputs first data to be supplied to the first data line through a first output channel and a positive data voltage of third data to be supplied to the third data line through a second output channel, and ,
The first N buffer outputs negative data voltages of the first data and the third data,
The second P buffer outputs second data to be supplied to the second data line through a third output channel, and a positive data voltage of fourth data to be supplied to the fourth data line through a fourth output channel. ,
The second N buffer outputs negative data voltages of the second data and the fourth data. The method of claim 10,
The switches include a multiplexer for distributing data using a plurality of MUX switches, a plurality of switches for supplying a data voltage, and switches for a charge share,
The above charge share switches
A first switch connecting the first and second output channels to perform charge sharing; And
And a second switch configured to perform charge sharing by connecting the third and fourth output channels. The method of claim 11,
A display device in which the second and third data lines cross each other to connect the third data line to the second output channel, and to the second data line to the third output channel. A display panel including a plurality of data lines, a plurality of gate lines orthogonal to the data lines, and a pixel array;
A data driver supplying a data voltage to the data lines; And
A gate driver for supplying a gate pulse synchronized with the data voltage to the gate lines,
In the display panel, neighboring sub-pixels share one data line,
When the data lines are arranged in the order of a first data line, a second data line, a third data line, and a fourth data line from the left,
The first data line group includes the first and third data lines,
A second data line group includes the second and fourth data lines,
The data driver
A first switch turned on at a first charge share timing to charge share data lines belonging to the first data line group; And
And a second switch that is turned on at a second charge share timing different from the first charge share timing to charge share data lines belonging to the second data line group. The method of claim 13,
And a timing controller that controls operation timings of the data driver and the gate driver, and generates a polarity control signal and a source output enable signal. The method of claim 14,
The polarity control signal may include a first polarity control signal for controlling a polarity of a data voltage applied to the first data line group;
A second polarity control signal for controlling a polarity of a data voltage applied to the second data line;
A third polarity control signal for controlling a polarity of a data voltage applied to the third data line; And
A fourth polarity control signal for controlling a polarity of a data voltage applied to the fourth data line,
The second polarity control signal has a phase difference with respect to the first polarity control signal by a preset time,
The third polarity control signal is an inversion signal of the first polarity control signal,
The fourth polarity control signal is an inversion signal of the second polarity control signal,
The data driver selects a positive data voltage in response to a first logic value of the polarity control signals, and selects a negative data voltage in response to a second logic value of the polarity control signals. The method of claim 15,
The source output enable signal is
A first source output enable signal for controlling output timing and charge share timing of data voltages supplied to data lines belonging to the first data line group; And
A second source output enable signal for controlling an output timing and a charge share timing of a data voltage supplied to data lines belonging to the second data line group,
The data driver performs a charge share in response to a first logic value of the source output enable signals, and outputs a data voltage in response to a second logic value of the source output enable signals. The method of claim 1 or 13,
The display panel is a display device in which a white data voltage is first charged and then voltage is charged in an order of a red data voltage, a blue data voltage, and a green data voltage, or a blue data voltage, a red data voltage, and a green data voltage.

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