KR102188496B1 - Nano-sturucture semiconductor light emitting device - Google Patents

Abstract

According to an embodiment of the present invention, a plurality of nano light emitting structures each having a nanocore made of a first conductivity type semiconductor, an active layer and a second conductivity type semiconductor layer sequentially positioned on the surface of the nano core, and the plurality of nano A contact electrode made of a transparent conductive material, a contact electrode made of a transparent conductive material, a low refractive index layer having a first refractive index, and filling a space between the plurality of nano light emitting structures, and the plurality of A nanostructured semiconductor light emitting device including a high refractive index layer disposed on the low refractive index layer to cover the nano light emitting structure and having a second refractive index greater than the first refractive index may be provided.

Description

Nano structure semiconductor light emitting device {NANO-STURUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE}

The present invention relates to a three-dimensional nanostructure semiconductor light emitting device.

Recently, as a new semiconductor light emitting device technology, semiconductor light emitting devices using nanostructures have been developed. A semiconductor light emitting device using a nano structure (hereinafter referred to as a'nano structure semiconductor light emitting device') not only greatly improves crystallinity, but also can obtain an active layer on a non-polar or semi-polar surface, thereby reducing efficiency due to polarization. Can be prevented. In addition, since it can emit light through a large surface area, light efficiency can be greatly improved. In order to effectively maintain such improved light efficiency, the nanostructure semiconductor light emitting device needs to further improve external quantum efficiency, that is, light extraction efficiency.

In the art, there is a need for a three-dimensional nanostructure semiconductor light emitting device equipped with a light extraction structure configured to suit a unique shape in which a plurality of nano light emitting structures are arranged.

According to an embodiment of the present invention, a plurality of nano light emitting structures each having a nanocore made of a first conductivity type semiconductor, an active layer and a second conductivity type semiconductor layer sequentially positioned on the surface of the nano core, and the plurality of nano A contact electrode made of a transparent conductive material, a contact electrode made of a transparent conductive material, a low refractive index layer having a first refractive index, and filling a space between the plurality of nano light emitting structures, and the plurality of A nanostructured semiconductor light emitting device including a high refractive index layer disposed on the low refractive index layer to cover the nano light emitting structure and having a second refractive index greater than the first refractive index may be provided.

The low refractive index layer may have a level lower than the height of the nano light emitting structure. In this case, a part of the high refractive index layer may be filled between the nano light emitting structures to have an interface in contact with the low refractive index layer.

The contact electrode may be disposed on an upper surface of the low refractive index layer and a surface of an area higher than the upper surface of the low refractive index layer of the nano light emitting structure. In this case, a part of the high refractive index layer may be filled between the nano light emitting structures to have an interface in contact with the contact electrode.

In a specific example, the nano light emitting structure may include a main portion having a side surface that is a first crystal plane and an upper end portion having a surface that is a second crystal surface different from the first crystal surface.

The first crystal plane may be an m plane, and the second crystal plane may be an r plane. Alternatively, the first crystal plane may be an m plane, and the second crystal plane may be a c plane.

A part of the high refractive index layer is filled between the nano light emitting structures to have an interface with the low refractive index layer, and the interface may be located on a side surface of the nano light emitting structure.

The interface may be located in a range of 50% or more from the height of the main part of the nano light emitting structure.

The contact electrode may be disposed on the side of the nano light-emitting structure so that the upper end of the nano light-emitting structure is exposed. In this case, the contact electrode may be formed to have substantially the same height as the level of the low refractive index layer.

The first refractive index may be 1.5 or less, and the second refractive index may be 1.7 or more.

The first refractive index may be smaller than the refractive index of the nano light emitting structure, and a difference between the first refractive index and the second refractive index may be 0.2 or more.

At least one intermediate refractive index layer disposed between the low refractive index layer and the high refractive index layer and having a refractive index between the first and second refractive indexes may be further included.

A pattern for light extraction may be disposed on the upper surface of the high refractive index layer. In this case, the light extraction pattern may have an uneven structure integrated with the high refractive index layer.

According to an embodiment of the present invention, a nanostructure semiconductor light emission including a plurality of nano light-emitting structures, a contact electrode made of a transparent conductive material, and a light-transmitting protection part made of a transparent material, disposed on the surface of the plurality of nano light-emitting structures Device can be provided. The light-transmitting protection part is filled in the space between the plurality of nano light-emitting structures, is a low refractive index having a first refractive index, and is disposed on the plurality of nano light-emitting structures, and has a second refractive index greater than the first refractive index. A refractive index layer may be provided.

The low refractive index layer may have a level lower than the height of the nano light emitting structure, and a part of the high refractive index layer may be filled between the nano light emitting structures to have an interface with the low refractive index layer.

The first refractive index may be smaller than the refractive index of the nano light emitting structure.

An embodiment of the present invention provides a lighting device comprising a light emitting module having the above-described nanostructure semiconductor light emitting device, a driving unit configured to drive the light emitting module, and an external connection unit configured to supply an external voltage to the driving unit. can do.

By disposing layers having different refractive indices in different regions, it is possible to improve light extraction efficiency in a desired direction. For example, by filling or emptying (air filling) a material having a relatively low refractive index between the nano light-emitting structures, light traveling in the lateral direction can be suppressed, thereby increasing light extraction efficiency. In addition, by applying a material having a relatively high refractive index toward the upper direction, it is possible to improve the efficiency of light extraction toward a desired upper direction.

1 is a cross-sectional view of a nanostructured semiconductor light emitting device according to an embodiment of the present invention.
FIG. 2 is a schematic perspective view showing an example of a nanocore employable in FIG. 1.
3 is a schematic perspective view showing another example of a nano core.
4A and 4B are cross-sectional views of a nano light emitting structure for explaining the principle of improving light extraction efficiency in the embodiment shown in FIG. 1.
5A to 5E are cross-sectional views illustrating a method of manufacturing the nanostructured semiconductor light emitting device shown in FIG. 1.
6 is a graph showing changes in light extraction efficiency according to refractive index conditions of a low refractive index layer and a high refractive index layer.
7 is a graph showing a change in light extraction efficiency according to an interface position between a low refractive index layer and a high refractive index layer.
8A to 8E are cross-sectional views according to major processes for explaining another example of a method of manufacturing a nanostructured semiconductor light emitting device.
9A and 9B are plan views of masks showing various examples of opening shapes.
10A and 10B are side cross-sectional views of a mask showing various examples of the shape of an opening.
11A and 11B are schematic diagrams for explaining a heat treatment process applicable to FIG. 8D.
12A to 12D are cross-sectional views for explaining a process for obtaining a nano core using the mask shown in FIG. 10A.
13 is a cross-sectional view of a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
14 is a cross-sectional view of a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
15 is a cross-sectional view of a nanostructured semiconductor light emitting device according to an embodiment of the present invention.
16 is a cross-sectional view of a nanostructured semiconductor light emitting device according to an embodiment of the present invention.
17 is a cross-sectional view of a nanostructured semiconductor light emitting device according to an embodiment of the present invention.
18 is a cross-sectional view of a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
19 and 20 show various examples of a semiconductor light emitting device package employing a nanostructured semiconductor light emitting device according to an embodiment of the present invention.
21 and 22 show examples of a backlight unit employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
23 shows an example of a lighting device employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
24 shows an example of a headlamp employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

These embodiments may be modified in different forms or may be combined with each other, and the scope of the present invention is not limited to the embodiments described below. In addition, the present embodiments are provided to more completely explain the present invention to those with average knowledge in the art. For example, the shape and size of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

On the other hand, the expression "one example" used in the present specification does not mean the same embodiment, and is provided to emphasize and describe different unique features. However, the embodiments presented in the description below do not exclude that they are implemented in combination with features of other embodiments. For example, even if a matter described in a specific embodiment is not described in another embodiment, it may be understood as a description related to another embodiment unless there is a description contradicting or contradicting the matter in another embodiment.

1 is a cross-sectional view of a nanostructured semiconductor light emitting device according to an embodiment of the present invention.

The nanostructure semiconductor light emitting device 10 illustrated in FIG. 1 may include a base layer 12 made of a first conductivity type semiconductor material and a plurality of nano light emitting structures 15 disposed thereon. In addition, the nanostructured semiconductor light emitting device 10 may include a substrate 11 having an upper surface on which the base layer 12 is disposed.

A convex pattern R may be formed on the upper surface of the substrate 11. The irregularities R may improve the quality of a single crystal grown while improving light extraction efficiency. The substrate 11 may be an insulating, conductive, or semiconductor substrate. For example, the substrate 11 may be sapphire, SiC, Si, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , or GaN.

The base layer 12 may provide a growth surface of the nano light emitting structure 15. The base layer 12 may be a nitride semiconductor satisfying Al _x In _y Ga _{1 -x- y} N (0≤x<1, 0≤y<1, 0≤x+y<1), and a specific conductivity It can be doped with type impurities. For example, the base layer 12 may be doped with n-type impurities such as Si.

An insulating film 13 having an opening for growing a nano light emitting structure 15 (especially, a nano core) may be formed on the base layer 12. A nano core 15a may be formed in the area of the base layer 12 exposed by the opening. The insulating layer 13 may be used as a mask for growing the nano core 15a. For example, the insulating layer 13 may be an insulating material such as SiO ₂ or SiN _x .

The nano light emitting structure 15 has a nano core 15a made of a first conductivity type semiconductor, an active layer 15b sequentially formed on the surface of the nano core 15a, and a second conductivity type semiconductor layer 15c. I can. The nano core 15a satisfies Al _x In _y Ga _{1 -x- y} N (0≤x<1, 0≤y<1, 0≤x+y<1) similar to the base layer 12 It may be a nitride semiconductor. For example, the nano core 15a may be n-type GaN. The active layer 15b may have a multiple quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked with each other. For example, in the case of a nitride semiconductor, it may have a multiple quantum well structure of GaN/InGaN. If necessary, the active layer 15b may have a single quantum well (SQW) structure. The second conductivity type semiconductor layer 15c is a crystal satisfying p-type Al _x In _y Ga _{1 -xy} N (0≤x<1, 0≤y<1, 0≤x+y<1), and Accordingly, it may be composed of a plurality of layers.

As shown in FIG. 2, the nano light emitting structure 15 employed in the present embodiment may include a main portion M having a hexagonal column structure and an upper end T positioned on the main portion M. . The main part M of the nano light-emitting structure 15 has sides that are the same crystal plane, and the upper part T of the nano light-emitting structure 15 has a crystal plane different from that of the side surfaces of the nano light-emitting structure 15. I can. The upper end portion T of the nano light emitting structure 15 may have a hexagonal pyramid shape.

The shape of the nano light-emitting structure 15 and each crystal plane may be determined by the shape and each crystal plane of the nano core 15a, and the nano light-emitting structure 15 employable in the present embodiment may also be changed in various forms. . That is, according to the grown nano core or subsequent process, the nano light emitting structure 15 may have a different shape and a different crystal plane.

For example, as shown in Figure 3, the nano light-emitting structure 25, similar to Figure 2, has a main portion (M) providing a side surface having a first crystal plane (r), but the upper end (T) Is a crystal plane different from the first crystal plane, but may have a plane (c') that is not a completely semi-polar plane. In addition, in a specific example (see FIG. 17), the top surface of the nano light emitting structure may have a flat surface by using a planarization process or the like.

The nanostructured semiconductor light emitting device 10 may include a contact electrode 16 connected to the second conductivity type semiconductor layer 15c. The contact electrode 16 employed in this embodiment may be made of a transparent conductive material. Although not limited thereto, the contact electrode 16 may be one of a transparent conductive oxide layer or a nitride layer in order to emit light toward the nano light emitting structure side (a direction opposite to the substrate side). For example, ITO (Indium Tin Oxide), ZITO (Zinc-doped Indium Tin Oxide), ZIO (Zinc Indium Oxide), GIO (Gallium Indium Oxide), ZTO (Zinc Tin Oxide), FTO (Fluorine-doped Tin Oxide), AZO (Aluminium-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), In ₄ Sn ₃ O ₁₂ or Zn _(1-x) Mg _x O (Zinc Magnesium Oxide, 0≤x≤1) selected from the group consisting of There may be at least one. If necessary, the contact electrode 16 may include graphene.

The nanostructured semiconductor light emitting device 10 may include a light-transmitting protective layer 17 formed on an upper surface of the nano light emitting structure 15. This light-transmitting protective layer 17 may serve as a passivation capable of protecting the nano light-emitting structure 15.

The light-transmitting protective layer 17 employed in the present embodiment may be provided to improve light extraction efficiency suitable for the nano light-emitting structure 15. The light-transmitting protective layer 17 may include a low refractive index layer 17a having a first refractive index and a high refractive index layer 17b having a second refractive index greater than the first refractive index. The low refractive index layer 17a may be filled in the space between the plurality of nano light emitting structures 15, and the high refractive index layer 17b may be positioned on the plurality of nano light emitting structures 15.

1, the high refractive index layer 17b may be disposed on the low refractive index layer 17a to cover the plurality of nano light emitting structures 15. Light extraction efficiency in the upper direction can be greatly improved by the light-transmitting protective layer 17.

Specifically, according to Snell's law, since light traveling to a region having a relatively low refractive index increases an incidence angle range for total reflection, the amount of light traveling can be suppressed. On the contrary, since the incident angle range of total reflection is smaller than that of light traveling to a region having a relatively high refractive index, the amount of light traveling can be increased.

Therefore, when compared with a form having a single refractive index layer (see Fig. 4a), in the light-transmitting protective layer 17 employed in this embodiment (see Fig. 4b), the high refractive index layer 17b is a nano light emitting structure. (15) Arranged on the top to increase the amount of light that proceeds upward, while the low refractive index layer (17a) is disposed in the space between the nano light-emitting structures (15) to proceed in the lateral direction of the nano-light-emitting structures (15) Can be reduced. In this way, by suppressing the propagation of light in the lateral direction of the nano light-emitting structure 15 and effectively extracting light in the upper direction, effective luminous efficiency in a desired upper direction can be greatly improved.

In FIG. 4A, a single refractive index layer was exemplified as a low refractive index layer 17a to prepare, but the same applies to the case of changing to a high refractive index layer 17b. That is, even when the high refractive index layer 17b is introduced as a single refractive index layer in FIG. 4A, since the amount of light propagating in the lateral direction of the nano light emitting structure 15 increases, the nano light emitting structure 15 is compared with the structure of FIG. 4B. The light propagating in the upper direction of is inevitably reduced.

As described above, the nano light emitting structure 15 may include GaN (refractive index: about 2.4). In this case, the second refractive index (in the range of about 1.7 to about 3) of the high refractive index layer 17b disposed on the top is formed of a material having a range similar to the refractive index of the nano light-emitting structure 15, and is disposed on the side thereof. The low refractive index layer 17a may be formed of a material having a first refractive index (about 1.5 or less) lower than the second refractive index. In other words, the first refractive index may be smaller than the refractive index of the nano light emitting structure, and a difference between the first refractive index and the second refractive index may be 0.2 or more. In a specific example, the low refractive index layer 17a may be air not filled with another material layer.

In this way, in consideration of the refractive index of the nano light-emitting structure 15, the refractive index of the low refractive index layer 17a and the high refractive index layer 17b is also designed, and a desired light-transmitting absorption layer can be formed by selecting an appropriate material. Refractive index conditions of the low refractive index layer 17a and the high refractive index layer 17b will be described in more detail with reference to FIGS. 8 and 9.

The nanostructured semiconductor light emitting device 10 may include first and second electrodes 19a and 19b. The first electrode 19a may be disposed in a region where a portion of the base layer 12 made of a first conductivity type semiconductor is exposed. In addition, the second electrode 19b may be disposed in a region where the contact electrode 16 is extended and exposed.

5A to 5E are cross-sectional views illustrating a method of manufacturing the nanostructured semiconductor light emitting device shown in FIG. 1.

As shown in FIG. 5A, a plurality of nano cores 15a may be formed on the base layer 12 made of a first conductivity type semiconductor.

The substrate 11 may have an upper surface on which the concave portion R is formed. The base layer 12 may be formed on the upper surface of the substrate 11. An insulating film 13 having an opening is formed on the base layer 12. Using the insulating layer 13 as a mask, a desired nano core 15a may be grown in the exposed area of the base layer 12.

In this embodiment, the nanocore 15 formed using selective growth was described, but unlike this, a desired nanocore is grown by using a mold having an opening area corresponding to the desired nanocore and removing the mold. Can be obtained.

As shown in FIG. 5B, an active layer 15b and a second conductivity type semiconductor layer 15c may be sequentially formed on the surfaces of the plurality of nano cores 15a.

Through this process, a plurality of desired nano light-emitting structures 15 can be formed. The active layer 15b may have a multiple quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked with each other. For example, in the case of a nitride semiconductor, it may have a multiple quantum well structure of GaN/InGaN. If necessary, the active layer 15b may have a single quantum well (SQW) structure. The second conductivity type semiconductor layer 15c is a crystal satisfying p-type Al _x In _y Ga _{1 -xy} N (0≤x<1, 0≤y<1, 0≤x+y<1), and Accordingly, it may be composed of a plurality of layers. For example, the second conductivity type semiconductor layer 15c may include an AlGaN electron blocking layer and a GaN contact layer.

Next, as shown in FIG. 5C, a contact electrode 16 may be formed on the nano light emitting structure 15.

The contact electrode 16 may be formed on the surface of the second conductivity type semiconductor layer 15c. Although not limited thereto, the contact electrode 16 employed in this embodiment may be made of a transparent conductive material. The contact electrode 16 may be either a transparent conductive oxide layer or a nitride layer. For example, ITO (Indium Tin Oxide), ZITO (Zinc-doped Indium Tin Oxide), ZIO (Zinc Indium Oxide), GIO (Gallium Indium Oxide), ZTO (Zinc Tin Oxide), FTO (Fluorine-doped Tin Oxide), AZO (Aluminium-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), In ₄ Sn ₃ O ₁₂ or Zn _(1-x) Mg _x O (Zinc Magnesium Oxide, 0≤x≤1) selected from the group consisting of There may be at least one. If necessary, the contact electrode 16 may include graphene. A space S may exist between the nano light emitting structures 15.

Subsequently, as shown in FIG. 5D, a low refractive index layer 17a may be formed to fill the space S between the nano light emitting structures 15.

As the low refractive index layer 17a, a material having a low refractive index such as SiO ₂ (1.46) may be used. The low refractive index layer 17a may be formed by a deposition process such as a chemical vapor deposition process (CVD) or a physical vapor deposition process (PVD). Alternatively, a process different from a material that can be easily filled in the space between the nano light emitting structures 15 may be used. For example, the low refractive index layer 17a may be made of TEOS (TetraEthylOrthoSilane), BPSG (BoroPhospho Silicate Glass), CVD-SiO ₂ , SOG (Spin-on Glass), SOD (Spin-on Delectric) materials. In this case, since the fluidity of each material is used, the filling process can be easily performed by spin coating or reflow process.

Meanwhile, a light-transmitting resin having a relatively low refractive index (1.4 to 1.7) and excellent in workability may also be used as the low refractive index layer 17a. For example, as the light-transmitting resin, at least one resin selected from epoxy resin, silicone resin, polyethylene, and polycarbonate may be used. The low refractive index layer 17a may employ a porous structure in order to implement a lower refractive index. For example, when porous silicon is used, a refractive index of about 1.2 levels can be achieved.

The low refractive index layer 17a may be formed to have a level L1 lower than the height of the nano light emitting structure. Accordingly, a space in which a high refractive index layer (17b in FIG. 9) can be positioned on the nano light emitting structure 15 may be provided. The level L1 of the low refractive index layer 17a may be located at a point equal to or greater than 50% of the height H defined as the main portion of the nano light emitting structure 15. .

Subsequently, as shown in FIG. 5E, a high refractive index layer 17b may be formed on the low refractive index layer 17a.

The high refractive index layer 17b may be formed to cover the nano light emitting structure 15. That is, the level L2 of the high refractive index layer 17b may be formed higher than the total height of the nano light emitting structure 15. In this embodiment, the high refractive index layer 17b may directly contact the low refractive index layer 17a to have an interface. In addition, a part of the high refractive index layer 17b may be formed to fill the space between the nano light emitting structures 15. Accordingly, it may be located in a partial area of the main part of the nano light emitting structure 15. Through the arrangement of the high refractive index layer 17b, more light can be extracted from the nano light emitting structure 15 to the upper portion through the high refractive index layer 17b. As shown in FIG. 9, the high refractive index layer 17b may be formed to have a thickness t of a portion located in the main portion of the nano light emitting structure 15. This thickness (t) may be 50% or less of the height (H) defined as the main portion of the nano light emitting structure (15). .

The high refractive index layer 17b may be formed by a deposition process such as a chemical vapor deposition process (CVD) or a physical vapor deposition process (PVD). The high refractive index layer 17b has a larger refractive index than the low refractive index layer 17a. The refractive index of the high refractive index layer 17b is determined according to the refractive index of the low refractive index layer 17a, but when the refractive index layer of the low refractive index layer 17a is about 1.5 or less, the refractive index of the high refractive index layer 17b May be greater than or equal to about 1.7.

In order to improve light extraction efficiency in the upper direction, the high refractive index layer 17b may have a refractive index similar to or higher than that of the nano light emitting structure 15. For example, when the nano light-emitting structure 15 is GaN (about 2.4), it may be 1.9 or more, preferably 2.0 or more.

For example, the high refractive index layer 17b is TiO ₂ (2.8), SiC (2.69), ZnO (2.1), ZrO ₂ (2.23), ZnS (2.66), SiN (2.05), HfO ₂ (1.95) and It may be at least one of the diamonds (2.44) (refractive index (@450nm) in parentheses).

6 is a graph showing changes in light extraction efficiency according to refractive index conditions of a low refractive index layer and a high refractive index layer.

The x-axis represents the second refractive index, which is the refractive index of the high refractive index layer, and the y-axis represents light extraction efficiency. The reference value Ref represents the light extraction efficiency when the light-transmitting protective layer is not applied.

When the first refractive index, which is the refractive index of the low refractive index layer, is 1 (Air), 1.5, 2, and 2.5, the light extraction efficiency in the upper direction of the nano light emitting structure was measured while changing the second refractive index. When the first refractive index (n ₁ ) corresponding to the low refractive index layer is higher than the second refractive index (n ₂ ), the light extraction efficiency is generally less than the reference value. When the first and second refractive indices are the same, the light extraction efficiency slightly increases only when the same refractive index value is higher than the refractive index of the nano light emitting structure (2.4) (2.5).

On the other hand, according to the conditions of the present invention, when the second refractive index is greater than the first refractive index, it is confirmed that the light extraction efficiency is significantly improved than that of a single layer having a high refractive index (n ₂ /n ₁ =2.5/2.5). I can. For example, when the refractive index condition (n ₂ /n ₁ ) was 2.5/2.0, 2.4/1, 2.0/1.5, 2.5/1.5, 3.0/1.5, it was found that the light extraction efficiency was improved by 5-7%. . In particular, when the low refractive index layer (first refractive index) was 1.5 or less than when 2.0, it was confirmed that the effect of improving the light extraction efficiency was large.

As described in FIGS. 5D and 5E, the high refractive index layer covering the upper end of the nano light-emitting structure may extend to the main part of the nano light-emitting structure and cover the side surface thereof. In this way, more light can be extracted upward through the portion in which the high refractive index layer extends to the main portion.

7 is a graph showing a change in light extraction efficiency according to an interface position between a low refractive index layer and a high refractive index layer. When defining the coating rate (%) as the ratio of the thickness (t) of the part covering the main part of the high refractive index layer to the height (H) of the main part of the nano light-emitting structure, when it is increased to about 50%, it is higher than the reference value (REF). It can be seen that it has increased. Here, the reference value REF refers to the light extraction efficiency obtained when a high refractive index layer is employed, and is located only at the upper end of the nano light emitting structure and does not extend to the main part.

In this way, light extraction efficiency can be greatly improved by extending the high refractive index layer to the main portion of the nano light emitting structure at an appropriate level.

The nanostructure semiconductor light emitting device according to the present embodiment may be manufactured by various manufacturing methods. 8A to 8E are examples of a method of manufacturing a nanostructured semiconductor light emitting device, showing a process of growing a nanocore by using a mask as a mold structure. This process may be understood as a process replacing the process of forming the nano light-emitting structure shown in FIGS. 5A and 5B.

As shown in FIG. 8A, a base layer 32 may be provided by growing a first conductivity type semiconductor on the substrate 31.

The base layer 32 not only provides a crystal growth surface for growing the nano light emitting structure, but also provides a structure electrically connecting the polarities of one side of the nano light emitting structure to each other. Accordingly, the base layer 32 may be formed of a semiconductor single crystal having electrical conductivity. When the base layer 32 is directly grown, the substrate 31 may be a substrate for crystal growth. A buffer layer composed of Al _x In _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) on the substrate 31 before growth of the base layer 32 is included. Thus, a multilayer structure may be additionally formed. The multilayer structure includes an undoped GaN layer and an AlGaN layer or an intermediate layer composed of a combination of these layers to prevent current leakage from the base layer 32 to the buffer layer and improve the crystal quality of the base layer 32. .

Next, as shown in FIG. 8B, a mask 33 having a plurality of openings H and including an etch stop layer is formed on the base layer 32.

The mask 33 employed in this example includes a first material layer 33a formed on the base layer 32 and an etch rate of the first material layer 33a formed on the first material layer 33a. A second material layer 33b having a higher etch rate may be included.

The first material layer 33a may be provided as the etch stop layer. That is, the first material layer 33a has an etch rate lower than that of the second material layer 33b under the etching conditions of the second material layer. At least the first material layer 33a is a material having electrical insulation properties, and if necessary, the second material layer 33b may also be an insulation material.

The first and second material layers 33a and 33b may be formed of different materials to obtain a desired difference in etch rate. For example, the first material layer 33a may be a SiN-based material, and the second material layer 33b may be SiO ₂ . Alternatively, the difference in the etch rate may be implemented using the pore density. The second material layer 33b or both the first and second material layers 33a and 33b are used as a material having a porous structure, and the difference in porosity is adjusted to form the first and second material layers 33a and 33b. It is possible to secure a difference in the etch rate of. In this case, the first and second material layers 33a and 33b may be formed of the same material. For example, the first material layer 33a is made of SiO ₂ having a first porosity, and the second material layer 33b is made of the same SiO ₂ as the first material layer 33a, but is larger than the first porosity. It can have 2 porosity. Accordingly, under the condition that the second material layer 33a is etched, the first material layer 33a may have an etch rate lower than that of the second material layer 33b.

The total thickness of the first and second material layers 33a and 33b may be designed in consideration of a desired height of the nano light-emitting structure. The etch stop level by the first material layer 33a may be designed in consideration of the total height of the mask 33 from the surface of the base layer 32. After the first and second material layers 33a and 33b are sequentially formed on the base layer 32, a plurality of openings H may be formed to expose the base layer 32 region. The formation of the opening (H) may be performed by forming a photoresist on the mask layer 33 and using the photoresist and a wet/dry etching process using the same. The size of each opening H may be designed in consideration of the size of the desired nano light emitting structure. For example, the opening H exposing the surface of the base layer 32 may be 600 nm or less of the width (diameter), and further 50 to 500 nm or less.

The opening H may be manufactured using a semiconductor process, and for example, the opening H having a high aspect ratio may be formed using a deep-etching process. The aspect ratio of the opening H may be 5:1 or more, and further 10:1 or more.

Although it may vary depending on the etching conditions, in general, the opening H in the first and second material layers 33a and 33b may have a width that decreases toward the base layer 32.

In general, a dry etching process is used for the deep etching process, and reactive ions generated from plasma may be used or an ion beam generated in a high vacuum may be used. Compared with wet etching, such dry etching can perform precise processing of microstructures without geometric limitations. A CF-based gas may be used for etching the oxide layer of the mask 33. For example, an etchant in which at least one of O ₂ and Ar is combined with a gas such as CF ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ , and CHF ₃ may be used.

The planar shape and arrangement of the opening H may be variously implemented. For example, in the case of a flat shape, it may be implemented in various ways such as a polygon, a square, an oval, and a circle. The mask 33 shown in FIG. 8B may have an array of openings H having a circular cross section, as shown in FIG. 9A, but may have different shapes and arrangements as needed. For example, like the mask 33' shown in FIG. 9B, an array of openings having a regular hexagonal cross section may be provided.

The opening H shown in FIG. 8B is illustrated as a rod structure having a constant diameter (or width), but is not limited thereto, and may have various structures using an appropriate etching process. As such an example, masks having openings of different shapes are shown in Figs. 10A and 10B. In the case of FIG. 10A, the mask 43 made of the first and second material layers 43a and 43b has an opening H of a column structure having a shape of increasing cross-sectional area as it goes upward, and in the case of FIG. 10B, The mask 43 ′ formed of the first and second material layers 43a ′ and 43b ′ may have a columnar opening H having a shape whose cross-sectional area decreases toward the top.

Next, as shown in Fig. 8C, a plurality of nano cores 35a are formed by growing a first conductivity type semiconductor in the exposed area of the base layer 32 so that the plurality of openings H are filled. Then, a current blocking intermediate layer 34 is formed on the upper end (T) of the nano core 35a.

The first conductivity type semiconductor of the nano core 35a may be an n-type nitride semiconductor, and may be the same material as the first conductivity type semiconductor of the base layer 32. For example, the base layer 32 and the nano core 35a may be formed of n-type GaN.

The nitride single crystal constituting the nano core 35a may be formed by using an MOCVD or MBE process, and the mask 33 acts as a mold for the grown nitride single crystal to correspond to the shape of the opening (H). (35a) can be provided. That is, the nitride single crystal is selectively grown in the region of the base layer 32 exposed to the opening H by the mask 33, filling the opening H, and the nitride single crystal to be filled is the opening ( It may have a shape corresponding to the shape of H).

A current blocking intermediate layer 34 is formed on the surface of the upper end portion T of the nano core 35a while leaving the mask 33 as it is. Therefore, it is possible to easily form the current blocking intermediate layer 34 on a desired upper end without a separate mask forming process.

The current blocking intermediate layer 34 may be a semiconductor layer that is not intentionally doped or is doped with a second conductivity type impurity opposite to the nano core 35a. For example, when the nanocore 35a is n-type GaN, the current blocking intermediate layer 34 may be undoped GaN or GaN doped with p-type impurities such as Mg. In this case, the nano core 35a and the current blocking intermediate layer 34 can be continuously formed by switching only the types of impurities in the same growth process. In this way, the entire process may be further simplified by combining the forming process of the current blocking intermediate layer 34 and the molding process.

Subsequently, as shown in FIG. 8D, the mask 33 is removed to the first material layer 33a as the etch stop layer so that the side surfaces of the plurality of nano cores 35a are partially exposed.

In the present embodiment, by applying an etching process in which the second material layer 33b can be selectively removed, only the second material layer 33b may be removed and the first material layer 33a may remain. . The remaining first material layer 33a may prevent the active layer 35b and the second conductivity type semiconductor layer 35c from being connected to the base layer 32 in a subsequent growth process.

As in this example, in the manufacturing process of the nano light emitting structure using a mask having an opening as a mold, an additional heat treatment process may be introduced to improve crystallinity.

First, in order to improve the crystal quality of the nanocore during the growth of the nanocore 35a before the current blocking intermediate layer 34 is formed, a stabilization process (heat treatment process) of the nanocore 35a may be additionally performed. have. That is, when growing to the midpoint of growth of the desired nanocore 35a (about 0.2 to 1.8 μm in height as the base layer), the supply of the TMGa source, which is a supply source of the group III element of GaN, is stopped, and about 5 seconds in the NH ₃ atmosphere. Heat treatment may be performed for about 5 minutes at a temperature similar to that of the substrate during growth (about 1000 to 1200°C).

In addition, after completing the growth of the nano core (35a) and removing the upper layer (33b) of the mask, the surface of the nanocore (35a) is heat-treated under certain conditions to make the crystal plane of the nanocore (35a) semi-polar or non-polar. It can be converted into a stable surface that is advantageous for crystal growth, such as a crystal surface. This process can be described with reference to FIGS. 11A and 11B.

11A and 11B are schematic diagrams for explaining a heat treatment process applicable to the process of FIG. 8D.

Fig. 11A can be understood as the nanocore 35a obtained in Fig. 8D. The nano core 35a has a crystal plane determined according to the shape of the opening. Although it varies depending on the shape of the opening, in general, the surface of the nanocore 35a thus obtained has a relatively unstable crystal plane, and may not be a favorable condition for subsequent crystal growth.

As in the present embodiment, when the opening has a cylindrical rod shape, as shown in Fig. 11A, the side surface of the nano core 35a may have a curved surface other than a specific crystal surface.

When the nano-core 35a is heat-treated, unstable crystals on the surface thereof are rearranged, and as shown in FIG. 11B, a stable crystal plane such as semi-polar or non-polar can be obtained. The heat treatment conditions can be converted to a desired stable crystal plane by performing the heat treatment conditions at 600°C or higher, and in a specific example, 800 to 1200°C for several seconds to tens of minutes (1 second to 60 minutes).

In this heat treatment process, if the substrate temperature is lower than 600°C, crystal growth and rearrangement of the nano-core are difficult, making it difficult to expect a heat treatment effect. If the temperature is higher than 1200°C, nitrogen (N) evaporates from the GaN crystal plane, resulting in a decrease in crystal quality . In addition, it is difficult to expect a sufficient heat treatment effect for a time shorter than 1 second, and heat treatment for a time longer than several tens of minutes, for example, 60 minutes may reduce the efficiency of the manufacturing process.

For example, when grown on the C (0001) plane ((111) plane in the case of a silicon substrate) of the sapphire substrate, the nano-core 35a having a cylindrical shape shown in FIG. 6A is in the appropriate temperature range described above. By heat treatment at, the curved surface (side surface), which is an unstable crystal surface, can be converted into a hexagonal crystal column (35a' in Fig. 11B) having a non-polar surface (m surface) that is a stable crystal surface. The stabilization process of such a crystal plane can be realized by a high-temperature heat treatment process.

This principle is difficult to clearly explain, but it can be understood that partial regrowth proceeds so as to have a stable crystal plane by depositing such residual source gas when crystals located on the surface are rearranged at high temperatures or when the source gas remains in the chamber.

In particular, in terms of regrowth, the heat treatment process may be performed in an atmosphere in which the source gas remains in the chamber, or the heat treatment may be performed under conditions of intentionally supplying a small amount of source gas. For example, as shown in FIG. 11A, in the case of the MOCVD chamber, TMGa and NH ₃ remain, and by heat treatment in such a residual atmosphere, the source gas reacts on the surface of the nanocore, and partial regrowth is performed to have a stable crystal plane. Can be done. Due to this regrowth, the width of the heat-treated nanocore 35a' may be slightly larger than the width of the nanocore 35a before the heat treatment (see FIGS. 11A and 11B).

In this way, by introducing an additional heat treatment process, it may contribute to improving the crystallinity of the nanocore. That is, through such a heat treatment process, non-uniformities (eg, defects, etc.) existing on the surface of the nanocore after removing the mask can be removed, and stability of the crystal can be greatly improved through rearrangement of the internal crystals. . This heat treatment process may be performed under conditions similar to the growth process of the nano core in the chamber after removing the mask. For example, the heat treatment temperature (eg, the substrate temperature) may be performed between 800 and 1200° C., but similar effects can be expected in a heat treatment process of 600° C. or higher.

Subsequently, as shown in FIG. 8E, an active layer 35b and a second conductivity type semiconductor layer 35c are sequentially grown on the surfaces of the plurality of nano cores 35a'.

Through this process, the nano light-emitting structure 35 is composed of a first conductivity type semiconductor nano core 35a', an active layer 35b surrounding the nano core 35a', and a second conductivity type semiconductor layer 35b. It may have a core-shell structure including a shell layer.

The nano-core 35a' includes an upper end having a crystal plane different from its side surface, and as described above, the active layer formed on the upper end and the portion (II) of the second conductivity type semiconductor layer are formed on the side surfaces of the active layer and the second It may have a composition and/or thickness different from that of the portion (I) of the conductive type semiconductor layer. In order to solve the problem of leakage current and emission wavelength caused by this, the current blocking intermediate layer 34 is disposed on the upper end of the nano core 35a'. Due to the selective arrangement of the current blocking intermediate layer 34, the active layer region formed on the upper end of the nano core 35a ′ while ensuring the flow of current normally through the active layer region formed on the side of the nano core 35a ′. The flow of current through the current may be blocked by the current blocking intermediate layer 34.

Accordingly, it is possible to improve efficiency by suppressing leakage current concentrated on the upper end of the nano core 35a', and to accurately design a desired emission wavelength.

The mask employed in the above-described embodiment has exemplified a form composed of two material layers, but the present invention is not limited thereto, and may be implemented in a form employing three or more material layers.

For example, in the case of a mask having first to third material layers sequentially formed from the base layer, the second material layer is an etch stop layer and is made of a material different from the first and third material layers. If necessary, the first and third material layers may be made of the same material.

In the etching condition of the third material layer, at least the second material layer has an etch rate lower than that of the third material layer, and thus may function as an etch stop layer. At least the first material layer is a material having electrical insulating properties, and if necessary, the second or third material layer may also be an insulating material.

12A to 12D are cross-sectional views for each main process illustrating a process of forming a nano light emitting structure using the mask 43 shown in FIG. 10A.

As shown in FIG. 12A, a nano core 45a may be grown on the base layer 42 using the mask 43. The base layer 42 may be formed on the substrate 41. The mask 43 has an opening having a width that becomes narrower downward. The nano core 45a may be grown in a shape corresponding to the shape of the opening.

In order to further improve the crystal quality of the nano core 45a, one or more heat treatment processes may be introduced during growth. In particular, by rearranging the top surface of the nano core 45a into a crystal plane of a hexagonal pyramid during growth, a more stable crystal structure can be obtained, and high quality of crystals to be grown afterwards can be ensured.

This heat treatment process may be performed under the temperature conditions described above. For example, it may be performed under a temperature condition that is the same as or similar to the growth temperature of the nano core 45a for convenience of processing. In addition, it may be performed in a manner in which a metal source such as TMGa is stopped while maintaining a pressure/temperature equal to or similar to the growth pressure and temperature of the nano core 45a in an NH ₃ atmosphere. This heat treatment process may last for several seconds to tens of minutes (eg, 5 seconds to 30 minutes), but a sufficient effect can be obtained even with a duration of about 10 seconds to about 60 seconds.

In this way, the heat treatment process introduced in the process of growing the nano core 45a can prevent the deterioration of crystallinity caused when the nano core 45a is grown at a high speed, so that the crystal quality can be improved with fast crystal growth. I can plan.

The time and frequency of the heat treatment process section for stabilization may be variously changed according to the height and diameter of the final nano core. For example, if the width of the opening is 300 to 400 nm and the height (mask thickness) of the opening is about 2.0 μm, a stabilization time of about 10 seconds to about 60 seconds is inserted at the midpoint of about 1.0 μm to provide desired high quality. Can grow its core. Of course, this stabilization process may be omitted depending on the core growth conditions.

Subsequently, as shown in FIG. 12B, a current blocking intermediate layer 44 may be formed on the upper end of the nano core 45a.

After forming the nano-core 45a to a desired height, a current blocking intermediate layer 44 may be formed on the upper surface of the nano-core 45a while leaving the mask 43 as it is. As described above, by using the mask 43 as it is, the current blocking intermediate layer 44 can be easily formed in a desired region (top surface) of the nano core 45a without a separate mask forming process.

The current blocking intermediate layer 44 may be a semiconductor layer that is not intentionally doped or doped with a second conductivity type impurity opposite to the nano core 45a. For example, when the nanocore 45a is n-type GaN, the current blocking intermediate layer 44 may be undoped GaN or GaN doped with p-type impurity Mg. In this case, the nanocore 45a and the current blocking intermediate layer 44 can be continuously formed by switching only the types of impurities in the same growth process. For example, if Si doping is stopped under the same conditions as the growth of n-type GaN nanocores, and Mg is injected and grown for about 1 minute, the current blocking intermediate layer 44 having a thickness of about 200 nm to about 300 nm is formed. The current blocking intermediate layer 44 can effectively block a leakage current of several ㎂ or more. As described above, in the mold method process as in the present embodiment, the introduction process of the current blocking intermediate layer 44 can be simplified.

Subsequently, as shown in FIG. 12C, the mask 43 is removed up to the first material layer 43a as the etch stop layer so that the side surfaces of the plurality of nano cores 45a are exposed.

In the present embodiment, by applying an etching process in which the second material layer 43b can be selectively removed, only the second material layer 43b may be removed and the first material layer 43a may remain. . The remaining first material layer 43a may prevent the active layer and the second conductive type semiconductor layer from being connected to the base layer 42 in a subsequent growth process.

As in the present embodiment, in the manufacturing process of the nano light-emitting structure using the mask having an opening as a mold, an additional heat treatment process may be introduced to improve crystallinity.

After removing the second material layer 43b of the mask, the surface of the nanocore 45a may be heat-treated under certain conditions to convert the unstable crystal plane of the nanocore 45a into a stable crystal plane (see FIGS. 11A and 11B. ). In particular, as in this embodiment, since the nano core 45a is grown in an opening having an inclined sidewall, it has a shape having an inclined sidewall corresponding to the shape, but as shown in FIG. 12D, after the heat treatment process The nano-core 45a' may have a substantially uniform diameter (or width) due to regrowth with rearrangement of crystals. In addition, the upper end of the nanocore 45a immediately after growth may also have an incomplete hexagonal pyrimide shape, but the nanocore 45a' after the heat treatment process may be changed into a hexagonal pyramid shape having a uniform surface. As described above, after removing the mask, the nanocore having an uneven width may be regrown (and rearranged) into a hexagonal pyramidal column structure having a uniform width through a heat treatment process.

As described above, the nano light-emitting structure obtained by the present process can provide a desired nano-structure semiconductor light-emitting device through the process of forming a light-transmitting protective layer in FIGS. 5C to 5E, but is not limited thereto, and disclosed in other embodiments. As described above, various light-transmitting protective layers in which a low refractive index layer/high refractive index layer are combined may be provided. In particular, the embodiments shown in Figs. 13, 14 and 18 are illustrated as including a current blocking intermediate layer 54 which is a high resistance element similar to the structure obtained in this process.

13 is a cross-sectional view of a nanostructure semiconductor light emitting device according to an embodiment of the present invention.

The nanostructure semiconductor light emitting device 50 shown in FIG. 13 includes a substrate 51 having a convex pattern R, a base layer 52 formed on the substrate 51 and made of a first conductivity type semiconductor material, and It may include a plurality of nano light emitting structures 55 disposed thereon.

The substrate 51 may be an insulating, conductive, or semiconductor substrate. For example, the substrate 51 may be sapphire, SiC, Si, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , or GaN. The base layer 52 may provide a growth surface of the nano light emitting structure 55. The base layer 52 may be an n-type nitride semiconductor satisfying Al _x In _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1).

The nano core 55a may be formed in the area of the base layer 52 exposed by the opening H of the insulating layer 53. For example, the insulating layer 53 may be an insulating material such as SiO ₂ or SiN _x . The nano light emitting structure 55 has a nano core 55a made of a first conductivity type semiconductor, an active layer 55b sequentially formed on the surface of the nano core 55a, and a second conductivity type semiconductor layer 55c. I can.

The nanostructured semiconductor light emitting device 50 may include a contact electrode 56 connected to the second conductivity type semiconductor layer 55c. The contact electrode 56 employed in this embodiment may be made of a transparent conductive material.

The light-transmitting protective layer 57 may include a low refractive index layer 57a having a first refractive index and a high refractive index layer 57b having a second refractive index greater than the first refractive index. The low refractive index layer 57a may be filled in the space between the plurality of nano light emitting structures 55, and the high refractive index layer 57b may be located on the plurality of nano light emitting structures 55.

In this embodiment, the contact electrode 56 may be disposed on the side of the nano light-emitting structure 55 so that the upper end T of the nano light-emitting structure 55 is exposed. In this structure, the high refractive index layer 57b may directly contact the upper end portion T of the nano light emitting structure 55 without the contact electrode 56. This process may be performed by applying an etch back process for selective removal after forming the contact electrode 56.

If necessary, after forming the low refractive index layer 57a, the level of the low refractive index layer 57b can be adjusted together with the selective removal process of the contact electrode 56. In this case, the contact electrode 56 may be formed to have substantially the same height as the level of the low refractive index layer 57a.

By the arrangement of the low-refractive-index layer 57a and the high-refractive-index layer 57b described above, light progression in the lateral direction of the nano light-emitting structure 55 can be suppressed and light can be effectively extracted in the upper direction. Effective luminous efficiency in the upper direction can be greatly improved.

In this embodiment. The nano core 55a includes an upper end portion T having a crystal plane different from a surface of another region. Unlike the side surface of the nano-core 55a, the upper end T of the nano-core 55a may have an inclined crystal surface.

As shown in FIG. 13, a current blocking intermediate layer 54 may be formed on the surface of the upper end (T) of the nano core 55a. The current blocking intermediate layer 54 may be positioned between the active layer 55b and the nano core 55a.

The current blocking intermediate layer 54 may be made of a material having high electrical resistance so as to block a leakage current that may be caused in the upper portion T of the nano core 55a. For example, the current blocking intermediate layer 54 may be a semiconductor layer that is not intentionally doped or is doped with a second conductivity type impurity opposite to the nano core 55a. For example, when the nanocore 55a is n-type GaN, the current blocking intermediate layer 54 may be undoped GaN or GaN doped with p-type impurities such as Mg. The current blocking intermediate layer 54 is not particularly distinguished from other layers around it, and may be a high-resistance region made of the same material (eg, GaN) and implemented by a difference in doping concentration or doping material. For example, while supplying n-type impurities, GaN is grown to form a nano core 55a, and the growth of GaN continues without interruption, blocking the supply of n-type impurities or supplying p-type impurities such as Mg to The current blocking intermediate layer 54 may be formed. Of course, while growing GaN, which is a nano core, another composition of Al _x In _y Ga _1-xy N (0≤x<1, 0≤y<1, 0≤x+y) is supplied by additionally supplying sources of Al and/or In. A current blocking intermediate layer made of <1) may also be formed.

When formed as a semiconductor layer, the current blocking intermediate layer 54 may have a thickness of about 50 nm or more for sufficient electrical resistance. The second conductivity type impurity of the current blocking intermediate layer 54 may be about 1.0×10 ¹⁶ /cm 3 or more. In the case of the current blocking intermediate layer 54 doped with the second conductivity type impurity, the thickness and concentration may be appropriately complementary. For example, when the thickness is thin, resistance can be secured by increasing the doping concentration, and vice versa.

In this embodiment, the flow of current through the active layer region formed on the upper end portion T of the nano core 55a may be blocked by the current blocking intermediate layer 54. Accordingly, it is possible to effectively block the occurrence of leakage current generated at the top of the nano core 55a.

The nanostructure semiconductor light emitting device 50' shown in FIG. 14 has a structure similar to that of the nanostructure semiconductor light emitting device shown in FIG. 13, and elements denoted by the same reference numerals may be understood with reference to the description of FIG. However, the nanostructured semiconductor light emitting device 50 ′ has a region in which a contact electrode 56 ′ is formed different from the shape shown in FIG. 13.

As shown in FIG. 14, the contact electrode 56 ′ may not be located in the upper region of the side surface of the nano light emitting structure 55. An upper region of the side surface of the nano light emitting structure 55 in which the contact electrode 56 ′ is not located may contact the light-transmitting protective layer 57 ′.

Also, as in the present embodiment, the low refractive index layer 57 ′ may be formed at a level similar to the height of the contact electrode 56 ′. The high refractive index layer 57b' may be positioned in a region T'of the side surface of the nano light emitting structure 55 where the contact electrode 56' is not formed. In this region T', since most of the light traveling to the high refractive index layer 57b' can proceed without interference from the contact electrode 56', the light extraction efficiency can be further improved.

15 is a cross-sectional view of a nanostructured semiconductor light emitting device according to an embodiment of the present invention. Unless there is a description to the contrary, descriptions related to the preceding embodiments may be combined with the description of this embodiment.

The nanostructure semiconductor light emitting device 60 shown in FIG. 15 includes a substrate 61 having a convex pattern R, a base layer 62 formed on the substrate 61 and made of a first conductivity type semiconductor material, and It may include a plurality of nano light-emitting structures 65 disposed thereon.

The substrate 61 may be an insulating, conductive, or semiconductor substrate. The base layer 62 may provide a growth surface of the nano light emitting structure 65. The base layer 62 may be an n-type nitride semiconductor. The nano core 65a may be formed in the area of the base layer 62 exposed by the opening of the insulating layer 63.

The nano light emitting structure 65 has a nano core 65a made of a first conductivity type semiconductor, an active layer 65b sequentially formed on the surface of the nano core 65a, and a second conductivity type semiconductor layer 65c. I can.

The light-transmitting protective layer 67 may include a low refractive index layer 67a having a first refractive index and a high refractive index layer 67c having a second refractive index greater than the first refractive index. In this embodiment, the light-transmitting protective layer 67 may further include an intermediate refractive index layer 67b between the low refractive index layer 67a and the high refractive index layer 67c. The intermediate refractive index layer 67b may have a refractive index higher than a first refractive index and smaller than a second refractive index. The low refractive index layer 67a may be filled in the space between the plurality of nano light emitting structures 65. The low refractive index layer 67a employed in this embodiment may have a lower level than the previous embodiment. The intermediate refractive index layer 67b employed in this embodiment is illustrated as a single layer structure, but may be formed of a plurality of intermediate refractive index layers, and each intermediate refractive index layer may have a different refractive index. For example, the plurality of intermediate refractive index layers may be disposed such that the refractive index increases from the bottom to the top.

The contact electrode 66 may be disposed on an upper surface of the low refractive index layer 67a and a surface of the nano light emitting structure 65 that is higher than the upper surface of the low refractive index layer 67a. In this case, a part of the intermediate refractive index layer 67b may be filled between the nano light emitting structures 65 to have an interface in contact with the contact electrode 66. Unlike the present embodiment, when the intermediate refractive index layer 67b is not employed, a part of the high refractive index layer 67c is filled between the nano light-emitting structures 65 to be in contact with the contact electrode 66. Can have

The high refractive index layer 67c is formed on the intermediate refractive index layer 67b and may cover the plurality of nano light emitting structures 65.

16 is a cross-sectional view of a nanostructured semiconductor light emitting device according to an embodiment of the present invention. Unless there is a description to the contrary, descriptions related to the preceding embodiments may be combined with the description of this embodiment.

The nanostructure semiconductor light emitting device 60' shown in FIG. 16 is the light emitting device shown in FIG. 15 except that the contact electrode 66' is formed so that the upper end T of the nano light emitting structure 65 is exposed. It has a structure similar to 60).

That is, in this embodiment, the contact electrode 66 ′ may be disposed on the side of the nano light-emitting structure 65 so that the upper end T of the nano light-emitting structure 65 is exposed. In this structure, the high refractive index layer 67c may directly contact the upper end portion T of the nano light emitting structure 65 without the contact electrode 66. A description of such a process can be understood by referring to the corresponding part described in FIG. 12.

17 is a cross-sectional view of a nanostructured semiconductor light emitting device according to an embodiment of the present invention. Unless there is a description to the contrary, descriptions related to the preceding embodiments may be combined with the description of this embodiment.

The nanostructure semiconductor light emitting device 70 shown in FIG. 17 has a structure in which the upper end T of the nano light emitting structure 75 is flat. .

That is, the upper end portion T of the nano light emitting structure 75 has a flat top surface. This structure can be obtained by sequentially forming an active layer 75b and a second conductivity type semiconductor layer 75c after applying a planarization process to the upper end portion T of the nano core 75a after growth of the nano core 75a. . As such, the shape and crystal plane of the nano light-emitting structure 75 may have various other shapes and crystal planes.

18 is a cross-sectional view of a nanostructure semiconductor light emitting device according to an embodiment of the present invention. Unless there is a description to the contrary, descriptions related to the preceding embodiments may be combined with the description of this embodiment.

The nanostructured semiconductor light emitting device 50" shown in FIG. 18 is the light emitting device 50 shown in FIG. 13, except that it has an uneven structure P as a light extraction pattern on the upper surface of the high refractive index layer 57b". ) Has a similar structure.

The high refractive index layer 57b" may have a light extraction pattern made of a non-flat surface in order to improve light extraction efficiency to the outside. This light extraction pattern is made of a regular or irregular irregular structure (P). The uneven structure P may be formed as a separate layer (which may have a different refractive index), and may be formed by processing the surface of the high refractive index layer 57b", as in the present embodiment. . In this case, the uneven structure P may be understood to have a structure integrated with the high refractive index layer 57b".

19 and 20 show an example of a package employing the above-described semiconductor light emitting device.

The semiconductor light emitting device package 500 illustrated in FIG. 19 may be a nanostructured semiconductor light emitting device 10, a package body 502, and a pair of lead frames 503 illustrated in FIG. 1.

The nanostructured semiconductor light emitting device 10 may be mounted on the lead frame 503 so that each electrode may be electrically connected to the lead frame 503. If necessary, the nanostructured semiconductor light emitting device 10 may be mounted in a region other than the lead frame 503, for example, in the package body 502. In addition, the package body 502 may have a cup shape to improve light reflection efficiency, and the reflective cup includes an encapsulant made of a light-transmitting material to encapsulate the nanostructure semiconductor light emitting device 10 and the wire W. 505) can be formed.

The semiconductor light emitting device package 600 illustrated in FIG. 20 may include a nanostructured semiconductor light emitting device 10, a mounting substrate 610, and an encapsulant 603 illustrated in FIG. 1.

The nanostructured semiconductor light emitting device 10 may be mounted on a mounting substrate 610 and electrically connected to the mounting substrate 610 through a wire W.

The mounting substrate 610 may include a substrate body 611, an upper electrode 613 and a lower electrode 614, and a through electrode 612 connecting the upper electrode 613 and the lower electrode 614. The mounting substrate 610 may be provided as a substrate such as a PCB, MCPCB, MPCB, or FPCB, and the structure of the mounting substrate 610 may be applied in various forms.

The encapsulant 603 may be formed in a dome-shaped lens structure having a convex top surface, but according to an embodiment, the direction of light emitted through the top surface of the encapsulant 603 is formed by forming the surface into a convex or concave lens structure. It is possible to adjust the angle. If necessary, a wavelength conversion material such as a phosphor or a quantum dot may be disposed on the surface of the encapsulant 603 or the nanostructured semiconductor light emitting device 10.

The nanostructure semiconductor light emitting device according to the above-described embodiment and a package including the same can be advantageously applied to various application products.

The nanostructured semiconductor light emitting device according to the above-described embodiment may be employed as a light source for various applications. 21 to 24 illustrate various application products in which a nanostructured semiconductor light emitting device can be employed.

21 and 22 show examples of a backlight unit employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.

Referring to FIG. 21, the backlight unit 1000 includes a light source 1001 mounted on a substrate 1002 and at least one optical sheet 1003 disposed thereon. The light source 1001 may use the above-described nanostructure semiconductor light emitting device or a package including the nanostructure semiconductor light emitting device.

In the backlight unit 1000 shown in FIG. 21, the light source 1001 emits light toward an upper portion on which the liquid crystal display device is disposed, whereas the backlight unit 2000 of the other example shown in FIG. 22 is a substrate 2002. The light source 2001 mounted thereon emits light in the lateral direction, and the emitted light is incident on the light guide plate 2003 to be converted into a surface light source. Light passing through the light guide plate 2003 is emitted upward, and a reflective layer 2004 may be disposed on the lower surface of the light guide plate 2003 in order to improve light extraction efficiency.

23 is an exploded perspective view showing an example of a lighting device employing a nanostructured semiconductor light emitting device according to an embodiment of the present invention.

The lighting device 3000 shown in FIG. 23 is shown as a bulb type lamp as an example, and includes a light emitting module 3003, a driving part 3008, and an external connection part 3010.

In addition, external structures such as external and internal housings 3006 and 3009 and a cover part 3007 may be additionally included. The light emitting module 3003 may include a light source 3001 which may be the above-described nanostructure semiconductor light emitting device or a package including the nanostructure semiconductor light emitting device and a circuit board 3002 on which the light source 3001 is mounted. . For example, the first and second electrodes of the nanostructure semiconductor light emitting device may be electrically connected to the electrode pattern of the circuit board 3002. In the present embodiment, one light source 3001 is illustrated as being mounted on the circuit board 3002, but a plurality of light sources 3001 may be mounted as necessary.

The outer housing 3006 may act as a heat dissipation unit, and includes a heat dissipation plate 3004 that directly contacts the light emitting module 3003 to improve a heat dissipation effect, and a heat dissipation fin 3005 surrounding the side of the lighting device 3000. I can. The cover part 3007 is mounted on the light emitting module 3003 and may have a convex lens shape. The driving unit 3008 may be mounted on the inner housing 3009 and connected to an external connection unit 3010 such as a socket structure to receive power from an external power source.

Further, the driving unit 3008 serves to convert and provide an appropriate current source capable of driving the semiconductor light emitting device 3001 of the light emitting module 3003. For example, the driving unit 3008 may be composed of an AC-DC converter or a rectifying circuit component.

24 shows an example in which a nanostructure semiconductor light emitting device according to an embodiment of the present invention is applied to a head lamp.

Referring to FIG. 24, a headlamp 4000 used as a vehicle light, etc. includes a light source 4001, a reflective part 4005, and a lens cover part 4004, and the lens cover part 4004 is a hollow guide. It may include 4003 and a lens 4002. The light source 4001 may include the above-described nanostructure semiconductor light emitting device or a package including the nanostructure semiconductor light emitting device.

The head lamp 4000 may further include a heat dissipation unit 4012 that discharges heat generated from the light source 4001 to the outside, and the heat dissipation unit 4012 includes a heat sink 4010 and a cooling fan so that effective heat dissipation is performed. (4011) may be included. In addition, the headlamp 4000 may further include a housing 4009 that fixes and supports the heat dissipation part 4012 and the reflective part 4005. The housing 4009 may include a central hole 4008 for mounting the heat dissipation unit 4012 on one surface thereof.

The housing 4009 may include a front hole 4007 that is integrally connected to the one surface and fixed to the other surface bent in a right angle direction so that the reflective part 4005 is positioned on the upper side of the light source 4001. Accordingly, the front side is opened by the reflecting unit 4005, and the reflecting unit 4005 is fixed to the housing 4009 so that the opened front corresponds to the front hole 4007 to reflect light reflected through the reflecting unit 4005. It may pass through the front hole 4007 and be emitted to the outside.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical spirit of the present invention. It will be obvious to those who have the knowledge of.

Claims (20)

A plurality of nano light emitting structures each having a nanocore made of a first conductivity type semiconductor, an active layer sequentially positioned on the surface of the nanocore, and a second conductivity type semiconductor layer;
A contact electrode disposed on the surface of the second conductive semiconductor layer of the plurality of nano light emitting structures and made of a transparent conductive material;
A low refractive index layer filled in the space between the plurality of nano light emitting structures and having a first refractive index; And
A nanostructured semiconductor light emitting device comprising a high refractive index layer disposed on the low refractive index layer to cover the plurality of nano light emitting structures and having a second refractive index greater than the first refractive index.
The method of claim 1,
The nanostructure semiconductor light emitting device, characterized in that the low refractive index layer has a level lower than the height of the nano light emitting structure.
The method of claim 2,
Part of the high refractive index layer is a nanostructure semiconductor light emitting device, characterized in that the interface is filled between the nano light-emitting structure and in contact with the low refractive index layer.
The method of claim 2,
The contact electrode is a nanostructure semiconductor light emitting device, characterized in that disposed on the upper surface of the low refractive index layer and a surface of the nano light emitting structure higher than the upper surface of the low refractive index layer.
The method of claim 4,
Part of the high refractive index layer is a nanostructure semiconductor light emitting device, characterized in that it has an interface in contact with the contact electrode by filling between the nano light emitting structure.
The method of claim 5,
The nano-structured semiconductor light-emitting device, wherein the nano light-emitting structure includes a main portion having a side surface that is a first crystal plane and an upper end portion having a surface that is a second crystal surface different from the first crystal surface.
The method of claim 6,
The nanostructure semiconductor light emitting device, characterized in that the interface is located at a point of 50% or more from the height of the main portion of the nano light emitting structure.
The method of claim 6,
The first crystal plane is an m plane, and the second crystal plane is a nanostructure semiconductor light emitting device, characterized in that the r plane.
The method of claim 6,
Part of the high refractive index layer is filled between the nano light emitting structures to have an interface with the low refractive index layer,
The interface is a nanostructure semiconductor light emitting device, characterized in that located on the side of the nano light emitting structure.
The method of claim 9,
The contact electrode is a nanostructure semiconductor light emitting device, wherein the contact electrode is disposed on the side of the nano light emitting structure to expose the upper end of the nano light emitting structure.
The method of claim 10,
The contact electrode is a nanostructure semiconductor light emitting device, characterized in that formed to have the same height as the level of the low refractive index layer.
The method of claim 1,
The first refractive index is 1.5 or less, and the second refractive index is 1.7 or more.
The method of claim 1,
The first refractive index is less than the refractive index of the nano light emitting structure,
Nanostructure semiconductor light emitting device, characterized in that the difference between the first refractive index and the second refractive index is 0.2 or more.
The method of claim 1,
A nanostructure semiconductor light emitting device further comprising at least one intermediate refractive index layer disposed between the low refractive index layer and the high refractive index layer and having a refractive index between the first and second refractive indexes.
The method of claim 1,
Nanostructure semiconductor light emitting device, characterized in that the light extraction pattern is disposed on the upper surface of the high refractive index layer.
The method of claim 15,
The light extraction pattern is a nanostructure semiconductor light emitting device, characterized in that the uneven structure integrated with the high refractive index layer.
A plurality of nano light emitting structures;
A contact electrode disposed on the surface of the plurality of nano light-emitting structures and made of a transparent conductive material; And
A low refractive index layer filled in the space between the plurality of nano light emitting structures and having a first refractive index, and a high refractive index layer disposed on the plurality of nano light emitting structures and having a second refractive index greater than the first refractive index. A nanostructured semiconductor light emitting device including a light-transmitting protection unit provided.
The method of claim 17,
The low refractive index layer has a level lower than the height of the nano light emitting structure,
A nanostructure semiconductor light emitting device, characterized in that a part of the high refractive index layer is filled between the nano light emitting structures to have an interface with the low refractive index layer.
The method of claim 17,
The first refractive index is a nanostructure semiconductor light emitting device, characterized in that less than the refractive index of the nano light emitting structure.
A light emitting module including the nanostructured semiconductor light emitting device according to any one of claims 1 to 19;
A driving unit configured to drive the light emitting module; And
A lighting device comprising an external connection unit configured to supply an external voltage to the driving unit.

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