KR102152090B1 - Test system for soc and test method thereof - Google Patents

Abstract

Disclosed are a system on chip (SoC) test system to universally test homogenous or heterogeneous SoCs and a test method thereof. According to one embodiment of the present invention, the SoC test system comprises: a mast test platform mounted on a master motherboard and including a master instrument board and a master controller; and a slave test platform mounted on a slave motherboard prepared in parallel to the master motherboard and including a slave instrument board equal to or different from the master instruction board and a slave controller. Moreover, an SoC test method comprises: a synchronous clock signal transmission step, a synchronization complete signal transmission step, and a universal SoC test step.

Description

System-on-chip (SoC) test system and its test method {TEST SYSTEM FOR SOC AND TEST METHOD THEREOF}

The present invention relates to a test system, and more particularly, to a system-on-chip (SoC) test system capable of universally testing the same or heterogeneous system-on-chip (SoC) and a test method thereof.

As the current system-on-chip (SoC) technology advances, it is becoming increasingly important in the system-on-chip (SoC) field to reduce test cost by universalizing tests between various types of system-on-chip (SoC).

A system on chip (SoC) refers to a device in which a product and system that can be fully driven on a single chip is embedded, and includes a memory and a processor that controls and processes digital and analog signals. System on Chip (SoC) is the crystallization of IT core technology in which system technology and semiconductor technology are fused.

Types of system-on-chip (SoC) include a power management integrated circuit (PMIC), an application processor (AP), a display driver integrated circuit (DDI), a power IC, and a cmos image sensor (CIS).

In order to secure electrical reliability, in order to verify various electrical and physical characteristics, each system-on-chip (SoC) test process is performed to test for system-on-chip (SoC) defects. In testing System on Chip (SoC), different unique test platforms are required depending on the target System on Chip (SoC).

1 is a diagram showing a conventional system on a chip (SoC) test system. As shown in FIG. 1, a conventional system-on-chip (SoC) test system is provided on test platforms 10a, 10b, and 10c, and motherboards 11a, 11b, and 11c, which are provided in accordance with system-on-chip (SoC) specifications. Built-in and specialized instrument boards (12a, 12b, 12c) to test according to each system-on-chip (SoC) specification, and each system-on-chip such as AP, DDI, and CIS that can be tested by specializing in each test platform (SoC) (30a, 30b, 30c) may be included.

Conventional system-on-chip (SoC) test systems are not compatible with each other to test different system-on-chip (SoC), so separate test platforms and related facilities are installed. in need.

Such a conventional system-on-chip (SoC) test system can secure high productivity when mass-producing system-on-chip (SoC) having the same characteristics in a large amount for a short period, but it is difficult to quickly respond to improvements or modifications in use. Although the test system itself supports some channel expansion, the number of slots is limited, and the size of the test heads 40a, 40b, and 40c is fixed, so the channels that can be expanded/changed are also limited. The conventional system-on-chip (SoC) test system allows limited testing of some of the functions of the system-on-chip (SoC). However, there is a problem that test efficiency is degraded, such as requiring a separate process for testing other characteristic values. there was.

In addition, there is a problem of increasing the test cost because a new test platform must be introduced for a separate characteristic value test.

Korean Patent Publication No. 10-0684548 relates to a system-on-chip capable of performing a function test by adding a circuit, and a system-on-chip capable of universally testing the same or heterogeneous system-on-chip (SoC). There is no disclosure of a chip (SoC) test system.

Korean Registered Gazette No. 10-0684548 (Announcement date: 2007.02.20.)

One technical problem to be solved by the present invention is to provide a system-on-chip (SoC) test system capable of universally testing the same or heterogeneous system-on-chip (SoC) and a test method thereof.

In order to solve the above technical problem, the present invention provides a system on a chip (SoC) test system.

A system-on-chip (SoC) test system according to an embodiment of the present invention is a system-on-chip (SoC) test system for universally testing a system-on-chip (SoC), and is mounted on a master motherboard. A master test platform having a master instrument board and a master controller; And a slave test platform mounted on a slave motherboard provided in parallel with the master motherboard and having a slave instrument board and a slave controller equal to or different from the master instrument board, wherein the master controller generates a synchronization clock signal It is transmitted to the slave test platform, and the slave controller may receive the synchronization clock signal to synchronize a test environment between the master test platform and the slave test platform, and transmit a synchronization completion signal to the master test platform.

According to an embodiment, the master controller generates a pattern start signal and transmits it to the slave test platform, and the slave test platform receiving the pattern start signal simultaneously operates the system on a chip (SoC) with the master test platform. You can test it.

According to an embodiment, when the test of the system-on-chip (SoC) is terminated, the master controller may generate a pattern end signal and transmit it to the slave test platform.

According to an embodiment, the master controller generates a trigger signal and transmits it to the slave test platform, and the slave test platform receiving the trigger signal is an analog of the system-on-chip (SoC) at the same time as the master test platform. You can measure the data.

According to an embodiment, the slave instrument board may be formed of the same instrument board as the master instrument board to support parallel testing between two or more system-on-chip (SoC).

According to an embodiment, the system on a chip (SoC) may have the same specifications.

In addition, in order to solve the above technical problem, the present invention provides a system-on-chip (SoC) test method.

A system-on-chip (SoC) test method according to an embodiment of the present invention includes: a synchronization clock signal transmitting step of generating a synchronization clock signal in a master test platform and transmitting the synchronization clock signal to a slave test platform; A synchronization completion signal transmitting step of generating a synchronization completion signal in the slave test platform in which the master test platform and the test environment are synchronized by the received synchronization clock signal and transmitting the synchronization completion signal to the master test platform; And a system on which generates a pattern start signal from the master test platform and transmits the pattern start signal to the slave test platform, thereby universally testing the System on Chip (SoC) on the slave test platform simultaneously with the master test platform. It may include a chip general test step.

According to an embodiment, when the system-on-chip (SoC) test result is generated in the system-on-chip universal test step, the master test platform generates a pattern end signal and transmits the pattern end signal to the slave test platform. It may further include transmitting a pattern end signal for terminating the test of the master test platform and the slave test platform.

A system-on-chip (SoC) test method according to another embodiment of the present invention includes: a synchronization clock signal transmitting step of generating a synchronization clock signal in a master test platform and transmitting the synchronization clock signal to a slave test platform; A synchronization completion signal transmitting step of generating a synchronization completion signal in the slave test platform in which the master test platform and the test environment are synchronized and transmitting the synchronization completion signal to the master test platform; And transmitting the trigger signal of the master test platform to the slave test platform, and measuring analog data of the system-on-chip (SoC) at the same time in the master test platform and the slave test platform by the trigger signal. Can include.

According to an embodiment of the present invention, by a master controller that generates a synchronization clock signal capable of synchronizing the test environment between the master test platform and the slave test platform. It has the advantage of being able to respond flexibly by testing new performance characteristics according to development such as improvement.

According to another embodiment of the present invention, by providing a master controller that generates and transmits a synchronous clock signal, it is possible to selectively combine only parts necessary for testing a specific system-on-chip (SoC) between the master test platform and the slave test platform. It has the advantage of being able to freely expand the test environment between heterogeneous materials.

According to another embodiment of the present invention, by combining and expanding a plurality of slave test platforms to a master test platform by means of a synchronization clock signal, a pattern start signal, and a trigger signal, the same or different systems can be turned on without adding new facilities. There is an advantage of being able to test a chip (SoC) universally and build a test environment that can meet diversifying customer requirements.

According to another embodiment of the present invention, by combining a plurality of slave test platforms to a master test platform by means of a synchronization clock signal, a pattern start signal, and a trigger signal, there is an advantage of reducing the time and cost required for developing a separate test system. .

1 is a diagram showing a conventional system on a chip (SoC) test system.
2 is a diagram illustrating a system-on-chip (SoC) test system according to an embodiment of the present invention.
3 is a diagram illustrating a system on a chip (SoC) test system for simultaneously testing two or more of the same SoCs according to an embodiment of the present invention.
4 is a diagram illustrating a slave test platform in which a master test platform and a test environment are synchronized according to an embodiment of the present invention.
5 is a flow chart illustrating a system-on-chip (SoC) test method according to an embodiment of the present invention.
6 is a flowchart illustrating a method of testing a system on a chip (SoC) according to an embodiment of the present invention.
7(a) and 7(b) are graphs showing deviations between expected and measured values of a system-on-chip (SoC) test system and a system-on-chip (SoC) test system according to an embodiment of the present invention. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical idea of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

In the present specification, when a component is referred to as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed therebetween. In addition, in the drawings, the shape and size are exaggerated for effective description of technical content.

Further, in various embodiments of the present specification, terms such as first, second, and third are used to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one component from another component. Therefore, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. In addition, in the present specification,'and/or' is used to mean including at least one of the elements listed before and after.

In the specification, expressions in the singular include plural expressions unless the context clearly indicates otherwise. In addition, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, elements, or a combination of the features described in the specification, and one or more other features, numbers, steps, and configurations It is not to be understood as excluding the possibility of the presence or addition of elements or combinations thereof. In addition, in the present specification, "connection" is used to include both indirectly connecting a plurality of constituent elements and direct connecting.

Further, in the following description of the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

2 is a diagram showing a system-on-chip (SoC) test system according to an embodiment of the present invention, and FIG. 3 is a system-on-chip (SoC) test for simultaneously testing two or more of the same SoCs according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a system, and FIG. 4 is a diagram illustrating a slave test platform in which a master test platform and a test environment are synchronized according to an embodiment of the present invention.

2 to 4, a system-on-chip (SoC) test system according to an embodiment of the present invention may include a master test platform 100 and a slave test platform 200. A tester head 400 may be further included.

The system-on-chip (SoC) test system may provide a test solution capable of meeting diversifying customer requirements by combining and expanding a plurality of slave test platforms 200 to the master test platform 100.

Master Test Platform(100)

The plurality of master test platforms 100 may be mounted on the master motherboard 110. The master test platform 100 may have a master instrument board 120 and a master controller 130. The master test platform 100 may include a slave test platform 200 to be described later and a facility that operates different functions according to a target system on a chip (SoC).

The system-on-chip (SoC) may be detachably mounted and detached from the master test platform 100. The system-on-chip (SoC) may be physically and electrically connected to the master test platform 100 and the slave test platform 200 by connecting members such as connectors, cables, probes, and sockets. One or the same system-on-chip (SoC) can be tested by one SoC test system.

The master instrument board 120 may test an operation of a system on a chip (SoC) mounted on the master test platform 100 or measure analog data on a system on a chip (SoC). The master instrument board 120 may be any one of a digital board capable of testing the operation of a system on a chip (SoC) or measuring analog data, a parametric measurement unit (PMU), and a device power supply (DPS).

The master controller 130 may activate the master instrument board 120 and the slave instrument board 220 required to test the system-on-chip (SoC) by calling in performance characteristic information of the system-on-chip (SoC). In addition, the master controller 130 may control the synchronization of a test environment of a system-on-chip (SoC) between the master test platform 100 and the slave test platform 200. The master controller 130 may selectively call and operate at least one or more of the master instrument board 120 and the slave instrument board 130. The master controller 130 selectively combines the master instrument board 120 and the slave instrument board 220 required for testing a specific system-on-chip (SoC) between the master test platform 100 and the slave test platform 200. Can be operated.

The master controller 130 may generate a synchronizing clock signal (SCL) and transmit a synchronization clock signal SCL to the slave test platform 200.

The master controller 130 may simultaneously test a system-on-chip (SoC) in the master test platform 100 and the slave test platform 200 or control analog data measurement of the system-on-chip (SoC).

In order to test the system-on-chip (SoC), the master controller 130 may generate a pattern start signal (PS) and transmit a pattern start signal PS to the slave test platform 200. . The master controller 130 may generate a pattern end signal (PE) when the test of the system-on-chip (SoC) is finished, and transmit the pattern end signal PE to the slave test platform 200. have.

The test result for the system-on-chip (SoC) may be shared by the master test system 100 and the slave test system 200 by the pattern start signal PS and the pattern end signal PE.

The slave test platform 200 may increase the accuracy and reliability of test result information with the master test platform 100 by sharing the pattern start signal PS and the pattern end signal PE by the master controller 130.

In order to measure analog data of a system on a chip (SoC), the master controller 130 may generate a trigger signal (TR) and transmit a trigger signal TR to the slave test platform 200. . Analog data is used to determine whether the system-on-chip (SoC) operates normally, such as the operating characteristics of the system-on-chip (SoC), such as the driving voltage, frequency, and current of the system-on-chip (SoC), or power consumption in a specific software It can be data that can be.

As shown in FIG. 4, the synchronization clock signal SCL may be synchronized to the slave test platform 200 at the same size and time ta as the value input to the master test platform 100. The master test platform 100 and the slave test platform 200 may share test start and end signals with each other by the synchronization clock signal SCL. Similarly, test or analog data of a system-on-chip (SoC) between the master test platform 100 and the slave test platform 200, which are separated by a pattern start signal (PS), a pattern end signal (PE), and a trigger signal (TR). The measurement environment can be compatible.

The synchronization clock signal SCL and the synchronization finish signal SF may be prerequisites for testing the system on a chip (SoC) or measuring analog data. That is, the pattern start signal PS and the trigger signal TR may be dependent on the synchronization clock signal SCL and the synchronization completion signal SF.

Since the trigger signal TR acts independently from the pattern start signal PS, the system-on-chip (SoC) test and analog data measurement are independently operated according to the master instrument board 120 and the slave instrument board 220. Can be performed independently from

Slave Test platform(200)

Among the contents of the slave test platform 200, contents overlapping with the master test platform 100 will be omitted below.

In the SoC test system that tests the AP operation at 100MHz and 200MHz, it is assumed that the master instrument board 120 can test under the 100MHz condition and the master test platform 100 cannot test under the 100MHz condition. . At this time, a slave test platform 200 including a slave instrument board 220 for testing at 200 MHz is provided in parallel on the master test platform 100 to test a system on a chip (SoC) under conditions of 100 MHz and 200 MHz.

The system-on-chip (SoC) tested in the slave test platform 200 may be the same as the system-on-chip (SoC) tested in the master test platform 100, and may have different specifications, and a heterogeneous system with different functions. It may be a test platform for testing on-chip (SoC).

At least one slave test platform 200 may be provided in accordance with a test operation of a system-on-chip (SoC). In the case of FIG. 2, the case of two slave test platforms 200 is illustrated.

The slave test platform 200 may be mounted on the slave motherboard 210. The slave test platform 200 may have a slave instrument board 220 and a slave controller 230. The slave test platform 200 may test a system-on-chip (SoC) simultaneously with the master test platform 100 by interlocking with the received pattern start signal PS. In addition, the slave test platform 200 may measure analog data of a system-on-chip (SoC) simultaneously with the master test platform 100 by interlocking with the received trigger signal TR.

The slave motherboard 210 may be provided in parallel with the master motherboard 110.

The slave instrument board 220 may be composed of instrument boards that are the same as or different from the master instrument board 120. The slave instrument board 220 according to an exemplary embodiment may be formed of the same instrument board as the master instrument board 120 to support parallel testing between two or more system-on-chip (SoC). In this case, a plurality of system-on-chip (SoC) that are tested in parallel may have the same specifications.

In FIG. 3, the AP is described as an example of a system on a chip (SoC). As shown in FIG. 3, AP1 and AP2 can be simultaneously tested on the slave test platform 200 in which the master test platform 100 is synchronized. In this case, AP1 and AP2 may be connected to the master test platform 100 and the slave test platform 200 by a connection member.

The slave controller 230 may receive a synchronization clock signal SCL. In addition, the slave controller 230 may transmit a synchronization completion signal SF to the master test platform 100.

The slave test platform 200 is interlocked with a synchronization clock signal SCL so that the master test platform 100 and the test environment are synchronized with each other, and transmits a synchronization completion signal SF to the master test platform 100 to determine the synchronization state. You can give feedback.

The operation method of the System on Chip (SoC) test system is as follows.

5 is a flow chart showing a system-on-chip (SoC) test method according to an embodiment of the present invention, and FIG. 6 is a flow chart showing a system-on-chip (SoC) test method according to an embodiment of the present invention.

In the system-on-chip (SoC) test method according to an embodiment of the present invention, a master test platform and a slave test platform are synchronized with each other to simultaneously test a system-on-chip (SoC) or simultaneously test analog data of a system-on-chip (SoC). Can be measured.

Referring to FIG. 5, a system on chip (SoC) test method for testing a system on chip (SoC) includes a synchronization clock signal transmission step (S10), a synchronization completion signal transmission step (S20), and a pattern start signal transmission step (S31). ), a system-on-chip general-purpose test step (S32). In addition, a pattern end signal transmission step (S33) may be further included.

In the synchronization clock signal transmission step S10, the master test platform 100 generates a synchronization clock signal SCL and transmits the synchronization clock signal SCL to the slave test platform 200.

In the synchronization completion signal transmission step S20, the test environment between the slave test platform 200 and the master test platform 100 may be synchronized by the received synchronization clock signal SCL. In addition, the synchronization completion signal SF may be generated from the synchronized slave test platform 200 and transmitted to the master test platform 100.

In the pattern start signal transmission step (S31), the master test platform 100 may generate the pattern start signal PS and transmit it to the slave test platform 200.

In the system-on-chip universal test step (S32), the system-on-chip (SoC) may be universally tested in the slave test platform 200 at the same time as the master test platform 100.

In the pattern start signal transmission step (S33), when the test result of the system-on-chip (SoC) is generated, the pattern end signal PE is generated by the master test platform 100 to transmit the pattern end signal PE to the slave test platform 200. ) To terminate the test of the master test platform 100 and the slave test platform 200.

Referring to FIG. 6, a system-on-chip (SoC) test method for measuring analog data of a system-on-chip (SoC) includes a synchronization clock signal transmission step (S10), a synchronization completion signal transmission step (S20), and a trigger signal transmission step. (S41), analog data measurement step (S42) may be included.

Since the synchronization clock signal SCL and the synchronization completion signal SF are the same as the system-on-chip (SoC) testing method for testing the system-on-chip (SoC), a description thereof will be omitted.

In the trigger signal transmission step S41, a trigger signal TR may be generated by the master test platform 100 and transmitted to the slave test platform 200.

In the analog data measurement step S42, the slave test platform 200 may measure analog data of the system-on-chip (SoC) at the same time as the master test platform 100.

Hereinafter, the system-on-chip (SoC) of the present invention according to the difference in the error rate of the measured value based on the expected value between the system-on-chip (SoC) test system according to an embodiment of the present invention and the conventional system-on-chip (SoC) test system. Let's look at the performance characteristics of the test system.

7(a) and 7(b) are graphs showing deviations between expected and measured values of a system-on-chip (SoC) test system and a system-on-chip (SoC) test system according to an embodiment of the present invention. .

In FIG. 7(a), different test platforms are arbitrarily combined in a conventional system-on-chip (SoC) test system, and accordingly, a deviation between an expected value and a measured value between current flowing through the system-on-chip (SoC) is shown. The expected value, measured value, and error rate of current are shown in Table 1 below. Each data is a current value, and the unit is amperes (A).

No Expected value (A) Measured value (A) Error rate (%) One -0.1 -0.0535 -46.5 2 -0.05 -0.0319 -36.2 3 0 0.00152 0 4 0.05 0.0315 -37 5 0.1 0.0928 -7.2 6 0.15 0.1549 3.267 7 0.2 0.2163 8.15 8 0.256 0.256 0

7(b) shows a deviation between an expected value and a measured value of a current flowing through a system on a chip (SoC) in a system-on-chip (SoC) test system synchronized and coupled between different test platforms according to an embodiment of the present invention. Show The expected value, measured value, and error rate of current are shown in Table 2 below.

No Expected value (A) Measured value (A) Error rate (%) One -0.1 -0.0.997 -0.3 2 -0.05 -0.04993 -0.14 3 0 0.00075 0 4 0.05 0.04997 -0.06 5 0.1 0.09983 -0.17 6 0.15 0.1499 -0.067 7 0.2 0.1995 -0.25 8 0.256 0.2559 -0.039

As shown in Figs. 7(a), 7(b), and Tables 1 and 2, in the case of the conventional system-on-chip (SoC) test system, an error rate of up to 46.5% is shown, and the measured value is less than the expected value. You can see that it came out.

In contrast, it can be seen that the system-on-chip (SoC) test system according to an embodiment of the present invention has a maximum error rate of 0.3% or less, so that the reliability of the measured value based on the expected value is high. That is, in the case of the system-on-chip (SoC) test system of the present invention, it is possible to improve the accuracy of measurement data.

In the above, although the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to specific embodiments, and should be interpreted by the appended claims. In addition, those who have acquired ordinary knowledge in this technical field should understand that many modifications and variations can be made without departing from the scope of the present invention.

100: master test platform 110: master motherboard
120: master instrument board 130: master controller
200: slave test platform 210: slave motherboard
220: slave instrument board 230: slave controller
300: system on chip
SCL: Synchronization clock signal PS: Pattern start signal
PE: Pattern end signal
TR: trigger signal
SF: Synchronization complete signal

Claims (9)

In a system-on-chip (SoC) test system for universally testing system-on-chip (SoC),
Mounted on the master motherboard. A master test platform having a master instrument board and a master controller; And
A slave test platform configured to perform different functions from the master test platform, mounted on a slave motherboard arranged parallel to the master motherboard, and having a slave instrument board and a slave controller that are the same as or different from the master instrument board. Including,
The master controller,
Generate a synchronization clock signal and transmit it to the slave test platform,
The slave controller,
Receive the synchronization clock signal to synchronize a test environment between the master test platform and the slave test platform, and transmit a synchronization completion signal to the master test platform,
A system-on-chip (SoC) test system capable of testing different system-on-chips (SoCs) of the same or different types by combining and extending at least one of the slave test platforms to the master test platform.
The method of claim 1,
The master controller,
Generate a pattern start signal and transmit it to the slave test platform,
A system-on-chip (SoC) test system, wherein the slave test platform, which has received the pattern start signal, tests the system-on-chip simultaneously with the master test platform.
The method of claim 1,
The master controller,
When the test of the system-on-chip is finished, a pattern end signal is generated and transmitted to the slave test platform, a system-on-chip (SoC) test system.
The method of claim 1,
The master controller,
Generate a trigger signal and transmit it to the slave test platform,
The slave test platform receiving the trigger signal measures analog data of the system-on-chip at the same time as the master test platform, a system-on-chip (SoC) test system.
The method of claim 1,
The slave instrument board,
A system-on-chip (SoC) test system comprising the same instrument board as the master instrument board to support parallel testing between two or more of the system-on-chips.
The method of claim 5,
The system-on-chips have the same specifications, a system-on-chip (SoC) test system.
A synchronization clock signal transmission step of generating a synchronization clock signal in a master test platform and transmitting the synchronization clock signal to a slave test platform;
A synchronization completion signal transmitting step of generating a synchronization completion signal in the slave test platform in which the master test platform and the test environment are synchronized by the received synchronization clock signal and transmitting the synchronization completion signal to the master test platform; And
A system-on-chip general-purpose system that generates a pattern start signal from the master test platform and transmits the pattern start signal to the slave test platform to test a system-on-chip (SoC) in the slave test platform simultaneously with the master test platform. Includes the enemy testing phase,
The slave test platform is provided with at least one, and in order to universally test the system-on-chip (SoC) of the same or different types, a system-on-chip (SoC) capable of testing different characteristic values from the master test platform Test method.
The method of claim 7,
When the system-on-chip test result is generated in the system-on-chip universal test step, the master test platform generates a pattern end signal and transmits the pattern end signal to the slave test platform, so that the master test platform and the slave test platform A system on a chip (SoC) test method further comprising the step of transmitting a pattern end signal to terminate the test of.
A synchronization clock signal transmission step of generating a synchronization clock signal in a master test platform and transmitting the synchronization clock signal to a slave test platform;
A synchronization completion signal transmitting step of generating a synchronization completion signal in the slave test platform in which the master test platform and the test environment are synchronized and transmitting the synchronization completion signal to the master test platform; And
An analog data measurement step of transmitting a trigger signal of the master test platform to the slave test platform, and measuring analog data of a system-on-chip simultaneously in the master test platform and the slave test platform by the trigger signal,
The slave test platform is provided with at least one, and in order to universally test the system-on-chip (SoC) of the same type or different types, it is possible to test different characteristic values from the master test platform, a system-on-chip (SoC) Test method.

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