KR102157547B1 - Shift register - Google Patents

Abstract

The present invention discloses a shift register. The shift register of the disclosed invention includes a node control unit including an inverting unit for controlling a voltage of a reset node according to a voltage of a set node, and outputs a scan pulse based on at least one voltage of the set node and the reset node. A plurality of stages including an output unit; An inverter voltage controller configured to control a high potential inverter voltage supplied to each inverting unit of the plurality of stages based on a voltage of at least one reset node provided in at least one stage; And a voltage divider that supplies first and second base voltages to the inverter voltage control unit, generates a preset reference voltage using the first and second base voltages, and supplies it to the inverter voltage control unit. Includes wealth.

Description

Shift register {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly, to a shift register capable of generating a stable output by preventing fluctuations in an inverter voltage supplied to the shift register.

A typical liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal display panel in which pixel regions are arranged in a matrix form and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in a region defined by vertically crossing the gate lines and data lines. Further, pixel electrodes and common electrodes for applying an electric field to each of the pixel regions are formed on the liquid crystal display panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) as a switching device.

The thin film transistor is turned on by a scan pulse applied to the gate electrode via the gate line, so that the data signal of the data line is charged to the pixel voltage.

On the other hand, the driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller that supplies control signals for controlling the gate driver and data driver, and various types of liquid crystal display devices. It has a power supply for supplying the driving voltages of the branches.

The gate driver sequentially drives the liquid crystal cells on the liquid crystal display panel line by line by sequentially supplying scan pulses to the gate lines. Here, the gate driver includes a shift register to sequentially output the above-described scan pulses.

This shift register includes a plurality of stages formed of a plurality of switching elements.

Each stage of the shift resistor operates by receiving a charging voltage, a discharging voltage, a high-potential inverter voltage, and a low-potential inverter voltage. In particular, the high-potential inverter voltage turns on the pull-down transistor of the stage to prevent the stage. The dedicated voltage is being output.

However, when the high potential inverter voltage supplied to the stage fluctuates, there is a problem that different voltages are output from the stage.

The present invention was conceived to solve the above problems, and prevents malfunction by supplying a stable high potential inverter voltage to each stage according to a monitoring voltage (Vm) corresponding to the degree of deterioration of the pull-down switching device disposed on the stage. Its purpose is to provide a shift register.

The shift register of the present invention for solving the problems of the prior art as described above includes a node controller including an inverting unit for controlling the voltage of the reset node according to the voltage of the set node, and at least one of the set node and the reset node. Includes a plurality of stages including an output unit that outputs a scan pulse based on one voltage, and is supplied to each inverting unit of the plurality of stages based on a voltage of at least one reset node provided in at least one stage. An inverter voltage control unit for controlling a high potential inverter voltage, supplying first and second base voltages to the inverter voltage control unit, and generating a preset reference voltage using the first and second base voltages, and the inverter By including a power supply unit with a voltage divider supplied to the voltage control unit, a stable high-potential inverter voltage is supplied to each stage according to the monitoring voltage (Vm) corresponding to the degree of deterioration of the pull-down switching device disposed on the stage, thereby preventing malfunction There is a prevented effect.

The shift register according to the present invention has an effect of preventing malfunction by supplying a stable high potential inverter voltage to each stage according to a monitoring voltage Vm corresponding to a degree of deterioration of a pull-down switching device disposed on a stage.

In addition, the shift register according to the present invention has the effect of reducing the size of the device by using the power terminals of the first and second base voltages VB1 and VB2 for the reference voltage Vref supplied to the inverter voltage control unit.

1 is a diagram showing a shift register according to the present invention.
FIG. 2 is a diagram illustrating a timing diagram of various signals supplied or output to each stage of FIG. 1.
3 is a diagram showing the configuration of a stage according to an embodiment of the present invention.
4 is a diagram showing a specific configuration of the inverter voltage control unit of FIG. 3.
5 is a diagram illustrating a connection structure of an inverter voltage control unit and a power supply unit of FIG. 3.
6 is a view showing another configuration of the monitoring switching device (Tm) provided in the voltage monitoring unit of FIG.
7 is a diagram showing a specific configuration of the stage of the present invention.
8A to 8C are diagrams showing high potential inverter voltages respectively output from the conventional inverter voltage control unit and the inverter voltage control unit according to the present invention.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms different from each other, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have it, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When'include','have','consists of' and the like mentioned in the present specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of two parts is described as'upper','upper of','lower of','next to','right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example,'after','following','after','before', etc. It may also include cases that are not continuous unless' is used.

First, second, etc. are used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be a second component within the technical idea of the present invention.

Each of the features of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments can be implemented independently of each other or can be implemented together in a related relationship. May be.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. The same reference numbers throughout the specification denote the same elements.

1 is a diagram illustrating a shift register according to the present invention, and FIG. 2 is a diagram illustrating a timing diagram of various signals supplied or output to each stage of FIG. 1.

As shown in FIG. 1, the shift register according to the embodiment of the present invention includes a plurality of stages STn-2 to STn+2. Here, each stage outputs one scan pulse (SPn-2 to SPn+2) for one frame period through each output terminal SOT.

Each of the stages STn-2 to STn+2 drives a gate line connected to itself by using a scan pulse and controls an operation of a stage located at a later stage from itself. On the other hand, depending on the circuit configuration in the stage, each stage may further control the operation of the stage located at its front end (dotted arrow in FIG. 1).

Stages sequentially output scan pulses starting with the stage assigned the fast number. That is, the first stage ST1 outputs the first scan pulse SP1, then the second stage ST2 outputs the second scan pulse SP2, and then the third stage ST3 is 3 The scan pulse (SP3) is output, .... Next, the ath stage outputs the ath scan pulse. Here, a is a natural number greater than or equal to 4.

On the other hand, although not shown in the drawing, the shift register further includes a+1th stage for outputting a scan pulse for resetting the ath stage, and the a+1th stage is a reset which is not connected to the gate line. It is a dummy stage for control. That is, the scan pulses from this reset control dummy stage are not supplied to the gate line.

Such shift registers may be built into the liquid crystal display panel. That is, the liquid crystal display panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and such a shift register is incorporated in the non-display portion.

Each stage of the shift resistor configured as described above receives a charging voltage, a discharge voltage, a high-potential inverter voltage, and a low-potential inverter voltage. In addition, each stage receives at least one of the first to fourth clock pulses CLK1 to CLK4 circulating with a sequential phase difference from each other.

Meanwhile, among these stages, the first stage ST1 further receives the start pulse Vst.

Charging voltage, discharging voltage, high potential inverter voltage, and low potential inverter voltage are all DC voltages. Among these, the charging voltage and the high potential inverter voltage exhibit positive polarity, while the discharge voltage and low potential inverter voltage exhibit negative polarity. Meanwhile, the discharge voltage and the low-potential inverter voltage may be ground.

The first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are output while circulating. That is, after sequentially outputting from the first clock pulse CLK1 to the fourth clock pulse CLK4, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output again. Accordingly, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2. Here, the fourth clock pulse CLK4 and the start pulse Vst may be synchronized with each other to be output.

In this way, when the fourth clock pulse CLK4 and the start pulse Vst are synchronized with each other, the fourth clock pulse CLK4 among the first to fourth clock pulses CLK1 to CLK4 is first output.

Also, the first to fourth clock pulses CLK1 to CLK4 are output such that pulse widths between adjacent clock pulses overlap each other. For example, as shown in FIG. 2, the first half of the pulse width of the second clock pulse CLK2 overlaps with the latter half of the pulse width of the first clock pulse CLK1, In addition, the second half of the pulse width of the second clock pulse CLK2 overlaps with the first half of the pulse width of the third clock pulse CLK3.

In this way, since the pulse widths of the first to fourth clock pulses CLK1 to CLK4 are overlapped, the scan pulses generated based on them are also overlapped with those adjacent to each other as shown in FIG. 2. Is output.

The first to fourth clock pulses CLK1 to CLK4 are used to generate scan pulses of each stage, and each stage receives one of the first to fourth clock pulses CLK1 to CLK4, and It generates a scan pulse using the supplied clock pulse.

For example, the 4k+1 stage charges the set node using the fourth clock pulse CLK4 and outputs the scan pulse using the first clock pulse CLK1, and the 4k+2 stage is the first clock pulse. The set node is charged using a pulse (CLK1) and a scan pulse is output using the second clock pulse (CLK2), and the 4k+3 stage charges the set node using the second clock pulse (CLK2) and The scan pulse is output using the 3 clock pulse CLK3, and the 4k+4 stage charges the set node using the third clock pulse CLK3 and generates the scan pulse using the fourth clock pulse CLK4. Print. Here, k represents a natural number.

In the present invention, an example in which four types of clock pulses having different phase differences are used, but any number of these clock pulses can be used as long as two or more types of clock pulses are used.

Each of the clock pulses CLK1 to CLK4 is output multiple times during one frame period, but the start pulse Vst is outputted only once during one frame period. In other words, each of the clock pulses CLK1 to CLK4 periodically indicates an active state (high state) several times during one frame period, but the start pulse Vst indicates only one active state during one frame period.

In order for each stage to output a scan pulse, a set operation of each stage must be preceded. When the stage is set, it means that the stage is in a state capable of outputting, that is, a state capable of outputting a clock pulse supplied to itself as a scan pulse. To this end, each stage is set by receiving a scan pulse from a stage located at the front end from itself. That is, the nth stage STn is set in response to the scan pulse from the n-pth stage. Here, n is a natural number and p is a natural number less than n.

For example, the nth stage STn is set in response to the scan pulse SPn-1 from the n-1th stage STn-1. However, since a stage does not exist immediately before the first stage located at the uppermost side, this first stage is set in response to a clock pulse and a start pulse Vst from the timing controller.

In addition, each stage is reset by receiving a scan pulse from a stage located at a rear end from itself. When the stage is reset, it means that the stage is in a state in which output is impossible, that is, a clock pulse supplied to itself cannot be output as a scan pulse.

For example, the nth stage STn is reset in response to a scan pulse from the n+qth stage. Here, q is a natural number and may be 2. Meanwhile, q and p may be set to the same number.

On the other hand, since there is no stage at the rear end of the above-described dummy stage for reset control, the a+1th stage is disabled in response to a clock pulse or a start pulse Vst from the timing controller.

The configuration of each stage in the shift register configured as described above will be described in more detail as follows.

FIG. 3 is a diagram showing a configuration of a stage according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a configuration of any one stage in FIG. 1 and an inverter voltage control unit connected thereto.

One n-th stage STn includes a node control unit NC and an output unit OU, as shown in FIG. 3.

The node control unit NC provided in the n-th stage STn is based on at least one of a scan pulse from a front stage and a scan pulse from a rear stage, based on the voltage of the set node Q and the reset node Qb. Control the state.

The node control unit NC has an inversion unit INV therein, and the inversion unit INV controls the voltage of the reset node Qb according to the voltage applied to the set node Q. That is, this inverting part INV makes the voltage of the reset node Qb low (discharged state) when the voltage of the set node Q is in a high state (charging state), and the voltage of the set node Q In this low state, the voltage of the reset node Qb is made high.

At this time, in making the voltage of the reset node Qb high or low, the inverting unit INV converts the high potential inverter voltage VDD_IT supplied to itself through the high potential inverter line IHL. The voltage of the reset node Qb is made high by using the voltage of the reset node Qb, and the voltage of the reset node Qb is made using the low-potential inverter voltage VSS_IT supplied to itself through the low-potential inverter line ILL. To low state.

The high potential inverter line IHL and the low potential inverter line ILL are commonly connected to all stages. Accordingly, when the size of the high potential inverter voltage VDD_IT transmitted to the high potential inverter line IHL is adjusted, all of the high potential inverter voltage VDD_IT supplied to all stages is changed. Likewise, when the level of the low-potential inverter voltage VSS_IT transmitted to the low-potential inverter line ILL is adjusted, all the low-potential inverter voltages VSS_IT supplied to all stages are changed.

The output unit OU provided in the n-th stage STn outputs the scan pulse SPn based on the voltage of at least one of the set node Q and the reset node Qb. Specifically, when the set node Q is in a charged state and the reset node Qb is in a discharged state, the output unit OU transmits a high-state clock pulse (for example, CLK2) supplied to the scan pulse ( For example, it outputs as SPn). On the other hand, this output unit OU outputs the first discharge voltage VSS1 when the set node Q is in a discharge state and the reset node Qb is in a charged state. Here, the scan pulse SPn and the first discharge voltage VSS1 are output through the output terminal OT of the corresponding stage (for example, STn).

To this end, the output unit OU may include a pull-up switching element Tu and a pull-down switching element Td therein.

The pull-up switching device Tu provided in the output unit OU of the n-th stage STn is controlled according to the voltage of the set node Q, and a second clock transmission line for transmitting the second clock pulse CLK2 ( It is connected between CTL2) and output terminal (OT). The pull-up switching device Us is turned on or off according to the voltage of the set node Q, and transmits the second clock pulse CLK2 to the output terminal OT when turned on.

The pull-down switching device Td is controlled according to the voltage of the reset node Qb, and is connected between the output terminal OT and the first discharge power line VSL1 transmitting the first discharge voltage VSS. . That is, the pull-down switching device Td is turned on or off according to the voltage of the reset node Qb, and transmits the first discharge voltage VSS1 to the output terminal OT when turned on.

All stages may have the same configuration as the nth stage STn as shown in FIG. 3.

Meanwhile, the inverter voltage control unit 300 receives the first and second base voltages VB1 and VB2 and the reference voltage Vref from the power supply unit 400, and is connected to at least one of all of these stages to provide a pull-down switching device. Determine the degree of deterioration of (Td) (or, if there are other switching devices connected to the reset node (Qb) through the gate electrode, such switching devices), and the high potential inverter voltage (VDD_IT) based on the determination result. Adjust the size. For example, as the driving time of the shift register increases, the degree of deterioration of the pull-down switching device (Td) also increases, and the inverter voltage control unit 300 increases the deterioration of the pull-down switching device (Td). The magnitude of the inverter voltage VDD_IT is further increased.

The inverter voltage control unit 300 determines the degree of deterioration of the pull-down switching device Td based on the voltage of at least one reset node Qb. 3 shows an example in which the inverter voltage control unit 300 is connected to any one stage, that is, the reset node Qb of the n-th stage STn, but this connection configuration is not limited thereto.

That is, the inverter voltage control unit 300 according to the present invention may be connected to, for example, two or more reset nodes Qb provided in each of two or more different stages.

Meanwhile, the inverter voltage control unit 300 and the power supply unit 400 may be installed inside any one stage.

In addition, the power supply unit 400 adjusts the size of the high potential inverter voltage VDD_IT based on the output of the voltage monitoring unit and a voltage monitoring unit that detects the degree of deterioration of the pull-down switching element Td in the inverter voltage control unit 300 The voltage is supplied to the voltage regulating part.

In particular, in the present invention, a voltage divider composed of resistors is disposed between the first and second base voltages VB1 and VB2 supplied to the voltage sensing unit of the inverter voltage control unit 300, The reference voltage (Vref) can be generated.

The configuration of the inverter voltage control unit 300 and the configuration of the power supply unit 400 will be described in detail as follows.

FIG. 4 is a diagram showing a detailed configuration of the inverter voltage control unit of FIG. 3, and FIG. 5 is a diagram illustrating a connection structure of the inverter voltage control unit and power supply unit of FIG.

Referring to FIGS. 4 and 5 together with FIG. 3, the inverter voltage control unit 300 includes a voltage monitoring unit 311a and a voltage adjusting unit 311b, as shown in FIG. 4.

The voltage monitoring unit 311a adjusts the size of the monitoring voltage Vm according to the size of the voltage applied to the reset node Qb provided in any one stage (for example, STn), and the adjusted monitoring The voltage (Vm) is output to the monitoring input line (MTL).

To this end, the voltage monitoring unit 311a includes a monitoring switching element Tm and a variable resistor Rv, as shown in FIG. 4. As the variable resistor Rv, a fixed resistor having a specific fixed resistance value may be used.

The monitoring switching device (Tm) is controlled according to the voltage of the reset node (Qb) provided in any one stage (for example, STn), and the monitoring input line (MTL) to which the monitoring voltage (Vm) is input and the It is connected between the first base power line VBL1 for transmitting the first base voltage VB1 from the power supply unit 400. This monitoring switching element Tm is used as an index for grasping the degree of deterioration of the switching elements (eg, pull-down switching elements) connected to the reset node Qb through a gate electrode. That is, the degree of deterioration of the monitoring switching element Tm means the degree of deterioration of the switching elements (eg, pull-down switching elements) connected to the reset node Qb through the gate electrode.

The variable resistor R is connected between the monitoring input line MTL and the second base power line VBL2 for transmitting the second base voltage VB2 from the power supply 400.

The voltage controller 311b adjusts the size of the high potential inverter voltage VDD_IT based on the preset reference voltage Vref and the monitoring voltage Vm applied to the monitoring input line MTL, and adjusts the adjusted high potential. The inverter voltage VDD_IT is supplied to the inverting unit INV.

The voltage controller 311b compares the monitoring voltage Vm from the monitoring input line MTL and the reference voltage Vref, as shown in FIG. 4, and based on the comparison result, the high potential inverter voltage It includes a comparator (CMP) that adjusts the size of (VDD_IT) and supplies the adjusted high potential inverter voltage (VDD_IT) to the inverting unit (INV).

Here, the high potential inverter voltage VDD_IT output from the comparator CMP is supplied to the inverting unit INV through the high potential inverter line IHL.

Meanwhile, according to FIG. 4, the reference voltage Vref is input to the non-inverting terminal (+) of the comparator CMP, and the monitoring voltage Vm is input to the inverting terminal (-) of the comparator CMP. Conversely, it is also possible to input the reference voltage (Vref) to the inverting terminal (-) and the monitoring voltage (Vm) to the non-inverting terminal (+).

The reference voltage (Vref) is a DC voltage whose value is fixed, and the monitoring voltage (Vm) changes according to the voltage level of the reset node (Qb), and the comparator (CMP) is the monitoring voltage (Vm) input to itself. The output, that is, the high potential inverter voltage (VDD_IT) is adjusted so that) equals the reference voltage (Vref). Accordingly, the voltage of the high-potential inverter voltage VDD_IT also changes according to the magnitude of the monitoring voltage Vm.

The above-described high potential inverter voltage VDD_IT may be defined by Equation 1 below.

[Equation 1]

VDD_IT = f(VQb, Vref, VB2, VB1)

That is, according to Equation 1 above, the high potential inverter voltage VDD_IT is the voltage VQb of the reset node Qb, the reference voltage Vref, the second base voltage VB2, and the first base voltage VB2. ) Is defined as a function whose value is determined.

Here, as the comparator CMP, an operational amplifier having a high gain may be used. When such an operational amplifier is used as its comparator (CMP), the above-described monitoring voltage (Vm) and the second base voltage (VB2) become almost the same, and the monitoring voltage (Vm) and the reference voltage (Vref) are almost the same. The high-potential inverter voltage VDD_IT and the voltage VQb of the reset node Qb are set to be set.

The voltage adjusting unit 311b configured as described above adjusts the value of the high-potential inverter voltage VDD_IT so that the resistance of the monitoring switching element Tm can be kept constant.

At this time, the current flowing through the monitoring switching element Tm is determined by the second base voltage VB2, the reference voltage Vref, the first base voltage VB1, and the voltage VQb of the reset node Qb. , The voltage controller 311b adjusts the value of the high potential inverter voltage VDD_IT applied to the reset node Qb so that the current value is substantially constant.

In addition, the reference voltage Vref input to the non-inverting terminal (+) of the voltage control unit 311b is between the first base voltage (VB1) terminal and the second base voltage (VB2) terminal of the power supply unit 400 It is withdrawn from and supplied from the voltage dividers R1 and R2 arranged in

As shown in FIG. 5, the power supply unit 400 includes a power terminal for generating a first base voltage VB1 and a power terminal for generating a second base voltage VB2, respectively.

In the present invention, the reference voltage Vref supplied to the voltage controller 311b is not provided with a separate power terminal, and is between the power terminal of the first base voltage VB1 and the power terminal of the second base voltage VB2. A voltage divider in which the first resistor R1 and the second resistor R2 are connected in series is arranged to generate the reference voltage Vref.

For example, when the magnitude of the first base voltage VB1 is -7 (V) and the magnitude of the second base voltage VB2 is -5 (V), the first and second resistors R1 of the voltage divider By setting the values of ,R2) to 10K (Ohm), the magnitude of the reference voltage Vref at the reference voltage output terminal F may generate -6 (V).

Therefore, the shift register of the present invention does not generate the reference voltage supplied to the inverter voltage control unit as a separate reference voltage power source, but generates the first and second base voltages VB1 and VB2 in a voltage distribution method to reduce the device size. It can have an effect.

In addition, in the present invention, the first capacitor C1 is disposed between the output terminal T of the comparator CMP of the voltage control unit 311b and the monitoring input line TML, and the reference voltage ( A second capacitor C2 is disposed at the non-inverting input terminal (+) to which Vref) is input.

That is, the non-inverting input terminal (+) of the comparator CMP is connected to the reference voltage output terminal F drawn from the voltage divider of the power supply unit 400.

The reference voltage Vref is input to the non-inverting input terminal (+) of the comparator CMP of the voltage control unit 311b, and the monitoring voltage Vm is input to the inverting input terminal (-) of the comparator CMP, Outputs high potential inverter voltage (VDD_IT).

However, when the reference voltage (Vref) input to the non-inverting input terminal (+) of the comparator (CMP) is a negative (-) voltage, the monitoring voltage (Vm) input to the inverting input terminal (-) of the comparator (CMP) First of all, when the reference voltage (Vref) is input to the non-inverting input terminal (+), the high potential inverter voltage (VDD_IT) is a negative (-) voltage for a certain period until the monitoring voltage (Vm) is normally input to the inverting input terminal (-). Is displayed.

That is, before voltage amplification for the difference between the reference voltage (Vref) input to the non-inverting input terminal (+) of the comparator (CMP) and the monitoring voltage (Vm) input to the inverting input terminal (-) is performed, the non-inverting input terminal (+) ), a voltage amplification is performed for the difference between the reference voltage (Vref) of) and the arbitrary voltage input to the inverting input terminal (-), so that there is a problem that a malfunction output occurs in the initial stage.

In the present invention, when the reference voltage Vref input to the non-inverting input terminal (+) of the comparator (CMP) is a negative (-) voltage, the second capacitor C2 connected to the non-inverting input terminal (+) of the comparator (CMP) And the non-inverting input terminal after the reference voltage Vref is input to the inverting input terminal (-) of the comparator (CMP) by the resistors R1 and R2 included in the voltage divider of the power supply unit 400. It was made to be entered in (+).

Therefore, in the present invention, the non-inverting input terminal (+) of the comparator (CMP) is less than the RC delay value by the first capacitor (C1) connected to the comparator (CMP) and the variable resistor (Rv) disposed in the voltage monitoring unit (311a). The RC delay value by the second capacitor C2 connected to and the first and second resistors R1 and R2 disposed in the voltage divider of the power supply is designed to be larger.

As described above, by adjusting the values of the variable resistor Rv, the first capacitor C1, the first and second resistors R1 and R2, and the second capacitor C2, the inverting input terminal of the comparator CMP Since the monitoring voltage (Vm) input as (-) is always faster than the reference voltage (Vref) input to the non-inverting input terminal (+), the high potential inverter voltage (VDD_IT) output from the voltage regulator 311b is always positive (+). ) It is output as a voltage to prevent malfunction of the stage.

However, although not described in the drawings, when the reference voltage Vref input to the non-inverting input terminal (+) of the voltage regulator 311b is a positive (+) value, the reference voltage Vref is higher than the monitoring voltage Vm. Since the input is required quickly, it is preferable that the RC delay values of the variable resistor Rv and the first capacitor C1 are set larger than the RC values of the first and second resistors R1 and R2 and the second capacitor C2.

As described above, the shift register according to the present invention has the effect of preventing malfunction by supplying a stable high potential inverter voltage to each stage according to the monitoring voltage Vm corresponding to the degree of deterioration of the pull-down switching device disposed on the stage. .

In addition, the shift register according to the present invention has the effect of reducing the size of the device by using the power terminals of the first and second base voltages VB1 and VB2 for the reference voltage Vref supplied to the inverter voltage control unit.

6 is a view showing another configuration of the monitoring switching device (Tm) provided in the voltage monitoring unit of FIG. 4.

6A, when two or more monitoring switching elements Tm1, Tm2, and Tm3 are provided, the gate electrodes of the two or more monitoring switching elements Tm1, Tm2 and Tm3 are It may be commonly connected to the reset node Qb provided in any one stage (for example, STn). At this time, the two or more monitoring switching elements Tm1, Tm2, and Tm3 are connected in parallel between the monitoring input line MTL and the first base power line VBL1.

As another method, as shown in (b) of FIG. 6, two or more monitoring switching elements Tm1, Tm2, and Tm3 are applied to the voltages of the reset nodes Qb1, Qb2 and Qb3 of each of the plurality of stages. Accordingly, it is individually controlled and may be connected in parallel between the monitoring input line MTL and the first base power line VBL1. For example, the gate electrode of the first monitoring switching element Tm1 is connected to the reset node Qb1 of the n-1th stage STn-1, and the gate electrode of the second monitoring switching element Tm2 is It is connected to the reset node Qb2 of the n-stage STn, and the gate electrode of the third monitoring switching element Tm3 may be connected to the reset node Qb3 of the n+1th stage STn+1. have.

7 is a diagram showing a specific configuration of the stage of the present invention.

7 illustrates a specific configuration of the n-th stage STn, and other stages may also have a structure as illustrated in FIG. 11.

The node controller NC of the n-th stage STn may further include first and second switching devices Tr1 and Tr2 in addition to the above-described inversion unit INV.

The first switching device Tr1 provided in the n-th stage STn is controlled according to a scan pulse (eg, SPn-1) from the previous stage, and a charging power line for transmitting a charging voltage VDD It is connected between (VDL) and the set node (Q). The first switching device Tr1 is turned on or off according to the scan pulse SPn-1 from the previous stage, and transmits the charging voltage VDD to the set node Q when turned on.

However, the operation of the first switching element Tr1 provided in the first stage that first outputs the scan pulse during one frame period is controlled by the start pulse Vst from the timing controller.

Meanwhile, the first switching device Tr1 provided in the n-th stage STn may receive the scan pulse SPn-1 from the previous stage instead of the charging voltage VDD.

In addition, the first switching device Tr1 provided in the first stage may receive a start pulse Vst instead of the charging voltage VDD.

The second switching device Tr2 provided in the n-th stage STn is controlled according to a scan pulse (eg, SPn+2) from a subsequent stage, and the set node Q and the second discharge voltage VSS2 It is connected between the second power discharge line (VSL2) for transmitting. The second switching device (Tr2) is turned on or off according to the scan pulse (SPn+2) from the rear stage, and transmits the second discharge voltage (VSS2) to the set node (Q) when turned on. do.

However, the operation of the second switching element Tr2 provided in the above-described dummy stages for reset control is controlled by the start pulse Vst from the timing controller.

8A to 8C are diagrams showing high potential inverter voltages respectively output from the conventional inverter voltage control unit and the inverter voltage control unit according to the present invention.

Hereinafter, it will be described together with FIGS. 4 and 5.

8A is a reference voltage Vref to the comparator CMP of the inverter voltage control unit 300 from an individual reference voltage Vref supply power terminal without arranging a voltage divider in the power supply unit 400 of FIGS. 4 and 5. This is the case that you entered.

As shown in the drawing, monitoring in which a reference voltage (Vref) having a negative (-) value input to the non-inverting input terminal (+) of the comparator (CMP) of the inverter voltage control unit 300 is input to the inverting input terminal (-) When the voltage is input faster than the voltage Vm, it can be seen that the high potential inverter voltage VDD is not immediately output at the initial time and a negative (-) voltage is output to the start pulse Vst region.

That is, the positive (+) high potential inverter voltage (VDD) is the target voltage, but after the negative (-) inverter voltage (VDD) is output for a period of 400 ms, the high potential inverter is the target voltage from this. It can be seen that the voltage VDD is output.

In this way, when the reference voltage Vref of the non-inverting input terminal (+) of the comparator CMP of the inverter voltage control unit 300 is input before the monitoring voltage Vm, the high potential inverter voltage VDD is negative ( -) It fluctuates severely from voltage to positive voltage (+), causing malfunction of the stage.

FIG. 8B is a case in which a voltage divider is disposed in the power supply unit 400 so that the reference voltage Vref generation terminal is not separately disposed, and the reference voltage is generated by voltage distribution of the first and second base voltages VB1 and VB2. to be.

That is, since the second capacitor C2 is not disposed at the non-inverting input terminal (+) of the comparator CMP disposed in the inverter voltage control unit 300, the reference voltage Vref is monitored in the comparator CMP as shown in FIG. 8A. It is input before the voltage (Vm).

Accordingly, as shown in the figure, it can be seen that after a negative (-) voltage is output for 20 ms in an initial section in which the high potential inverter voltage VDD is output, it then rises to the high potential inverter voltage VDD.

8A and 8B, when a negative (-) reference voltage (Vref) is input to the comparator (CMP) of the inverter voltage control unit 300, the monitoring voltage (Vm) input to the inverting input terminal (-) When the reference voltage Vref input to the non-inverting input terminal (+) is faster, the high potential inverter voltage VDD is generated when the voltage varies from negative (-) to positive (+) voltage.

8C is a voltage divider composed of first and second resistors R1 and R2 in the power supply unit 400, as described in the present invention, and a reference voltage at the non-inverting input terminal (+) of the comparator CMP. Vref) is a diagram showing characteristics of the high potential inverter voltage VDD when the second capacitor C2 is disposed to delay the input.

In the present invention, the first capacitor C1 disposed in the comparator CMP of the inverter voltage control unit 300 and the variable resistor Rv disposed in the inverting input terminal (-) of the comparator CMP to which the monitoring voltage Vm is input. By increasing the RC delay values of the first and second resistors R1 and R2 and the second capacitor C2 of the voltage divider than the RC delay values of, high potential inverter voltage VDD fluctuations were prevented.

In the experimental example, the first and second resistors R1 and R2 arranged in the voltage divider are set to 10K (Ohm), the second capacitor C2 is 11 (㎌), and the first capacitor C1 is 10 (㎋). ), the variable resistance (Rv) was set to 10K (Ohm).

As shown in the figure, it can be seen that the high-potential inverter voltage VDD output from the comparator CMP of the inverter voltage control unit immediately rises to the target voltage in the positive (+) direction without fluctuation to the negative (-) voltage. .

As described above, the shift register according to the present invention has the effect of preventing malfunction by supplying a stable high potential inverter voltage to each stage according to the monitoring voltage Vm corresponding to the degree of deterioration of the pull-down switching device disposed on the stage. .

In addition, the shift register according to the present invention has the effect of reducing the size of the device by using the power terminals of the first and second base voltages VB1 and VB2 for the reference voltage Vref supplied to the inverter voltage control unit.

STn: nth stage VDD_IT: high potential inverter voltage
VSS_IT: Low potential inverter voltage INV: Inverting part
Q: Set node Qb: Reset node
IHL: High potential inverter line ILL: Low potential inverter line
OT: output terminal NC: node control unit
OU: output CLK2: second clock pulse
CTL2: second clock transmission line Tu: pull-up switching device
Td: pull-down switching element SPn: nth scan pulse
C1: first capacitor C2: second capacitor
R1: first resistor R2: second resistor

Claims (9)

A plurality of stages including a node control unit including an inverting unit for controlling the voltage of the reset node according to the voltage of the set node, and an output unit for outputting a scan pulse based on at least one voltage of the set node and the reset node field;
An inverter voltage controller configured to control a high potential inverter voltage supplied to each inverting unit of the plurality of stages based on a voltage of at least one reset node provided in at least one stage; And,
Includes a power supply unit having a voltage divider supplying first and second base voltages to the inverter voltage control unit, generating a preset reference voltage using the first and second base voltages, and supplying to the inverter voltage control unit Shift register.
The method of claim 1,
The inverter voltage control unit,
A voltage monitoring unit that adjusts the level of the monitoring voltage according to the level of the voltage applied to the reset node provided in any one stage and outputs the adjusted monitoring voltage to the monitoring input line;
A shift register comprising a voltage controller configured to adjust the level of the high potential inverter voltage based on the preset reference voltage and the monitoring voltage applied to the monitoring input line, and supply the adjusted high potential inverter voltage to the inverting unit.
The method of claim 2,
The voltage monitoring unit,
At least one monitoring switching device controlled according to a voltage of a reset node provided in any one of the stages and connected between a monitoring input line to which the monitoring voltage is input and a first base power line that transmits a first base voltage ; And,
A shift register including a variable resistor connected between the monitoring input line and a second base power line for transmitting a second base voltage.
The method of claim 3,
The voltage controller compares the monitoring voltage from the monitoring input line with a preset reference voltage, adjusts the magnitude of the high potential inverter voltage based on the comparison result, and reverses the adjusted high potential inverter voltage. A shift register including a comparator supplied to the negative and a first capacitor connected between the comparator and the output terminal of the comparator and a monitoring input line.
The method of claim 4,
A shift resistor including a second capacitor connected to a non-inverting input terminal of a comparator to which the preset reference voltage is input.
The method of claim 5,
When the preset reference voltage is a negative voltage,
The shift register, characterized in that the transfer of the preset reference voltage input to the non-inverting input terminal of the comparator is slower due to a difference in RC delay values than the transfer of the monitoring voltage input to the inverting input terminal of the comparator.
The method of claim 5,
When the preset reference voltage is a positive voltage,
The shift register, characterized in that transmission of a preset reference voltage input to the non-inverting input terminal of the comparator is faster by an RC delay than transmission of the monitoring voltage input to the inverting input terminal of the comparator.
The method of claim 1,
The node control unit provided in any one stage,
A first switching device connected to the set node and a charging power line that is controlled according to a start pulse or a scan pulse from a previous stage and transmits a charging voltage;
And a second switching device controlled according to a scan pulse from a subsequent stage, and connected between the set node and a first discharge power line that transmits the first discharge voltage.
The method of claim 1,
The output unit provided in any one stage,
A pull-up switching device controlled according to the voltage of the set node and connected between a clock transmission line for transmitting any one clock pulse and an output terminal of any one stage; And,
And a pull-down switching device controlled according to the voltage of the reset node and connected between the output terminal and a first discharge power line for transmitting the first discharge voltage.

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