KR102133573B1 - Semiconductor memory and memory system including semiconductor memory - Google Patents

Abstract

The present invention relates to a memory system. The memory system of the present invention is a memory controller that controls first and second semiconductor memories, and first and second semiconductor memories having a same structure to each other and including a plurality of memory cells arranged in rows and columns, respectively. It is composed. The first and second semiconductor memories commonly receive an address from a memory controller. The first addresses of the first rows adjacent to the row of memory cells selected from the first semiconductor memory in response to the commonly received address are the second addresses of the second rows adjacent to the row of memory cells selected from the second semiconductor memory. It is different from the others.

Description

A semiconductor memory and a memory system including the semiconductor memory {SEMICONDUCTOR MEMORY AND MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY}

The present invention relates to a semiconductor memory and a memory system including the semiconductor memory.

Semiconductor memory (semiconductor memory) is a storage device implemented using a semiconductor such as silicon (Si, silicon), germanium (Ge, Germanium), arsenic gallium (GaAs, gallium arsenide), indium phosphide (InP, indium phospide). Semiconductor memory is largely divided into volatile memory (Volatile memory) and nonvolatile memory (Nonvolatile memory).

Volatile memory is a memory device that loses stored data when the power supply is cut off. Volatile memory includes SRAM (Static RAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), and the like. Non-volatile memory is a memory device that retains stored data even when the power supply is cut off. Non-volatile memory includes ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), Flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like.

As semiconductor manufacturing processes develop, miniaturization of semiconductor memories is progressing. In particular, miniaturization of semiconductor memory cells is progressing. Miniaturized semiconductor memory cells are experiencing various phenomena that have not occurred before. In particular, some of the phenomena occurring in the miniaturized semiconductor memory cells may destroy data stored in the semiconductor memory cells, thereby deteriorating reliability of the semiconductor memory. Therefore, research is needed to solve the problems occurring in miniaturized semiconductor memory cells.

An object of the present invention is to provide a semiconductor memory having improved reliability and a four-memory system including the semiconductor memory.

A memory system according to an embodiment of the present invention includes first and second semiconductor memories having the same structure as each other and including a plurality of memory cells arranged in rows and columns, respectively; And a memory controller configured to control the first and second semiconductor memories, wherein the first and second semiconductor memories are configured to receive an address from the memory controller in common, and respond to the commonly received address. Thus, the first addresses of the first rows adjacent to the row of memory cells selected from the first semiconductor memory are adjacent to the row of the memory cells selected from the second semiconductor memory in response to the commonly received address. Is different from the second addresses of.

As an embodiment, the first addresses and the second addresses are addresses transferred from the memory controller to the first and second semiconductor memories.

As an embodiment, the first and second semiconductor memories are configured to convert the commonly received address into different translation addresses and access memory cells according to the translation addresses.

As an embodiment, each of the first and second semiconductor memories may include: an address buffer configured to store the commonly received address; A program circuit configured to store scramble information; And an address converter configured to convert an address stored in the address buffer into a conversion address according to the scramble information stored in the program circuit.

As an embodiment, scramble conversion information of the first and second semiconductor memories is set to different values.

As an embodiment, the program circuit includes a fuse circuit or a mode register.

As an embodiment, the memory controller is configured to write the scramble information to the first and second semiconductor memories at power-on.

As an embodiment, the third and fourth semiconductor memories may further include third and fourth semiconductor memories having the same structure as each other, and including a plurality of memory cells arranged in rows and columns, respectively. The third addresses of the third rows adjacent to the row of memory cells selected from the third semiconductor memory in response to the commonly received address are configured to receive the address in common, and in response to the commonly received address. It is different from the fourth addresses of the fourth rows adjacent to the row of memory cells selected from the fourth semiconductor memory.

As an embodiment, the first to fourth semiconductor memories are configured to commonly receive an address from the memory controller, and the first to fourth addresses are different.

As an embodiment, the first and second semiconductor memories form a first memory module communicating with the memory controller through a first channel, and the third and fourth semiconductor memories communicate with the memory controller through a second channel. Form a second memory module in communication.

As an embodiment, the first and second semiconductor memories form a first rank, the third and fourth semiconductor memories form a second rank, and the first and third semiconductor memories have common first data. The line communicates with the memory controller, and the second and fourth semiconductor memories communicate with the memory controller through common second data lines.

As an embodiment, a register block configured to receive the address from the memory controller and to transmit the received address to the first and second semiconductor memories further comprises the scrambled block upon power-on. And write information to the first and second semiconductor memories.

As an embodiment, the first address node of the memory controller is connected to different first and second address nodes of the first and second semiconductor memories, respectively.

A semiconductor memory according to an embodiment of the present invention includes a plurality of memory cells arranged in rows and columns; An address buffer configured to store the received address; A program circuit configured to store scramble information; And an address converter configured to convert an address stored in the address buffer into a conversion address according to the scramble information stored in the program circuit. And a row decoder configured to access rows of the plurality of memory cells based on the translation address.

As an embodiment, the program circuit includes a mode register or fuse circuit.

According to embodiments of the present invention, a plurality of semiconductor memories select memory cells at different locations in response to an address commonly received from a memory controller. The rows activated in the plurality of semiconductor memories are different from each other, and adjacent word lines experiencing stress by the activated rows are different from each other. In a plurality of semiconductor memories, since the rows experiencing stress from the active row are different from each other, burst errors are prevented from occurring. Accordingly, a semiconductor memory having improved reliability and a memory system including the semiconductor memory are provided.

1 is a block diagram showing a memory system according to a first embodiment of the present invention.
2 is a block diagram showing a memory chip according to an embodiment of the present invention.
3 is a table showing a first example of addresses allocated to word lines of a plurality of memory chips.
4 is a table showing examples of word lines that are stressed from word lines that are activated and word lines that are activated.
5 is a flowchart illustrating a method of operating a memory chip according to an embodiment of the present invention.
6 is a table showing examples of memory chips and scramble information corresponding to them.
7 is a table showing examples of addresses and addresses converted from a plurality of memory chips.
8 is a table showing another example of word lines that are stressed from word lines that are activated and word lines that are activated.
9 is a table showing examples of address translation schemes and scramble information.
10 is a flowchart illustrating a method of operating a memory controller according to an embodiment of the present invention.
11 is a block diagram illustrating a memory system according to a second embodiment of the present invention.
12 is a table showing examples of memory chips and scramble information SI corresponding to them.
13 is a block diagram illustrating a memory system according to a third embodiment of the present invention.
14 is a block diagram illustrating a memory system according to a fourth embodiment of the present invention.
15 is a table showing examples of memory chips and scramble information corresponding to them.
16 is a block diagram illustrating a memory system according to a fifth embodiment of the present invention.
17 is a block diagram illustrating a memory system according to a sixth embodiment of the present invention.
18 is a block diagram illustrating a memory system according to a seventh embodiment of the present invention.
19 is a table showing an example in which address lines are scrambled.
20 is a block diagram illustrating a computing device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to describe in detail that a person skilled in the art to which the present invention pertains can easily implement the technical spirit of the present invention. .

1 is a block diagram showing a memory system 1000 according to a first embodiment of the present invention. Referring to FIG. 1, the memory system 1000 includes a semiconductor memory device 1100 and a memory controller 1300.

The semiconductor memory device 1100 includes a plurality of memory chips 1101-110n. The plurality of memory chips 1101-110n may operate under the control of the memory controller 1300. The memory chips 1101-110n may exchange data with the memory controller 1300 through different data lines DL. The plurality of memory chips 1101-110n may receive an address from the memory controller 1300 through a common address line AL.

For example, the plurality of memory chips 1101 to 110n may be dynamic random access memory (DRAM) chips. Hereinafter, it is assumed that the plurality of memory chips 1101-110n are DRAM chips. However, the technical idea of the present invention is not limited to DRAM chips. The technical idea of the present invention includes SRAM (Static RAM), SDRAM (Synchronous DRAM), ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), Flash memory, It can be applied to various memories such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

The semiconductor memory device 1100 may form a memory module. The semiconductor memory device 1100 may be integrated into a single package to form a multi-chip package. The semiconductor memory device 1100 and the memory controller 1300 may be integrated into one package to form a chip-on-chip package. The semiconductor memory device 1100 and the memory controller 1300 may respectively form packages and form a package-on-package.

The memory controller 1300 is configured to control the semiconductor memory device 1100. The memory controller 1300 may control reading and writing of the semiconductor memory device 1100. The memory controller 1300 includes a nonvolatile memory 1310.

The nonvolatile memory 1310 includes read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EPMROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM) RAM, RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like. The nonvolatile memory 1310 may store various information required for the operation of the semiconductor memory device 1100. For example, the nonvolatile memory 1310 may store information for setting the mode registers of the memory chips 1101-110n of the semiconductor memory device 1100. For example, the nonvolatile memory 1310 may store information such as CAS latency, RAS latency, additive latency, burst length, and the like.

At power-on, the memory controller 1300 may transmit and store information stored in the nonvolatile memory 1310 to the memory chips 1101 to 110n.

The memory chips 1101-110n commonly receive addresses from the memory controller 1300. In response to the commonly received address, the memory chips 1101-110n may access memory cells at different locations. For example, in response to a commonly received address, the memory chips 1101-110n may access memory cells in different rows.

2 is a block diagram showing a memory chip 110k according to an embodiment of the present invention. 1 and 2, the memory chip 110k includes a memory cell array 110, a bank selector 120, a row decoder 130, a column decoder 140, a read and write circuit 150, and an address converter. 160, an address buffer 170, and a program circuit 180.

The memory cell array 110 includes a plurality of memory banks. Each of the plurality of memory banks may include a plurality of memory cells arranged along rows and columns. The rows of memory cells are respectively connected to word lines WL. The columns of memory cells are respectively connected to the bit lines BL. The number of banks of the memory cell array 110 is not limited.

The bank selector 120 is configured to select one of the memory banks of the memory cell array 110. The bank selector 120 may receive the address ADDR2 from the address converter 160 and select a memory bank according to the received address.

The row decoder 130 is connected to the memory cell array 110 through word lines WL. The row decoder 130 is configured to receive the address ADDR2 from the address converter 160 and select word lines WL according to the received address ADDR2. That is, the row decoder 130 may select rows of memory cells according to the received address ADDR2. The row decoder 130 may select rows of memory cells of the memory bank selected by the bank selector 120.

The column decoder 140 is connected to the memory cell array 110 through bit lines BL. The column decoder 140 is configured to receive the address ADDR2 from the address converter 160 and select bit lines BL according to the received address ADDR2. That is, the column decoder 140 may select columns of memory cells according to the received address ADDR2. The column decoder 140 may select rows of memory cells of the memory bank selected by the bank selector 120.

The read and write circuit 150 is connected to the column decoder 140. The read and write circuit 150 can access bit lines selected by the column decoder 140. The read and write circuit 150 may read and write memory cells connected to bit lines selected by the column decoder 140. The read and write circuit 150 may include a sense amplifier and a write driver.

The address converter 160 receives the address ADDR1 from the address buffer 170 and receives scramble information SI from the program circuit 180. The address converter 160 may convert the received address ADDR1 to the address ADDR2 based on the scramble information SI.

For example, the address converter 160 may convert a row address or a bank address based on scramble information SI. The address converter 160 may perform conversion in response to the RAS signal. The address converter 160 may transmit the converted address ADDR2 to the bank selector 120 or the row decoder 130.

The address converter 160 may not perform conversion on the column address. The address converter 160 may skip address translation in response to the CAS signal.

The address buffer 170 may receive the address ADDR1 from the memory controller 1300 through the address line AL. The address buffer 170 may store the received address ADDR1 and output it to the address converter 160.

The program circuit 180 may store scramble information SI. The program circuit 180 may be a fuse circuit (eg, a laser fuse circuit or an electric fuse circuit) or a mode register. When the program circuit 180 is a mode register, scramble information SI of the memory chips 1101-110n may be stored in the nonvolatile memory 1310 of the memory controller 1300. The memory controller 1300 may program scramble information SI to program circuits of the memory chips 1101 to 110n, respectively. When the program circuit 180 is a fuse circuit, the scramble information SI may be programmed in the program circuit 180 by the test device or the memory controller 1300.

The scramble information SI may include information on a relationship between a row address received from the memory controller 1300 and a row address used inside the memory chip 110k. For example, the scramble information SI may be a table including mapping information between addresses. The scramble information SI may include information on rules for converting between addresses.

3 is a table showing a first example of addresses allocated to word lines of a plurality of memory chips 1101 to 110n. Illustratively, an example of conventional address assignment is shown in FIG. 3.

1 to 3, first to tenth row addresses may be allocated to first to tenth word lines WL1 to WL10 of the memory chip 1101, respectively. First to tenth row addresses may be assigned to the first to tenth word lines WL1 to WL10 of the memory chip 1102, respectively. First to tenth row addresses may be assigned to the first to tenth word lines WL1 to WLi of the memory chip 110n, respectively. That is, in the memory chips 1101 to 110n, the same row addresses may be assigned to word lines of the same location.

For brevity, the first to tenth word lines WL1 to WL10 and the first to tenth row addresses are shown in FIG. 3. However, the number of word lines and the number of row addresses are not limited.

4 is a table showing examples of word lines that are stressed from word lines that are activated and word lines that are activated. 3 and 4, row addresses of '4' may be commonly transmitted to the memory chips 1101 to 110n. In response to the row address, the fourth word line WL4 may be activated in common in the memory chips 1101 to 110n.

When the fourth word line WL4 is activated, the third and fifth word lines WL3 and WL5 adjacent to the fourth word line WL4 may experience stress from the activated fourth word line WL4. . For example, the third and fifth word lines WL3 and WL5 may experience stress by row hammer or field penetration. The activated fourth word line WL4 is an aggressor word line, and the third and fifth word lines WL3 and WL5 adjacent to the activated fourth word line WL4 are victim word lines. Can. When the fourth word line WL_4 is repeatedly activated, memory cells connected to the third and fifth word lines WL3 and WL5 may lose data due to accumulated stress.

At least one memory chip among the plurality of memory chips 1101 to 110n may store parity for performing error correction. When error correction is performed, errors occurring in data stored in the plurality of memory chips 1101 to 110n may be corrected. However, error correction has a predetermined limit. For example, the number of error bits that can be corrected through error correction may be limited.

A plurality of memory chips 1101 to 110n commonly receive an address through the address line AL. When the fourth word line WL4 is repeatedly accessed, memory cells connected to the third and fifth word lines WL3 and WL5 of the plurality of memory chips 1101 to 110n commonly experience stress. Accordingly, data stored in memory cells connected to the third and fifth word lines WL3 and WL5 of the plurality of memory chips 1101 to 110n may be lost together. Thereafter, when a read is performed on the third or fifth word line WL3 or WL5 of the plurality of memory chips 1101 to 110n, all data bits output from the plurality of memory chips 1101 to 110n are It can be error bits. In this case, the number of error bits of data bits output from the plurality of memory chips 1101 to 110n may exceed a range that can be corrected through error correction.

In order to prevent such a problem, the memory chips 1101 to 110n according to an embodiment of the present invention convert the address ADDR1 received from the memory controller 1300 to the address ADDR2 using scramble information SI. To convert. The memory chips 1101-110n access memory cells using the converted address ADDR2. The scramble information SI may be set differently from the plurality of memory chips 1101 to 110n. For example, the scramble information SI is a plurality of memories when rows (or word lines) of memory cells of the memory chips 1101-110n are selected (or activated) by the same address ADDR1. The addresses of the victim word lines in the chips 1101 to 110n may be set to be different from each other. Accordingly, when the same address ADDR1 is repeatedly transmitted to the memory chips 1101 to 110n, stress is applied to memory cells corresponding to the same address (eg, row address) in the plurality of memory chips 1101 to 110n. Accumulation is prevented.

5 is a flowchart illustrating a method of operating a memory chip 110k according to an embodiment of the present invention. 1 and 5, in step S110, scramble information SI is read from the program circuit 180.

In step S120, the address ADDR1 is received from the outside.

In step S130, the received address ADDR1 is converted to the address ADDR2 according to the scramble information SI. For example, a row address of the received address ADDR1 may be converted.

6 is a table showing examples of memory chips 1101-110n and scramble information SI corresponding to them. 1 and 6, scramble information SI_1 to SI_n may be allocated to the memory chips 1101 to 110n, respectively. The scramble information SI_1 to SI_n may be different. The scramble information SI_1 to SI_n may include different address translation tables or different address translation rules. The scramble information SI_1 to SI_n is selected when (or activated) rows (or word lines) of memory cells of the memory chips 1101 to 110n by the same address ADDR1, and a plurality of memory chips ( 1101 to 110n), the addresses of the victim word lines may be set to be different from each other.

7 is a table showing an example of addresses and addresses converted from a plurality of memory chips 1101 to 110n. For example, row addresses transmitted from the memory controller 1300 and row addresses converted from the plurality of memory chips 1101 to 110n are illustrated in FIG. 7.

1, 2 and 7, the row address transmitted from the memory controller 1300 may not be converted in the memory chip 1101. The memory chip 1101 may perform no conversion. The scramble information SI of the memory chip 1101 may include information about no conversion. The converted address of the memory chip 1101 may be the same as the address transmitted from the memory controller 1300.

The row address transmitted from the memory controller 1300 may be converted in the memory chips 1102 to 110n. The memory chips 1102-110n may perform address conversion according to scramble information SI, respectively.

8 is a table showing another example of word lines that are stressed from word lines that are activated and word lines that are activated. Illustratively, an example of word lines and stressed word lines that are activated according to the translated address is shown in FIG. 8.

3, 7 and 8, a row address of '4' may be commonly transmitted to the memory chips 1101 to 110n. In the memory chip 1101, a row address of '4' may be converted to a row address of '4'. According to the converted row address of '4', the fourth word line WL4 may be activated in the memory chip 1101. As the fourth word line WL4 is activated, adjacent third and fifth word lines WL3 and WL5 may experience stress.

In the memory chip 1101, the address and the translated address may be the same. Accordingly, the addresses required to access the word lines WL3 and WL5 may be '3' and '5'.

In the memory chip 1102, a row address of '4' may be converted to a row address of '7'. According to the converted row address of '7', the seventh word line WL7 may be activated in the memory chip 1102. As the seventh word line WL7 is activated, adjacent sixth and eighth word lines WL6 and WL8 may experience stress.

In the memory chip 1102, the sixth word line WL6 may be accessed according to the converted row address of '6'. In the memory chip 1102, an address of '8' may be converted into a converted row address of '6'. Accordingly, the address required to access the sixth word line WL6 may be '8'.

Similarly, in the memory chip 1102, the eighth word line WL8 can be accessed according to the converted row address of '8'. In the memory chip 1102, the address of '9' may be converted to the converted row address of '8'. Accordingly, the address required to access the eighth word line WL8 may be '9'.

In the memory chip 110n, a row address of '4' may be converted to a row address of '10'. The tenth word line WL10 may be activated in the memory chip 110n according to the converted row address of '10'. As the tenth word line WL10 is activated, the adjacent ninth word line WL9 may experience stress.

In the memory chip 110n, the ninth word line WL9 may be accessed according to the converted row address of '9'. In the memory chip 110n, the address of '10' may be converted to a translated row address of '9'. Accordingly, the address required to access the ninth word line WL9 may be '10'.

As described above, the rows (or word lines) experiencing stress in the memory chip 1101 correspond to addresses '3' and '5' transmitted from the memory controller 1300. Rows (or word lines) experiencing stress in the memory chip 1102 correspond to addresses '8' and '9' transmitted from the memory controller 1300. The row (or word line) experiencing stress in the memory chip 110n corresponds to the address of '10' transmitted from the memory controller 1300.

When the memory controller 1300 transmits the row address of '4' to the memory chips 1101-110n, the memory chip 1101 stresses the rows of memory cells corresponding to the row addresses of '3' and '5'. Is applied, stress is applied to the rows of memory cells corresponding to the row addresses of '8' and '9' in the memory chip 1102, and corresponding to the row address of '10' in the memory chip 110n. Stress is applied to the row of memory cells. When the memory controller 1300 accesses a specific address of the memory chips 1101 to 110n, addresses associated with memory cells experiencing stress in the memory chips 1101 to 110n are changed. Accordingly, it is prevented that all data bits output from the memory chips 1101 to 110n by the address transmitted by the memory controller 1300 become error bits due to stress.

9 is a table showing examples of address translation schemes and scramble information (SI). Referring to FIG. 9, the address translation scheme may include cyclic shift, flip, randomize, and table translation.

A circular shift may cyclically shift a row address by a predetermined number of bits. The scramble information SI may include information on the number of bits whose row address is cyclically shifted.

A flip can invert bits at a predetermined location in a row address. The scramble information SI may include information about the number and position of bits to be inverted.

Randomize can generate a new address by computing the row address with a seed. The scramble information SI may include information on seeds for performing an operation.

Table conversion may convert addresses according to a pre-determined table (PDT). The scramble information SI may include a predetermined table PDT.

10 is a flowchart illustrating an operation method of the memory controller 1300 according to an embodiment of the present invention. For example, an example in which the memory controller 1300 programs scramble information SI stored in the nonvolatile memory 1310 to the memory chips 1101 to 110n is illustrated in FIG.

1 and 10, in step S210, the memory controller 1300 may detect that power is supplied.

In operation S220, the memory controller 1300 may read scramble information SI for the memory chips 1101-110n from the nonvolatile memory 1310.

In operation S230, the memory controller 1300 may program scramble information SI to the memory chips 1101-110n.

For example, steps S210 and S230 may be performed during the initialization operation of the memory system 1000.

11 is a block diagram illustrating a memory system 2000 according to a second embodiment of the present invention. Referring to FIG. 11, the memory system 2000 includes first and second semiconductor memory devices 2100 and 2200 and a memory controller 2300.

The first semiconductor memory device 2100 includes first memory chips 2101 to 210n. The first memory chips 2101 to 210n may communicate with the memory controller 2300 through separate data lines DL, respectively. The first memory chips 2101 to 210n may communicate with the memory controller 2300 through a common address line AL.

The second semiconductor memory device 2200 includes second memory chips 2201 to 220n. The second memory chips 2201 to 220n may communicate with the memory controller 2300 through separate data lines DL, respectively. The second memory chips 2201 to 220n may communicate with the memory controller 2300 through a common address line AL.

The data lines DL and the address lines AL in which the first memory chips 2101 to 210n communicate with the memory controller 2300 may form a first channel CH1. The data lines DL and the address lines AL that the second memory chips 2201 to 220n communicate with the memory controller 2300 may form a second channel CH2. The memory system 2000 may be a multi-channel memory system.

The first memory chips 2101 to 210n and the second memory chips 2201 to 220n may commonly receive an address from the memory controller 2300.

The memory controller 2300 is configured to control the first and second semiconductor memory devices 2100 and 2200. The memory controller 2300 includes a nonvolatile memory 2310. The nonvolatile memory 2310 may store various information required for the operation of the first and second semiconductor memory devices 2100 and 2200.

Each of the first memory chips 2101 to 210n and the second memory chips 2201 to 220n may convert an address received from the memory controller 2300 and operate according to the converted address. Each of the first memory chips 2101 to 210n and the second memory chips 2201 to 220n is configured such that the rows of memory cells that are activated according to addresses commonly received from the memory controller 2300 and the addresses of adjacent rows are different from each other. , Address translation can be performed.

The semiconductor memory device 2100 may form a memory module. The semiconductor memory device 2100 may be integrated into a single package to form a multi-chip package. The semiconductor memory device 2200 may form a memory module. The semiconductor memory device 2200 may be integrated into one package to form a multi-chip package. The semiconductor memory devices 2100 and 2200 may be integrated into one package to form a multi-chip package.

The semiconductor memory devices 2100 and 2200 and the memory controller 2300 may be integrated into one package to form a chip-on-chip package. The semiconductor memory devices 2100 and 2200 and the memory controller 2300 may respectively form packages and form a package-on-package.

12 is a table showing examples of memory chips 2101 to 210n, 2201 to 220n, and scramble information SI corresponding to them. 11 and 12, the first scramble information SI_a is allocated to the memory chips 2101 to 210n, and the second scramble information SI_b is allocated to the memory chips 2201 to 220n. That is, different scramble information SI_a and SI_b may be allocated for each channel of the memory chips 2101 to 210n and 2201 to 220n. The first scramble information SI_a and SI_b may be different from each other.

Second scramble information SI_1 to SI_n may be allocated to the memory chips 2101 to 210n, respectively. Second scramble information SI_1 to SI_2 may be allocated to the memory chips 2201 to 220n, respectively. The second scramble information SI_1 to SI_n may be different. Each of the memory chips 2101 to 210n and 2201 to 220n may perform address translation by combining first and second scramble information allocated to them. That is, the memory chips 2101 to 210n and 2201 to 220n may perform address translation based on different scramble information SI.

For example, the memory chips 2101 to 210n may generate scramble information SI_a1 to SI_an by combining the first scramble information SI_a and the second scramble information SI_1 to SI_n. The memory chips 2201 to 220n may generate scramble information SI_b1 to SI_bn by combining the first scramble information SI_b and the second scramble information SI_1 to SI_n. The scramble information SI_a1 to SI_an, SI_b1 to SI_bn may include different address translation tables or different address translation rules. The scramble information SI_a1 to SI_an, SI_b1 to SI_bn are activated (or activated) when rows (or word lines) of memory cells of the memory chips 2101 to 210n, 2201 to 220n are selected by the same address ADDR1. When), the addresses of the victim word lines in the plurality of memory chips 2101 to 210n and 2201 to 220n may be set to be different from each other.

13 is a block diagram illustrating a memory system 3000 according to a third embodiment of the present invention. Referring to FIG. 13, the memory system 3000 includes a semiconductor memory device 3100 and a memory controller 3300.

The semiconductor memory device 3100 includes first memory chips 3101_a to 310n_a and second memory chips 3101_b to 310n to b.

The first memory chips 3101_a to 310n_a may communicate with the memory controller 3300 through separate data lines DL, respectively. The first memory chips 3101_a to 310n_a may communicate with the memory controller 3300 through a common address line AL.

The second memory chips 3101_b to 310n_b may communicate with the memory controller 3300 through separate data lines DL, respectively. The first memory chips 3101_b to 310n_b may communicate with the memory controller 3300 through a common address line AL.

The first memory chips 3101_a to 310n_a may form a first rank, and the second memory chips 3101_b to 310n_b may form a second rank. The first memory chip 310k_a may share the data line DL and the address line AL with the corresponding second memory chip 310k_b.

The first memory chips 3101_a to 310n_a and the second memory chips 3101_b to 310n_b may commonly receive an address from the memory controller 3300.

The memory controller 3300 is configured to control the semiconductor memory device 3100. The memory controller 3300 includes a nonvolatile memory 3310. The nonvolatile memory 3310 may store various information required for the operation of the semiconductor memory device 3100.

Each of the first memory chips 3101_a to 310n_a and the second memory chips 3101_b to 310n_b may convert an address received from the memory controller 3300 and operate according to the converted address. Each of the first memory chips 3101_a to 310n_a and the second memory chips 3101_b to 310n_b is configured such that addresses of rows of adjacent memory cells and adjacent rows are different according to addresses commonly received from the memory controller 3300. , Address translation can be performed.

The semiconductor memory device 3100 may form a memory module. The semiconductor memory device 3100 may be integrated into one package to form a multi-chip package. The semiconductor memory device 3100 and the memory controller 3300 may be integrated into one package to form a chip-on-chip package. The semiconductor memory device 3100 and the memory controller 3300 may respectively form packages and form a package-on-package.

As illustrated in FIG. 12, the first memory chips 3101_a to 310n_a and the second memory chips 3101_b to 310n_b may be assigned different scramble information SI. For example, the first scramble information may be allocated for each rank of the memory chips 3101_a to 310n_a and 3101_b to 310b_b. Second scramble information may be allocated to the first memory chips 3101_a to 310n_a, and second scramble information may be allocated to the second memory chips 3101_b to 310n_b, respectively.

14 is a block diagram illustrating a memory system 4000 according to a fourth embodiment of the present invention. Referring to FIG. 14, the memory system 4000 includes first and second semiconductor memory devices 4100 and 4200 and a memory controller 4300.

The first semiconductor memory device 4100 includes first memory chips 4101_a to 410n_a and second memory chips 4101_b to 410n to b.

The first memory chips 4101_a to 410n_a may communicate with the memory controller 4300 through separate data lines DL, respectively. The first memory chips 4101_a to 410n_a may communicate with the memory controller 4300 through a common address line AL.

The second memory chips 4101_b to 410n_b may communicate with the memory controller 4300 through separate data lines DL, respectively. The first memory chips 4101_b to 410n_b may communicate with the memory controller 4300 through a common address line AL.

The first memory chips 4101_a to 410n_a may form a first rank, and the second memory chips 4101_b to 410n_b may form a second rank. The first memory chip 410k_a may share the data line DL and the address line AL with the corresponding second memory chip 410k_b.

The second semiconductor memory device 4400 includes first memory chips 4201_a to 420n_a and second memory chips 4201_b to 420n to b. The first memory chips 4201_a to 420n_a and the second memory chips 4201_b to 420n to b may form first and second ranks, respectively.

The memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, and 4201_b to 420n_b may commonly receive an address from the memory controller 4300.

The memory controller 4300 is configured to control the semiconductor memory device 4100. The memory controller 4300 includes a nonvolatile memory 4310. The nonvolatile memory 4310 may store various information required for the operation of the semiconductor memory device 4100.

Each of the memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, and 4201_b to 420n_b may convert an address received from the memory controller 4300 and operate according to the converted address. Each of the memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, and 4201_b to 420n_b is configured such that addresses of memory cells that are activated and addresses of adjacent rows are different according to an address commonly received from the memory controller 4300 , Address translation can be performed.

The semiconductor memory device 4100 may form a memory module. The semiconductor memory device 4100 may be integrated into a single package to form a multi-chip package. The semiconductor memory device 4200 may form a memory module. The semiconductor memory device 4200 may be integrated into a single package to form a multi-chip package. The semiconductor memory devices 4100 and 4200 may be integrated into one package to form a multi-chip package.

The semiconductor memory devices 4100 and 4200 and the memory controller 4300 may be integrated into one package to form a chip-on-chip package. The semiconductor memory devices 4100 and 4200 and the memory controller 4300 may respectively form packages and form a package-on-package.

The memory system 4000 of FIG. 14 may be a combination of the memory system 2000 of FIG. 11 and the memory system 3000 of FIG. 13. The memory system 4000 includes multiple channels, and a multi rank may be provided for each channel. Illustratively, in memory system 4000, the same number of ranks are provided per channel. However, different numbers of ranks may be provided for each channel.

15 is a table showing examples of memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, and 4201_b to 420n_b and scramble information SI corresponding to them. 14 and 15, first scramble information SI_a is allocated to memory chips 4101_a to 410n_a, 4101_b to 410n_b, and second scramble information SI_b to memory chips 4201_a to 420n_a and 4201_b to 420n_b. ) Can be assigned. That is, different first scramble information SI_a and SI_b may be allocated for each channel of the memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, and 4201_b to 420n_b. The first scramble information SI_a and SI_b may be different from each other.

In the first channel, the second scramble information SI_R1 is allocated to the memory chips 4101_a to 410n_a, and the second scramble information SI_R2 is allocated to the memory chips 4101_b to 410n_b. In the second channel, the second scramble information SI_R1 is allocated to the memory chips 4201_a to 420n_a, and the second scramble information SI_R2 is allocated to the memory chips 4201_b to 420n_b. That is, different scrambling information SI_R1 and SI_R2 may be allocated for each rank of the memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, and 4201_b to 420n_b. The second scramble information SI_R1 and SI_R2 may be different.

In the first rank RANK1 of the first channel CH1, third scramble information SI_1 to SI_n may be allocated to the memory chips 4101_a to 410n_a, respectively. In the second rank RANK2 of the first channel CH1, the third scramble information SI_1 to SI_2 may be allocated to the memory chips 4101_b to 410n_b, respectively. In the first rank RANK1 of the second channel CH2, third scramble information SI_1 to SI_n may be allocated to the memory chips 4201_a to 420n_a, respectively. In the second rank RANK2 of the second channel CH2, third scramble information SI_1 to SI_2 may be allocated to the memory chips 4201_b to 420n_b, respectively.

The third scramble information SI_1 to SI_n may be different. Each of the memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, and 4201_b to 420n_b may perform address translation by combining the first to third scramble information allocated thereto. That is, the memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, and 4201_b to 420n_b may perform address translation based on different scramble information SI.

For example, the memory chips 4101_a to 410n_a may generate scramble information SI_aR11 to SI_aR1n by combining the first to third scramble information. The memory chips 4101_b to 410n_b may generate scramble information SI_aR21 to SI_aR2n by combining the first to third scramble information. The memory chips 4201_a to 420n_a may generate scramble information SI_bR11 to SI_bR1n by combining the first to third scramble information. The memory chips 4201_b to 420n_b may generate scramble information SI_bR21 to SI_bR2n by combining the first to third scramble information.

The scramble information (SI_aR11 to SI_aR1n, SI_aR21 to SI_aR2n, SI_bR11 to SI_bR1n, SI_bR21 to SI_bR2n) may include different address translation tables or different address translation rules. The scramble information (SI_aR11 to SI_aR1n, SI_aR21 to SI_aR2n, SI_bR11 to SI_bR1n, and SI_bR21 to SI_bR2n) are memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 4201_a, 4201_n When the rows of (or word lines) of are selected (or activated), the addresses of the victim word lines in the plurality of memory chips 4101_a to 410n_a, 4101_b to 410n_b, 4201_a to 420n_a, 4201_b to 420n_b are different from each other. Can be set.

16 is a block diagram illustrating a memory system 5000 according to a fifth embodiment of the present invention. Referring to FIG. 16, the memory system 5000 includes a semiconductor memory device 5100 and a memory controller 5300.

The semiconductor memory device 5100 includes memory chips 5101 to 510n and a register chip 5110. The register chip 5110 receives an address from the memory controller 5300 through the address line AL. The register chip 5110 may transmit the received address to the memory chips 5101 to 510n.

The memory chips 5101-510n may communicate with the memory controller 5300 through separate data lines DL, respectively. The memory chips 5101-510n may communicate with the register chip 5110 through a common address line AL.

The memory system 5000 has the same structure as the memory system 1000 described with reference to FIG. 1 except that the register chip 5110 is provided, and may operate in the same manner. Each of the memory chips 5201 to 510n may convert an address received from the register chip 5110.

The scramble information SI may be transmitted from the memory controller 5300 to the memory chips 5101 to 510n through the register chip 5110. The register chip 5110 may store scramble information SI in an internal nonvolatile memory 5111. At power-on, the register chip 5110 may transmit scramble information SI to the memory chips 5101 to 510n.

The memory system 5000 may be implemented as multi-channel or multi-bank, as described with reference to FIGS. 11 to 15.

17 is a block diagram showing a memory system 6000 according to a sixth embodiment of the present invention. Referring to FIG. 17, the memory system 6000 includes a semiconductor memory device 6100 and a memory controller 6300.

The semiconductor memory device 6100 includes memory chips 6101-610n and a register chip 6110. The register chip 6110 receives an address from the memory controller 6300 through the address line AL. The register chip 6110 exchanges data with the memory controller 6300 through the data line DL. The register chip 6110 may transmit the received address to the memory chips 6101 to 610n. The register chip 6110 may exchange data exchanged with the memory controller 6300 with memory chips 6101-610n.

The memory chips 6101-610n may communicate with the register chip 6110 through separate data lines DL, respectively. The memory chips 6101-610n may communicate with the register chip 6110 through a common address line AL.

The memory system 6000 has the same structure as the memory system 1000 described with reference to FIG. 1 except that the register chip 6110 is provided, and may operate in the same manner. Each of the memory chips 6101 to 610n may convert an address received from the register chip 6110.

The scramble information SI may be transmitted from the memory controller 6300 to the memory chips 6101-610n through the register chip 6110. The register chip 6110 may store scramble information SI in an internal nonvolatile memory 6111. At power-on, the register chip 6110 may transmit scramble information SI to the memory chips 6101-610n.

The memory system 6000 may be implemented as multi-channel or multi-bank, as described with reference to FIGS. 11 to 15.

18 is a block diagram showing a memory system 7000 according to a seventh embodiment of the present invention. Referring to FIG. 18, the memory system 7000 includes a semiconductor memory device 7100 and a memory controller 7300.

The semiconductor memory device 7100 includes first and second memory chips 7101 and 7102. The first memory chip 7101 includes address nodes A1 to A4. The second memory chip 7102 includes address nodes A1 to A4. The first and second memory chips 7101 and 7102 may receive addresses from the memory controller 7300, respectively, through the address nodes A1 to A4.

The memory controller 7300 includes address nodes A1 to A4. The memory controller 7300 outputs addresses through the address nodes A1 to A4.

In FIG. 18, data lines between the first and second memory chips 7101 and 7102 and the memory controller 7300 are omitted.

The specific address node of the memory controller 7300 may be connected to different address nodes of the first and second memory chips 7101 and 7102, respectively. For example, the address node A1 of the memory controller 7300 is connected to the address nodes A1 of the first and second memory chips 7101 and 7102, and the address node A4 of the memory controller 7300 Is connected to the address nodes A4 of the first and second memory chips 7101 and 7102. On the other hand, the address node A2 of the memory controller 7300 is connected to the address node A2 of the first memory chip 7101, and is connected to the address node A3 of the second memory chip 7102. The address node A3 of the memory controller 7300 is connected to the address node A3 of the first memory chip 7101, and is connected to the address node A2 of the second memory chip 7102.

That is, address lines AL connecting the memory controller 7300 and the first and second memory chips 7101 and 7102 may be scrambled. Although the memory controller 7300 outputs the same address through the address nodes A1 to A4, the addresses received at the address nodes A1 to A4 of the first and second memory chips 7101 and 7102 are different from each other. Can be. For example, when the rows (or word lines) of memory cells of the memory chips 7101 and 7102 are selected (or activated) by the same address output from the memory controller 7300, the memory chips 7101, In 7102, the address lines AL may be scrambled so that the addresses of the victim word lines are different from each other.

19 is a table showing an example in which address lines AL are scrambled. Referring to FIG. 19, first to third address nodes A1 to A3 may be provided to a memory controller.

Address nodes A1, A2, and A3 of the memory controller may be connected to address nodes A1, A2, and A3 of the first memory chip MC1, respectively. Address nodes A1, A2, and A3 of the memory controller may be connected to address nodes A1, A3, and A2 of the second memory chip MC2, respectively. Address nodes A1, A2, and A3 of the memory controller may be connected to address nodes A2, A1, and A3 of the third memory chip MC3, respectively. Address nodes A1, A2, and A3 of the memory controller may be connected to address nodes A2, A3, and A1 of the fourth memory chip MC4, respectively. Address nodes A1, A2, and A3 of the memory controller may be connected to address nodes A3, A1, and A2 of the fifth memory chip MC5, respectively. Address nodes A1, A2, and A3 of the memory controller may be connected to address nodes A3, A2, and A1 of the sixth memory chip MC6, respectively.

20 is a block diagram illustrating a computing device 8000 according to an embodiment of the present invention. Referring to FIG. 20, the computing device 8000 includes a processor 8100, a memory 8200, a storage 8300, a modem 8400, and a user interface 8500.

The processor 8100 may control various operations of the computing device 8000 and perform logical operations. For example, the processor 8100 may be configured as a system-on-chip (SoC). The processor 8100 may be a general purpose processor or an application processor.

The memory 8200 may communicate with the processor 8100. The memory 8200 may be an operating memory (or main memory) of the processor 8100 or the computing device 8000. The memory 8200 may include volatile memory such as static RAM (SRAM), dynamic RAM (DRAM), or synchronous memory (SDRAM), or flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), and resistive RAM (RRAM). , Nonvolatile memory such as FRAM (Ferroelectric RAM).

The memory 8200 may include semiconductor memory chips described with reference to FIGS. 1 to 19. The memory 8200 may include at least one semiconductor memory chip. Each of the at least one semiconductor memory chip may operate by receiving an address from the processor 8100 and converting the received address.

The memory 8200 may include at least one memory module or at least one memory package.

The storage 8300 may store data to be stored in the computing device 8000 in the long term. The storage 8300 is a non-volatile memory such as a hard disk drive (HDD) or flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), rational RAM (RRAM), and ferroelectric RAM (FRAM). It can contain.

For example, the memory 8200 and the storage 8300 may be configured of the same type of non-volatile memory. At this time, the memory 8200 and the storage 8300 may be configured as one semiconductor integrated circuit.

The modem 8400 may communicate with an external device under the control of the processor 8100. For example, the modem 8400 may perform wired or wireless communication with an external device. Modem 8400 is LTE (Long Term Evolution), WiMax (WiMax), GSM (Global System for Mobile communication), CDMA (Code Division Multiple Access), Bluetooth (Bluetooth), NFC (Near Field Communication), WiFi (WiFi) Various radio communication methods such as Radio Frequency Identification (RFID), or Universal Serial Bus (USB), Serial AT Attachment (SATA), Small Computer Small Interface (SCSI), Firewire, Peripheral Component Interconnection (PCI) Communication may be performed based on at least one of various wired communication methods.

The user interface 8500 can communicate with the user under the control of the processor 8100. For example, the user interface 8500 may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and the like. The user interface 8500 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix OLED (AMOLED) display, an LED, a speaker, a motor, and the like.

In the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope and technical spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, and should be determined not only by the claims described below but also by the claims and equivalents of the present invention.

1000-7000; Memory system
1100-7100; Semiconductor memory devices 2200, 4200; Semiconductor memory device
1300~7300; Memory controller
110k; Semiconductor memory chip
110; Memory cell array 120; Bank selector
130; Row decoder 140; Column decoder
150; Read and write circuit 160; Address translator
170; Address buffer 180; Program circuit

Claims (12)

First and second semiconductor memories including a plurality of memory cells arranged in rows and columns, respectively;
Third and fourth semiconductor memories having the same structure as the first and second semiconductor memories;
It is connected to the first and second semiconductor memories and provides common addresses, first_1 scramble information, 2_1 scramble information, and 2_2 scramble information to the first and second semiconductor memories, and the third and third A memory controller connected to four semiconductor memories and providing the common address, the first_2 scramble information, the second_1 scramble information, and the second_2 scramble information to the third and fourth semiconductor memories,
Each row of the plurality of first memory cells of the first semiconductor memory corresponds to a row of the same location in the plurality of second memory cells of the second semiconductor memory,
The first semiconductor memory accesses memory cells of a first row in the first semiconductor memory based on the common address, the first_1 scramble information, and the second_1 scramble information, and the second semiconductor memory is the common address , Accesses memory cells of a second row in the second semiconductor memory based on the first_1 scramble information and the second_2 scramble information,
The first position of the first row in the first semiconductor memory is different from the second position of the second row in the second semiconductor memory,
Row addresses adjacent to the memory cells of the first row in the first semiconductor memory are different from row addresses adjacent to the memory cells of the second row of the second semiconductor memory,
The third semiconductor memory selects a third row based on the common address, the first_2 scramble information, and the second_1 scramble information, and the fourth semiconductor memory includes the common address, the first_2 scramble information, and Select a fourth row based on the 2_2 scramble information, and
The third position of the third row is different from the first position, and the fourth position of the fourth row is different from the third position. According to claim 1,
The first to fourth semiconductor memories have the same structures. According to claim 1,
The first semiconductor memory converts the common address to a first address, and the second semiconductor memory converts the common address to a second address. According to claim 3,
Each of the first and second semiconductor memories is:
An address buffer for storing the common address;
A program circuit providing at least one of the 1_1 scramble information and the 2_1 or 2_2 scramble information; And
And an address converter for converting the common address stored in the address buffer into the first or second address according to the first_1 scramble information and the second_1 or 2_2 scramble information. According to claim 4,
The 2_1 scramble information is different from the 2_2 scramble information. According to claim 4,
The program circuit includes a fuse circuit or a mode register. According to claim 4,
The memory controller transmits the first_1 scramble information to the first and second semiconductor memories when the power is turned on. According to claim 1,
The common address is received from the memory controller, the received common address is transferred to the first and second semiconductor memories, and the first_1 scramble information is transmitted to the first and second semiconductor memories when powered on. And a register block providing the first_2 scramble information to the third and fourth semiconductor memories. According to claim 1,
The first address node of the memory controller is connected to a first address node of the first semiconductor memory, and is connected to a second address node of the second semiconductor memory. The method of claim 9,
The location of the first address node in the first semiconductor memory is different from the location of the second address node in the second semiconductor memory. For computing devices:
Processor;
A memory controller connected to the processor; And
First and second semiconductor memories connected to the memory controller to receive a common address; And
And third and fourth semiconductor memories connected to the memory controller and receiving the common address,
Each of the first and second semiconductor memories includes a plurality of memory cells arranged in rows and columns, and each row of the plurality of first memory cells in the first semiconductor memory includes a plurality of memory cells in the second semiconductor memory. 2 corresponds to the row of the same location in the memory cells,
The computing device converts the common address into the first row address of the first semiconductor memory based on the 1_1 scramble information and the 2_1 scramble information, and the common address based on the 1_1 scramble information and the 2_2 scramble information. To a second row address of the second semiconductor memory, and converting the common address to a third row address of the third semiconductor memory based on the first_2 scramble information and the second_1 scramble information, and the first_2 Converting the common address to the fourth row address of the fourth semiconductor memory based on the scramble information and the 2_2 scramble information,
The first row address is different from the third row address, and the third row address is different from the first row address. In the method of accessing the first to fourth semiconductor memories:
Receiving first_1 and first_2 scramble information;
Receiving 2_1 and 2_2 scramble information;
Receiving a common address;
Converting the common address to a first address using the 1_1 scramble information and the 2_1 scramble information, and transmitting the first address to the first semiconductor memory;
Converting the common address into a second address using the 1_1 scramble information and the 2_2 scramble information, and transmitting the second address to the second semiconductor memory;
Converting the common address into a third address using the first_2 scramble information and the second_1 scramble information, and transmitting the third address to the third semiconductor memory; And
And converting the common address to a fourth address using the 1_2 scramble information and the 2_2 scramble information, and transmitting the fourth address to the fourth semiconductor memory.

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