KR102138318B1 - Gate driving circuit and touch type liquid crystal display device including the same - Google Patents

Abstract

The present invention discloses a touch type liquid crystal display device. More specifically, the present invention provides a gate driving circuit with improved driving reliability in a liquid crystal display device in which a touch electrode is embedded and image display and touch sensing are implemented as a single display panel through time division driving, and a touch-type liquid crystal display including the same. It relates to the device.
According to an embodiment of the present invention, by further comprising a holding circuit that sustains the Q node voltage level of the gate driving circuit for a certain period of time in the output stop section, there is an effect of improving the driving reliability of the gate driving circuit and the touch type liquid crystal display. have.

Description

Gate driving circuit and touch type liquid crystal display device including the same {GATE DRIVING CIRCUIT AND TOUCH TYPE LIQUID CRYSTAL DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a touch-type liquid crystal display device, and in particular, a gate driving circuit having improved driving reliability of a liquid crystal display device in which a touch electrode is embedded and image display and touch sensing are implemented as a single display panel through time division driving, and the same It relates to a touch type liquid crystal display device.

Recently, a liquid crystal display device widely used in mobile devices, etc., is not only a method of using a general interface device such as a keyboard and a remote control device to select a predetermined object or area displayed on the screen, but also a finger or a stylus pen. The touch method of directly selecting and inputting an area of the screen is applied.

As an implementation method of a touch-type liquid crystal display, a structure in which a touch panel for sensing touch is provided separately from the display panel and attached to the display panel, or a single panel is formed by forming touch electrodes and wires on the substrate of the display panel. There is an in-cell structure to be implemented, and in particular, a touch-type liquid crystal display device to which the in-cell structure is applied is attracting attention for reasons such as a sensitive touch feeling and simplification of manufacturing processes.

1 is a diagram showing an electrode structure of a touch-type liquid crystal display to which a conventional in-cell structure is applied.

Referring to FIG. 1, a touch sensor formed on a conventional display panel includes a plurality of transmitter electrodes Tx and a plurality of receiver electrodes Rx formed to cross each other.

The illustrated electrode structure is a capacitive type, in which the display panel is composed of liquid crystal, and the common electrodes formed on the display panel are patterned in a horizontal direction to form the transmitter electrodes T1 to Tn, and are electrically connected to each other through jumping wiring. After connecting and patterning the common electrode in a vertical direction orthogonal to the horizontal direction to form the receiver electrodes R1 to Rm, the amount of change in mutual capacitance between the transmitter electrode Tx and the receiver electrode Rx It is a structure that detects.

Here, the common electrode corresponds to a pixel electrode in a pixel defined on the display panel, and when a change in mutual capacitance occurs due to a touch, it affects a gate driving signal and a data voltage for displaying an image.

FIG. 2 is a diagram showing a driving method of a conventional in-cell touch structure liquid crystal display device. In the initial stage, a display time (D) for displaying an image for one frame period and a touch sensing period for detecting a touch The method (a) of driving by time division by time, T) was applied.

However, the above-described method (a) has a limitation in that the sensitivity is low and the detection result is not accurate as touch detection is performed only in one section of one frame period. To compensate for this, the display section D and the touch sensing section T ) Is repeatedly alternately driven for 1 frame (b).

In this method b (b), the sensitivity is improved as the display section (D) and the touch sensing section (T) are repeated in a shorter period than the conventional one, but the output of the gate driving signal is temporarily stopped in the touch sensing section (T) and then the display It should be set in such a way that the gate driving signal is output again in section D.

FIG. 3 is a comparison of output waveforms of gate driving signals in a general liquid crystal display device and a liquid crystal display of the method b of FIG. 2, and the gate driving signals in the general liquid crystal display device are sequentially and continuously output by one horizontal period. On the other hand, (a), in a liquid crystal display device in which the display section (D) and the touch sensing section (T) alternate, the gate driving signal is stopped in response to the touch sensing section (T) and thus has a discontinuous waveform (b).

However, when the gate driving signal is output discontinuously due to the structure of the gate driving circuit, the potential of the Q node is lowered due to a leakage current during the intermittent period, resulting in a problem that the gate driving signal is not normally output. .

4 is a diagram schematically showing the structure of a conventional gate driving circuit. Referring to FIG. 4, a conventional gate driving circuit is pull-up in response to a gate start signal (V _ST ) or a gate driving signal of a previous stage. Up) and pull-down transistors T _PU and T _PD may be represented by a plurality of flip-flops 1 and 2 respectively turning on. The pull-up and pull-down transistors T _PU and T _PD are connected to the Q node Q and Qb node Qb of the flip-flops 1,2, respectively, and the gate driving signal VG1, VG2) is sequentially output.

Here, the driving of the gate driving circuit when an output stop period is set between the second gate driving signal VG2 and the third gate driving signal VG3 is described. First, the first flip-flop 1 is a high-level gate A high-level voltage is charged to the Q node (Q) by receiving the start signal (V _ST ), and then, as the clock signal (CLK) transitions to the high level, bootstrapping is performed to further increase the Q node (Q). As the pull-up transistor T _PU is completely turned on by being charged with a high high voltage, the gate driving circuit outputs a first gate driving signal VG1 of a high level.

At this time, the first gate driving signal VG1 is input as a gate start signal of the second flip-flop 2 so that the Q node Q of the second flip-flop 2 is pre-charged with a high-level voltage.

Subsequently, when one horizontal period (1H) elapses, as the voltage of the Qb node Qb of the first flip-flop 1 transitions to a high level, the first gate driving signal VG1 becomes a low level, and the second gate is driven. The signal VG2 is output at a high level. Accordingly, a gate start signal is input to the third flip-flop 3 so that a high-level voltage is charged to the Q node Q of the third flip-flop 3.

However, between the second gate driving signal (VG2) and the third gate driving signal (VG3), there is an output stop period for sensing the touch, so even after one horizontal period (1H) elapses, the third flip-flop (3) and The high-level clock signal CLK is not applied to the connected pull-up transistor TPU, and the operation of the gate driving circuit resumes when the output stop period ends.

At this time, all the gate driving signals VG1 to VG1 to the point when the second gate driving signal VG2 of the high level is output and 1 horizontal period 1H elapses until the point when the third gate driving signal VG3 is output to the high level. VG3) is output at a low level, and therefore, the Q node Q of the third flip-flop 3 is bootstrapped in response to the clock signal CLK after being charged to a high level, thereby forming the pull-up transistor T _PU . During turn-on, a phenomenon in which the voltage charged in the Q node Q is discharged to a certain voltage or less due to leakage current occurs.

Due to the discharge of the Q node Q, even if a high-level clock signal CLK is applied to the pull-up transistor T _PU of the third flip-flop 3, it is not completely turned on. There is a problem in that VG3) cannot be supplied to the display panel.

This is a cause of lowering the quality of the image and lowering the driving reliability of the liquid crystal display device.

The present invention has been conceived to solve the above-described problem, and the present invention improves the malfunction due to leakage current occurring in the gate driving circuit in the output stop section of the gate driving signal set for touch detection in a touch type liquid crystal display device. There is a purpose to do.

In order to achieve the above object, a gate driving circuit according to a preferred embodiment of the present invention is composed of a plurality of stages, and is a gate driving circuit set to have an output stop period between sequentially output gate driving signals, each The stage includes: a flip-flop unit connected to the D node and the rear stage to charge and discharge the Q node and the Qb node according to an input signal; An output unit outputting a gate driving signal according to voltage levels of the Q node and the Qb node; And a holding circuit unit receiving a gate start signal, an output of a front stage and a rear stage, and maintaining a voltage level of the Q node through a voltage charged in the D node connected to the output terminal.

In order to achieve the above object, in a touch-type liquid crystal display device according to a preferred embodiment of the present invention, a plurality of gate wires and data wires are cross-formed in a matrix form to define a pixel, and a touch sensor is provided in the plurality of pixels. A display panel provided; A gate driving circuit configured to sequentially supply gate driving signals to the plurality of gate wirings, and have an output stop period of the gate driving signal in a period in which the touch sensing by the touch sensor is performed; A data driving circuit for supplying a data signal to the data line in response to the gate driving signal; And a timing control circuit receiving a timing signal from an external source and generating a control signal of the gate driving circuit and the data driving circuit, wherein the gate driving circuit inputs a gate start signal, an output of a front stage, and an output of a rear stage. And a holding circuit unit configured to maintain a voltage level of a Q node that determines a high level output of the gate driving signal through a voltage charged in a D node connected to the received output terminal.

The touch-type liquid crystal display device according to an embodiment of the present invention further includes a holding circuit that maintains the Q node voltage level of the gate driving circuit for a certain period of time in the output stop period, thereby improving the driving reliability of the gate driving circuit and the touch-type liquid crystal display device. There is an effect that can be made.

1 is a diagram showing an electrode structure of a touch-type liquid crystal display to which a conventional in-cell structure is applied.
2 is a view showing a driving method of a conventional in-cell touch structure liquid crystal display device.
3 is a view comparing output waveforms of gate driving signals in a general liquid crystal display device and a liquid crystal display device of the method b of FIG. 2.
4 is a diagram schematically showing the structure of a conventional gate driving circuit.
5 is a diagram illustrating an overall structure of a touch type liquid crystal display device including a gate driving circuit according to an exemplary embodiment of the present invention.
6 is a view showing a part of the gate driving circuit of the present invention.
7 is a diagram showing an example of an equivalent circuit diagram for one stage of the gate driving circuit according to the first embodiment of the present invention.
8 is a diagram illustrating an example of an equivalent circuit diagram for one stage of a gate driving circuit according to a second embodiment of the present invention.
9 is a view showing waveforms of some of the signals applied in the output stop period of the gate driving circuit according to the prior art and according to an embodiment of the present invention.

Hereinafter, a gate driving circuit and a touch type liquid crystal display device including the same according to a preferred embodiment of the present invention will be described with reference to the drawings.

5 is a diagram illustrating an overall structure of a touch type liquid crystal display device including a gate driving circuit according to an exemplary embodiment of the present invention.

As shown, the touch-type liquid crystal display device of the present invention includes a display panel 100 for displaying an image, a timing control circuit 110 for generating a control signal for controlling each driving circuit through a timing signal, and a control Gate and data driving circuits 120 and 130 for controlling the display panel 100 in response to a signal, a touch sensing circuit 140 for detecting a touched area, and voltage of a specific node configured in the gate driving circuit 120 It includes a holding circuit 150 for maintaining the constant.

The display panel 100 is cross-formed on a transparent substrate in the form of a matrix of a plurality of gate lines GL and a data line DL, and a plurality of pixel areas PX are defined at the intersection points. A thin film transistor (not shown) is formed in each pixel region PX, and a liquid crystal cell controlled by the thin film transistor is configured to display a screen through it. In addition, one electrode included in the pixel region PX is formed of a touch sensor (not shown) that is divided and patterned to be connected to the sensing line SL.

The above-described thin film transistor is turned on when a scanning signal from the gate line GL, that is, a high-level gate driving voltage VG, is applied to transfer the data voltage applied from the data line DL to the liquid crystal capacitor. In addition, the thin film transistor is turned off when a low-level gate driving voltage is applied from the gate line GL so that the voltage charged in the liquid crystal capacitor is maintained for one frame.

The liquid crystal capacitor forms a capacitor in which a pixel electrode and a common electrode face each other, and includes a common electrode connected to a common wiring and a pixel electrode connected to a drain of the thin film transistor. In addition, the liquid crystal capacitor may be further connected to a storage capacitor for stably maintaining the voltage level of the charged pixel voltage until the next frame. In each pixel region, a gradation is realized by adjusting the light transmittance by varying the arrangement state of the liquid crystal according to the electric field formed by the pixel voltage charged through the thin film transistor and the common voltage applied to the common electrode.

In addition, a touch sensor (not shown) is formed on the display panel 100, which is made of the same metal material as the common electrode, and serves to transmit the location of the touch to the touch detection circuit, which is touched through the sensing wiring SL. It is electrically connected to the detection circuit 140.

The timing control circuit 110 receives an image-related signal applied from an external system (not shown) and timing signals such as a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, A gate control signal GCS and a data control signal DCS for controlling each driving circuit are generated.

Here, the horizontal synchronization signal Hsync is a signal indicating the time it takes to display one horizontal line of the screen, and the vertical synchronization signal Vsync is a signal indicating the time it takes to display the screen of one frame. In addition, the data enable signal DE is a signal indicating a period for supplying a pixel voltage to a pixel electrode of the display panel 100.

Further, although not shown, the timing control circuit 110 is connected to an external system (not shown) through a predetermined interface to receive an image-related signal and a timing signal output from the external system at high speed without error. An interface used for this includes a low voltage differential signal (LVDS) method or a transistor-transistor logic (TTL) interface method.

The gate driving circuit 120 is a shift register including a plurality of stages connected to the display panel 100 through a gate line GL, and includes a plurality of thin film transistors formed on one substrate of the display panel 100. The high-level gate driving signal VG is sequentially output to the gate wiring GL in response to the gate control signal GCS of the timing control circuit 120. In this case, the gate driving signal VG is not continuously output for one frame according to the touch sensitivity, but an output stop period is set at a predetermined period. As an example, the gate driving signal (VG) may be in a form in which 2 horizontal sections are continuously output and an output stop section is set between them, or 20 horizontal sections are continuously output and an output stop section is set each time. have.

The gate control signal GCS described above may include a gate start pulse, a gate shift clock, a gate output enable signal, and a separate gate start signal (V _ST). ) Can also be included.

In particular, since the gate driving circuit 120 is composed of a plurality of thin film transistors, the voltage is discharged at a specific node due to a leakage current in some of them, and a problem in that the gate driving signal VG of a normal level cannot be output may occur. have. In order to solve this problem, the gate driving circuit 120 according to the embodiment of the present invention is characterized in that it further includes a sustain circuit 127 that maintains a constant voltage level of a node discharged to the input terminal. A detailed description of the gate driving circuit 120 and the holding circuit 127 will be described later.

The gate driving circuit 120 turns on the thin film transistor provided in the pixel region PX in response to the gate control signal GCS applied from the timing control circuit 110, thereby turning on the data The data voltage VDATA of the analog waveform supplied from the driving circuit 130 is applied to the liquid crystal capacitors connected to each thin film transistor.

The data driving circuit 130 sequentially receives the digital image signal DATA in response to the data control signal DCS input from the timing control circuit 110, and refers to the reference voltage, and the analog data voltage ( VDATA). The data voltage is latched for one horizontal section (1H) and is simultaneously input to the display panel 100 through all data lines DL.

The above-described data control signal DCS may include a source start pulse, a source shift clock, and a source output enable signal.

The touch detection circuit 140 detects the presence or absence of a touch on the display panel 100 in response to a touch control signal (TCS) applied from the timing control circuit 110 and obtains coordinates on the display panel 100. do. The touch detection circuit 140 may include a low pass filter (LPF), an A/D converter, and a coordinate extractor. The LPF removes a high frequency component from the sensing signal included in the sensing result transmitted from the sensing wiring connected to the touch sensor, and extracts and outputs only the touch component. The A/D converter converts the filtered detection signal in the analog form output from the LPF into a digital form. The coordinate extraction unit serves to obtain the touched coordinates based on the sensing signal.

In particular, the touch detection circuit 140 stops output, which is a section in which the gate driving signal VG is not output in order to minimize the influence on the touch sensor according to the change of the gate driving signal VG and the data voltage VDATA. The detection signal is received in the section.

According to this structure, the liquid crystal display device of the present invention enables the gate driving circuit to be stably driven through a holding circuit that continuously maintains the voltage level of a specific node of the gate driving circuit in the output stop period.

Hereinafter, a structure and driving of a gate driving circuit according to an embodiment of the present invention will be described with reference to the drawings. In the following description, a method of driving a gate driving circuit will be described, for example, when two gate wirings are continuously driven and then set to have a predetermined output stop period.

6 is a view showing a part of the gate driving circuit of the present invention.

Referring to FIG. 6, the gate driving circuit 120 of the present invention receives a power supply voltage VDD and a ground voltage VSS, and applies gate driving signals VG1 to VGn to the gate wiring according to the clock signal CLK. It is composed of a shift register including a plurality of output stages.

In this structure, when a high-level gate start signal V _ST is applied to the first stage, the Q node inside the first stage is charged to a high level, and when a high-level clock signal CLK is applied, the first stage One stage outputs a high level first gate driving signal VG1 through a gate line for one horizontal period 1H.

At this time, the first gate driving signal VG1 is input to the second stage as a gate start signal, so that the Q node of the second stage is charged.

Next, when the first gate driving signal VG1 reaches the low level, the high level clock signal CLK is applied to the second stage, and accordingly, the second stage drives the high level second gate through the gate wiring. The signal VG2 is output.

Further, the second gate driving signal VG2 is input to the third stage as a gate start signal, and at the same time, the second gate driving signal VG2 is input to the first stage as a signal for discharging the Q node and charging the Qb node.

Subsequently, the gate driving circuit enters the output stop period for sensing the touch for a predetermined period, and accordingly, the gate driving circuit does not output a high-level gate driving signal. At this time, the third stage is in a state where a high-level gate start signal is already applied, so the Q node is charged to a high level, and even if a leakage current occurs in the thin film transistor connected to the Q node, the input terminal of the gate start signal is maintained. The high-level voltage is maintained until the high-level clock signal CLK is input to the third stage as the Q node is continuously charged even in the output stop period by the circuit.

Hereinafter, the structure and driving method of the gate driving circuit according to the first embodiment of the present invention will be described with reference to an equivalent circuit diagram of the gate driving circuit.

7 is a diagram showing an example of an equivalent circuit diagram for one stage of the gate driving circuit according to the first embodiment of the present invention.

As shown, one stage (STAGE) of the gate driving circuit of the present invention is a flip-flop unit 121 for charging and discharging the Q node (Q) and the Qb node (Qb) according to the input signal, and the Q node (Q ) And a gate driving signal (VG) according to the voltage level of the Qb node (Qb), and a holding circuit (127) that maintains the voltage level of the Q node (Q) in the output stop period. do.

Particularly, a plurality of thin film transistors constituting the flip-flop part 121 may have various connection structures, and the drawing shows an example using a minimum number of thin film transistors, but is not limited thereto.

The flip-flop unit 121 is turned on by the D node (D) to charge the Q node (Q) and a second thin film transistor (T2) connected to the diode to charge the Qb node (Qb). ), a third thin film transistor T3 that discharges the Qb node Qb according to charging of the Q node Q, and a fourth thin film transistor that discharges the Q node Q according to the output VEND of the rear stage. (T4) and a fifth thin film transistor (T5) for discharging the Q node (Q) according to the charge of the Qb node (Qb).

In describing the connection structure of the device, a D node D is connected to a gate of the first thin film transistor T1, and a drain and a source are connected to a power voltage VDD terminal and a Q node Q, respectively.

In the second thin film transistor T2, a gate and a drain are connected to a power supply VDD terminal, and a source is connected to a Qb node Qb.

The third thin film transistor T3 has a gate connected to the Q node Q, and a drain and a source connected to the Qb node Qb and the ground voltage VSS, respectively.

The fourth thin film transistor T4 has a gate connected to the output V _END of the rear stage, and a drain and a source connected to the Q node Q and the ground voltage VSS, respectively.

The fifth thin film transistor T5 has a gate connected to a Qb node Qb, and a drain and a source connected to the Q node Q and the ground voltage VSS, respectively.

The output unit 125 is turned on by a Q node (Q) and a clock signal (CLK) to output a high-level gate driving signal (VG), a pull-up thin film transistor (T _PU ) and a Qb node (Qb). And a pull-down thin film transistor T _PD outputting a low-level gate driving signal VG.

The pull-up transistor T _PU has a gate connected to a Q node Q, and a drain and a source connected to a clock signal CLK terminal and an output terminal of the gate driving signal VG, respectively.

The pull-down transistor T _PD has a gate connected to the Qb node Qb, and a drain and a source connected to the gate driving signal VG output terminal and the ground voltage VSS terminal, respectively.

The holding circuit unit 127 is turned on by the gate start signal V _ST or the output of the front stage to charge the D node D to a high level, and the first holding thin film transistor T _M1 and the output of the rear stage And a second storage thin film transistor T _{M2 that} is turned on and discharges the D node D to a level lower than at least a high level.

The first sustaining thin film transistor T _M1 has a gate connected to the gate start signal V _ST or a front gate driving signal output terminal, and a drain and a source connected to a power voltage VDD and a D node D, respectively. .

The second storage thin film transistor T _M2 has a gate connected to a rear gate driving signal V _END output terminal, and a drain and a source connected to a D node (D) and a ground voltage (VSS) terminal, respectively.

In this structure, the Q node (Q) is particularly easily discharged by the leakage current through the fifth thin film transistor (T5), which is the second and third thin film that controls the turn-on of the fifth thin film transistor (T5). This is because the voltage level at the low level of the Qb node Qb is set slightly higher than the ground voltage VSS as the transistors T2 and T3 are all N-MOS transistors.

However, when the gate start signal V _ST is applied, the Q node Q is charged, and the first thin film transistor T1 is charged by the voltage charged in the D node D when the corresponding stage corresponds to the output stop section. As the Q node Q is turned on and continuously charged, the discharge of the Q node Q due to the leakage current is compensated.

Hereinafter, a method of driving a gate driving circuit according to a first embodiment of the present invention will be described with reference to the drawings.

First, since the second thin film transistor T2 is always turned on when the previous stage output or the gate start signal V _ST is not applied, the high level voltage is charged to the Qb node Qb, and the fifth thin film transistor (T5) is turned on to discharge the voltage of the Q node Q to a low level. Accordingly, the pull-down transistor T _PD is turned on to output a low-level gate driving signal VG.

Then, the shear stage or a gate start signal (V _ST) is when a high level is applied to the first holding thin film transistor (T _M1), a first holding a thin film transistor (T _M1) is turned on and charge the D node, a high level voltage Accordingly, the first thin film transistor T1 is turned on and the Q node Q is charged with a high level voltage. As the Q node Q is charged, the third thin film transistor T3 is also turned on to discharge the Qb node Qb to a level lower than at least the high level.

Thereafter, when the previous stage or the gate start signal V _ST becomes a low level, and the current stage is a section in which the gate driving signal VG is output, the high level clock signal CLK is applied, so that the Q node Q is The voltage is bootstrapped so that the pull-up thin film transistor T _PU is completely turned on, and a high-level gate driving signal VG is output. At the same time, the third thin film transistor T3 is also completely turned on to discharge the Qb node Qb to a low level so that the pull-down thin film transistor T _PD can continue to be turned off.

On the other hand, when the current stage corresponds to the output stop section, the Q node Q is in a state of being charged with a high level voltage, and the voltage level of the Qb node Qb is the second thin film transistor T2 as the third thin film transistor is turned on. ) And the threshold voltage of the third thin film transistor T3, but the voltage level is somewhat higher than the ground voltage. At the same time, the first and second holding thin film transistors T _M1 and T _M2 are turned off, and the first thin film transistor T1 is turned on by the D node D charged to the high level. . Accordingly, the voltage level discharged by applying the power voltage VDD to the Q node Q is compensated.

Thereafter, when the high level clock signal CLK is applied to the pull-up thin film transistor T _PU , the high level gate driving signal VG is output.

Next, after one horizontal period (1H), when the rear gate driving signal V _END is applied from the rear stage, the second sustaining thin film transistor T _M2 and the fourth thin film transistor T4 are turned on and the D node D ) And Q node (Q) are discharged to a low level, and the third thin film transistor (T3) is turned off, the fifth thin film transistor (T5) is turned on to accelerate the discharge of the Q node (Q), the pull-down thin film The transistor T _PD is turned on to output a low-level gate driving signal VG.

Hereinafter, the structure and driving method of the gate driving circuit according to the second embodiment of the present invention will be described with reference to an equivalent circuit diagram of the gate driving circuit. In the second embodiment of the present invention, there is an advantage of stably discharging the D node D by controlling the second sustaining thin film transistor at the power voltage level.

8 is a diagram illustrating an example of an equivalent circuit diagram for one stage of a gate driving circuit according to a second embodiment of the present invention.

One stage of the gate driving circuit according to the second embodiment has the same structure of the flip-flop part 221 and the output part 225, but the Qb node Qb is the second holding thin film of the holding circuit part 227 The difference is that it is connected to the gate of the transistor T _M2 .

The flip-flop part 221 is turned on by the D node D to charge the Q node Q, and the second thin film transistor T2 is diode-connected to charge the Qb node Qb. ), a third thin film transistor T3 that discharges the Qb node Qb according to charging of the Q node Q, and a fourth thin film that discharges the Q node Q according to the output of the rear stage (V _END ). It includes a transistor T4 and a fifth thin film transistor T5 that discharges the Q node Q according to the charging of the Qb node Qb.

The output unit 225 is turned on by a Q node (Q) and a clock signal (CLK) and is turned on by a pull-up thin film transistor (T _PU ) that outputs a high-level gate driving signal (VG) and a Qb node (Qb). And a pull-down thin film transistor T _PD outputting a low-level gate driving signal VG.

The holding circuit unit 227 is turned on by the gate start signal V _ST or the output of the previous stage to charge the D node D to a high level, and the first holding thin film transistor T _M1 and the Qb node Qb are And a second storage thin film transistor T _M2 that is turned on by the output and discharges the D node D to a level lower than at least a high level.

In this structure, the Q node (Q) is particularly easily discharged by the leakage current through the fifth thin film transistor (T5), which is the second and third thin film that controls the turn-on of the fifth thin film transistor (T5). This is because the voltage level at the low level of the Qb node Qb is set slightly higher than the ground voltage VSS as the transistors T2 and T3 are all N-MOS transistors.

However, when the gate start signal V _ST is applied, the Q node Q is charged, and the first thin film transistor T1 is charged by the voltage charged in the D node D when the corresponding stage corresponds to the output stop section. As the Q node Q is turned on and continuously charged, the discharge of the Q node Q due to the leakage current is compensated.

Hereinafter, a method of driving a gate driving circuit according to a second embodiment of the present invention will be described with reference to the drawings.

First, since the second thin film transistor T2 is always turned on in a state in which the previous stage or the gate start signal V _ST is not applied, a high level voltage is charged to the Qb node Qb, and the fifth thin film transistor ( T5) is turned on to discharge the voltage of the Q node Q to a low level. Accordingly, the pull-down transistor T _PD is turned on to output a low-level gate driving signal VG.

Then, the shear stage or a gate start signal (V _ST) is when a high level is applied to the first holding thin film transistor (T _M1), a first holding a thin film transistor (T _M1) is turned on and charge the D node, a high level voltage Accordingly, the first thin film transistor T1 is turned on and the Q node Q is charged with a high level voltage. As the Q node Q is charged, the third thin film transistor T3 is also turned on to discharge the Qb node Qb to a level lower than at least the high level.

Thereafter, when the previous stage or the gate start signal V _ST becomes a low level, and the current stage is a section in which the gate driving signal VG is output, the high level clock signal CLK is applied, so that the Q node Q is The voltage is bootstrapped so that the pull-up thin film transistor T _PU is completely turned on, and a high-level gate driving signal VG is output. At the same time, the third thin film transistor T3 is also completely turned on to discharge the Qb node Qb to a low level so that the pull-down thin film transistor T _PD can continue to be turned off.

On the other hand, when the current stage corresponds to the output stop period, the first storage thin film transistor T _M1 is turned off, and the Q node Q is charged with a high level voltage. In addition, as the third thin film transistor is turned on, the voltage level of the Qb node Qb is determined according to the threshold voltages of the second thin film transistor T2 and the third thin film transistor T3, but the voltage level is slightly higher than the ground voltage. The second storage thin film transistor T _M2 is also turned off. Accordingly, the first thin film transistor T1 continues to be turned on by the voltage level of the D node D charged to the high level. Accordingly, the voltage level discharged by applying the power voltage VDD to the Q node Q is compensated.

Thereafter, when the high level clock signal CLK is applied to the pull-up thin film transistor T _PU , the high level gate driving signal VG is output.

Next, after one horizontal period (1H), when the rear gate driving signal V _END is applied from the rear stage, the second sustaining thin film transistor T _M2 and the fourth thin film transistor T4 are turned on and the D node D ) And Q node (Q) are discharged to a low level, and the third thin film transistor (T3) is turned off, the fifth thin film transistor (T5) is turned on to accelerate the discharge of the Q node (Q), the pull-down thin film The transistor T _PD is turned on to output a low-level gate driving signal VG.

9 is a view showing waveforms of some of the signals applied in the output stop period of the gate driving circuit according to the prior art and according to an embodiment of the present invention.

First, in the conventional gate driving circuit, when the gate start signal (V _ST ) or the previous stage output signal reaches a high level in an arbitrary stage corresponding to the output stop section, the Q node Q is charged and the Qb node Qb Is discharged, and when the signal reaches a low level, the voltage level of the Q node Q gradually decreases due to the leakage current. Thereafter, even when the high-level clock signal CLK is applied, the low-level state is maintained as it is without bootstrapping.

On the other hand, in the gate driving circuit according to the embodiment of the present invention, when the gate start signal (V _ST ) or the output signal of the previous stage reaches a high level in an arbitrary stage, the Q node Q is charged and the Qb node Qb ) Is discharged, and even if the signal goes to a low level, the D node (not shown) is held at a high level, so that the voltage of the Q node Q is also maintained. Thereafter, as the high-level clock signal CLK is applied, it is bootstrapped (BT) to output a normal gate driving signal.

Although many matters are specifically described in the above description, this should be interpreted as an illustration of a preferred embodiment rather than limiting the scope of the invention. Therefore, the invention should not be determined by the described embodiments, but should be defined by the claims and equivalents to the claims.

PX: Pixel GL: Gate wiring
DL: Data wiring SL: Sensing wiring
GCS: Gate control signal DCS: Data control signal
TCS: Touch control signal DATA: Video signal
VDATA: Data voltage Hsync: Horizontal synchronization signal
Vsync: Vertical synchronization signal DE: Data enable signal
100: display panel 110: timing control circuit
120: gate driving circuit 127: holding circuit
130: data driving circuit 140: touch sensing circuit

Claims (11)

As a gate driving circuit composed of a plurality of stages and set to have an output stop section between the sequentially output gate driving signals,
Each stage,
A flip-flop unit connected to the D node and the rear stage to charge and discharge the Q node and the Qb node according to an input signal;
An output unit outputting a gate driving signal according to voltage levels of the Q node and the Qb node; And
A sustain circuit unit charging the node D based on one of a gate start signal and an output of a previous stage, and discharging the node D based on an output of the later stage or a voltage of the node Qb,
A first thin film transistor that is turned on by the D node to charge the Q node; A second thin film transistor diode-connected to charge the Qb node; A third thin film transistor discharging the Qb node according to the charging of the Q node; A fourth thin film transistor discharging the Q node according to an output of a rear stage; And a fifth thin film transistor discharging the Q node according to charging of the Qb node.
A pull-up thin film transistor that is turned on by the voltage and a clock signal of the Q node to output the gate driving signal at a high level; And a pull-down thin film transistor turned on by the voltage of the Qb node to output the gate driving signal at a low level,
The holding circuit unit comprises: a first storage thin film transistor turned on by a gate start signal or an output of a previous stage to charge the D node to a high level; And a second storage thin film transistor that is turned on by an output of a subsequent stage or a voltage of the Qb node to discharge the D node to a level lower than at least a high level. delete delete delete delete A display panel in which a plurality of gate lines and data lines are cross-formed in a matrix form to define a pixel, and a touch sensor is provided in the plurality of pixels;
A gate driving circuit configured to sequentially supply gate driving signals to the plurality of gate wirings, and have an output stop period of the gate driving signal in a period in which the touch sensing by the touch sensor is performed;
A data driving circuit for supplying a data signal to the data line in response to the gate driving signal; And
A timing control circuit receiving a timing signal from an external source and generating control signals for the gate driving circuit and the data driving circuit,
The gate driving circuit,
A flip-flop unit connected to the D node and the rear stage to charge and discharge the Q node and the Qb node according to an input signal;
An output unit for outputting the gate driving signal according to voltage levels of the Q node and Qb node; And
And a sustain circuit unit charging the D node based on one of a gate start signal and an output of a previous stage and discharging the D node based on an output of a subsequent stage or a voltage of the Qb node,
A first thin film transistor that is turned on by the D node to charge the Q node; A second thin film transistor diode-connected to charge the Qb node; A third thin film transistor discharging the Qb node according to the charging of the Q node; A fourth thin film transistor discharging the Q node according to an output of a rear stage; And a fifth thin film transistor discharging the Q node according to charging of the Qb node,
A pull-up thin film transistor that is turned on by the voltage and a clock signal of the Q node to output the gate driving signal at a high level; And a pull-down thin film transistor turned on by the voltage of the Qb node to output the gate driving signal at a low level,
The holding circuit unit comprises: a first storage thin film transistor turned on by a gate start signal or an output of a previous stage to charge the D node to a high level; And a second sustaining thin film transistor that is turned on by an output of a subsequent stage or a voltage of the Qb node to discharge the D node to a level lower than at least a high level,
The charged D node maintains a voltage level of a Q node that determines a high level output of the gate driving circuit. The method of claim 6,
The holding circuit unit,
A touch-type liquid crystal display device that maintains the voltage level of the Q node in the output stop period. delete delete delete delete

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