KR102118179B1 - Manufacturing method of display apparatus and display apparatus manufactured by that method - Google Patents

Abstract

The present invention relates to a method and a device for manufacturing a display device, which are applied with a technology of separating R, G, and B chips formed on each wafer through etching, a technology of transferring each of the separated chips to a carrier substrate, a technology of selectively transferring a part of each of the chips transferred to the carrier substrate to a thermal peeling carrier substrate, and a technology capable of sequentially transferring each of the chips transferred to the thermal peeling carrier substrate to a display panel. According to an embodiment of the present invention, the method of the present invention comprises: a chip forming step of forming a plurality of chips and a protective layer for passivating the plurality of chips on a wafer; an etching step of etching the protective layer for each of the chips on the wafer; a carrier substrate attachment step of attaching a chip array, which is etched on the wafer and arranged in a matrix, to a carrier substrate; a wafer removal step of removing the wafer from the chip array; a transfer step of arranging a thermal peeling carrier substrate having a material peeled by heat on the chip array, and applying predetermined heat to the thermal peeling carrier substrate to selectively transfer a part of the chip array transferred to the carrier substrate to the thermal peeling carrier substrate; and a display panel transfer step of transferring to a display panel the part of the chip array transferred to the thermal peeling carrier substrate.

Description

A manufacturing method of a display device and a display device manufactured by the method{MANUFACTURING METHOD OF DISPLAY APPARATUS AND DISPLAY APPARATUS MANUFACTURED BY THAT METHOD}

The present invention is a technology for separating R chips, G chips, and B chips formed on each wafer through etching, a technique for transferring each separated chip to a carrier substrate, and thermally peeling a part of each chip transferred to the carrier substrate The present invention relates to a method and apparatus for manufacturing a display device to which a technology for selectively transferring, and a technology capable of sequentially transferring each chip transferred to a heat-exfoliating carrier substrate to a display panel is applied.

A light emitting diode (LED) is one of light emitting devices that emit light when a current is applied. The light-emitting diode can emit high-efficiency light at a low voltage, and thus has excellent energy saving effect.

In recent years, the luminance problem of light emitting diodes has been greatly improved, and has been applied to various devices such as a backlight unit of a liquid crystal display device, a display panel, a display device, and a home appliance.

The size of the micro light-emitting diode (μ-LED) is very small, from 1 to 100 μm, and approximately 25 million pixels are required to realize a 40-inch display device.

Therefore, there is a problem that it takes at least a month in time as a simple pick and place method to make one 40-inch display device.

Existing micro light-emitting diodes (μ-LEDs) are manufactured in plural on a sapphire substrate, and then, by a mechanical transfer method, pick & place, micro light-emitting diodes are individually glass or flexible substrates. Is transferred.

Since the micro light emitting diodes are picked up and transferred one by one, it is referred to as a 1:1 pick and place transfer method.

However, since the size of the micro light emitting diode chip fabricated on the sapphire substrate is small and the thickness is thin, the chip is damaged during the pick and place transfer process of transferring the micro light emitting diode chips one by one, the transfer fails, or the alignment of the chip ( Alignment has failed or a problem such as a tilt of the chip has been generated.

In addition, there is a problem that the time required for the transcription process takes too long.

Republic of Korea Patent Publication 10-2019-0096256

The present invention provides a method of selectively transferring a plurality of chips formed or disposed on a base substrate using predetermined heat and pressure.

In addition, it is intended to provide a method for selectively transferring some of a plurality of chips transferred from a wafer to a carrier substrate to a thermal peeling carrier substrate.

In addition, it is intended to provide a method capable of improving the selective chip transfer rate from a carrier substrate to a thermally peeled carrier substrate.

In addition, a display device is manufactured by using a technology of selectively transferring some of the plurality of chips transferred from a wafer to a carrier substrate to a thermal peeling carrier substrate and a technology of sequentially transferring a chip transferred to a thermal peeling carrier substrate to a display panel. I want to provide a way to do it.

In addition, if the chips are separated from each wafer in matrix units by a dicing process, damage to the EPI and reduction of net dies are caused by laser heat. On the other hand, by using the etching process and the LLO process, it is intended to provide a chip separation method that can fundamentally block EPI damage and increase the production efficiency of the LED chip.

In addition, it is intended to provide a method for quickly manufacturing a micro LED-based display device and minimizing transcription errors.

In addition, it is intended to provide a method for manufacturing a display device having various sizes and various pitches between pixels.

Also, it is intended to provide a method of using a wafer having as many RGB pixels as possible on a limited area regardless of the resolution of the display device.

In addition, it is intended to provide a method for quickly manufacturing a large-area display device.

The problem to be solved of the present invention is not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. will be.

In the transfer method using the thermal peeling substrate according to the embodiment of the present invention, a plurality of chips formed or disposed on the base substrate are transferred onto a thermal peeling substrate containing a material peeled off by heat.

A method of manufacturing a display device according to an embodiment of the present invention includes: a chip forming step of forming a plurality of chips and a protective layer for passivating a plurality of chips on a wafer; An etching step of etching the protective layer for each chip on the wafer; Attaching a chip array etched on the wafer and arranged in a matrix to a carrier substrate, a carrier substrate attaching step; A wafer removal step of removing the wafer from the chip array; A thermal peeling carrier substrate having a material peeled off by heat is disposed on the chip array, and a predetermined heat is applied to the thermal peeling carrier substrate to apply some of the chip array of the chip array transferred to the carrier substrate to the thermal peeling carrier substrate Selectively transferring, a transfer step; And a display panel transfer step of transferring the part of the chip array transferred to the heat exfoliating carrier substrate to a display panel.

Further, the display device according to the present invention may be manufactured by the above-described method for manufacturing a display device.

According to the above-described configuration of the present invention, there is an advantage in that a plurality of chips formed or disposed on the base substrate can be selectively transferred using a predetermined heat and pressure.

In addition, the technology of separating the R chips, G chips, and B chips formed on each wafer through etching, a technique of transferring each separated chip to a carrier substrate, and a part of each chip transferred to the carrier substrate as a thermal peeling carrier substrate There is an advantage of selectively transferring technology and sequentially transferring each chip transferred to a heat-exfoliating carrier substrate to a display panel.

In addition, there is an advantage that can improve the selective chip transfer rate from the carrier substrate to the thermal peeling carrier substrate.

In addition, in the process of separating the chips formed on the wafer into matrix units, an etching process is used instead of a conventional laser dicing process, thereby preventing EPI damage due to the heat of the laser and sawing (mechanical dicing) ) In the process, it is possible to bring down the net die due to the large dicing area due to the thickness of the saw blade, and it is possible to prevent the decrease in the light efficiency and the increase in defects of the micro LED due to particle contamination in the dicing process in advance. Brings

In addition, since a plurality of selected light-emitting elements can be quickly transferred to a display panel at a time without controlling the micro-level light-emitting elements one by one, there is an advantage of significantly reducing manufacturing cost and time of the display device.

In addition, there is an advantage in that a display device having various sizes and various pitches between chips can be manufactured.

In addition, since each wafer having as many RGB chips as possible on a limited area regardless of the resolution of the display device is used, the manufacturing cost of the wafer can be reduced, and a color conversion layer forming process is not required.

In addition, when manufacturing a large-area display device, there is an advantage in that the transfer method can be rapidly produced by repeatedly performing a change of position.

1 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention.
2 is a diagram in which R chips, G chips, and B chips are formed on each wafer according to an embodiment of the present invention.
3 is a process diagram of growing each Epi on each wafer according to an embodiment of the present invention.
4 is a process diagram of etching each chip formed on each wafer in one chip unit according to an embodiment of the present invention.
5 is a process diagram of transferring the etched chip of FIG. 4 from the wafer to the carrier substrate, and FIG. 6 is a process diagram of removing the wafer by the LLO technique.
6 is a process diagram of removing the wafer by the LLO technique.
7A to 7C are process diagrams for explaining the step (S150) of preparing the heat-release carrier substrate shown in FIG. 1.
8 to 10 are exemplary views for explaining a process of selectively transferring the chip array shown in FIG. 1 from a carrier substrate to a thermally peeled carrier substrate.
11 is the same process as that of FIGS. 8 to 10, some G LED chips 100G among the G LED chip arrays formed on the second carrier substrate 210R are selectively transferred to the second thermal peeling carrier substrate 220G. This is a drawing showing what has been transferred.
12 is the same process as that of FIGS. 8 to 10, some of the B LED chip 100B among the B LED chip arrays formed on the third carrier substrate 210B are selectively transferred to the third thermal peeling carrier substrate 220G. This is a drawing showing what has been transferred.
13 to 14 are exemplary views of a process in which the chip array is secondarily transferred from the first heat-peel carrier substrate to the display panel.
15 to 16 are other exemplary views of a process in which the chip array is secondarily transferred from the second thermal release carrier substrate to the display panel.
17 to 18 are other exemplary views of a process in which the chip array is secondarily transferred from the third thermal release carrier substrate to the display panel.

In the description of the embodiment, in the case of being described as being formed on the "top (top) or bottom (bottom)" of each component, the upper (upper) or lower (bottom) two components are in direct contact with each other Or one or more other components are disposed between two components.

In addition, when expressed as "up (up) or down (down)", it may include the meaning of the downward direction as well as the upward direction based on one component.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity. Also, the size of each component does not entirely reflect the actual size.

The chip, CSP, LED pixel CSP, and LED sub-pixel CSP used in the present invention can be defined as follows.

The chip is a concept including all of an LED chip, an RGB chip, an R chip, a G chip, a B chip, a Mini LED chip, and a Micro LED chip. Hereinafter, for convenience of description, the chip will be described as an R chip, a G chip, or a B chip, but it should be noted that the chip is not limited to an R chip, a G chip, or a B chip.

CSP (Chip Scale Package) is a package that has recently attracted much attention in the development of a single chip package (single chip package) means a single chip package having a semiconductor/package area ratio of 80% or more.

The LED pixel CSP refers to a single package in which one LED pixel is CSP packaged with a red LED, a green LED, and a blue LED as one pixel unit.

The LED sub-pixel CSP refers to a single package in which each of the red LED, green LED, and blue LED is packaged in one sub-pixel unit and CSP packaged in one LED sub-pixel unit.

The luminous body formed on the wafer may be defined as an LED chip.

1 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention.

Referring to FIG. 1, in the method of manufacturing a display device according to an embodiment of the present invention, forming a plurality of chips on each wafer (S110), etching the wafer for each chip by one chip ( Etching (S120), attaching the chip array of each wafer separated in chip units to the carrier substrate (S130), removing the wafer by laser lift off (LLO) process (S140), thermal peeling Preparing a carrier substrate (S150), selectively transferring the chip array from the carrier substrate to the thermally delaminated carrier substrate (S160), sequentially transferring the chip array selectively transferred to the thermally delaminated carrier substrate to the display panel (S170) and the step of removing the thermal release carrier substrate (S180).

Steps S110, S120, S130, S140, S150, S160, S170, and S180 will be described in detail below with reference to the accompanying drawings.

2 is a diagram in which chips are formed on each wafer according to an embodiment of the present invention.

As illustrated in FIG. 2, the embodiment of the present invention describes three wafers each formed with R chips, G chips, and B chips, but is not limited thereto.

Referring to FIG. 2, a plurality of light emitting elements 11R, 11G, and 11B that emit light of the same wavelength band is formed on each one of the wafers 10R, 10G, and 10B.

Here, the light emitting elements 11R, 11G, and 11B may be light emitting chips that emit red, green, and blue light.

The plurality of light emitting elements 11R, 11G, and 11B may be arranged at equal intervals along a plurality of rows and columns on each wafer 10R, 10G, and 10B.

Since the light-emitting elements 11R, 11G, and 11B arranged at equal intervals are subsequently transferred to the display panel in the row or column direction, the manufacturing cost of the light-emitting element can be lowered by efficiently utilizing the entire area of a relatively expensive wafer.

On the other hand, after forming a plurality of chips on each one wafer (10R, 10G, 10B), the wafer for each chip can be separated for each chip through an etching process.

The pitch W between chips formed on each of the wafers 10R, 10G, and 10B is preferably the same as the pitch between chips formed on the display panel or is determined by a multiple of a proportional constant of a predetermined value.

This can facilitate transfer when selectively transferring the chips from the thermal peeling carrier substrate, which will be described later, to the display panel in matrix units.

3 is a process diagram of growing each Epi on each wafer according to an embodiment of the present invention.

3, epi wafers 11R, 11G, and 11B emitting predetermined light are grown on one surface of each of the three wafers 10R, 10G, and 10B.

Here, the wafers 10R, 10G, and 10B may be any one of sapphire (Al2O3), silicon, gallium arsenide (GaAs), gallium nitride (GaN), and zinc nitride (ZnN). However, the present invention is not limited thereto, and any substrate that can be used as a wafer can be used.

Protection to form pads 14r, 14g, 14b on each of the grown epis 11R, 11G, 11B, and passivation of epis 11R, 11G, 11B and pads 14r, 14g, 14b The layer 13 is formed.

Here, the pads 14r, 14g, and 14b are not expanded, and may have a size and shape of a general pad.

When forming the protective layer 13, it is preferable to form the pads 14r, 14g, 14b so as to be exposed to the outside of the protective layer 13 in expanding the area of the pad.

In FIG. 3, cross-sectional views of the AA section and the BB section in FIG. 1 are respectively expressed, and preferably, a pair of (+) and (-) electrodes per chip is formed under the Epi layer. It can be formed up and down and, if necessary, can be formed left and right.

The light emitters formed on the wafers 10R, 10G, and 10B are electrically separated on a chip-by-chip basis, and are referred to as LED chips in the present invention. do.

4 is a process diagram of etching each chip formed on each wafer in one chip unit according to an embodiment of the present invention.

Referring to FIG. 4, epitaxial 11R, 11G, and 11B and pads 14r, 14g, and 14b are formed on the wafers 10B, 10G, and 10B as shown in FIG. 3, and the protective layer 13 is formed for each chip. Etching to form a plurality of physically separated chips (100R, 100G, 100B). Here, each chip and the protective layer 13 surrounding the chip will be referred to as a chip in this specification. Of course, each chip and the protective layer 13 surrounding the chip may also be referred to as a pixel CSP or sub-pixel CSP.

Here, in the process of etching for each chip (100R, 100G, 100B), wet or dry etching may be applied, and the shape of the LED chip is defined by etching, wherein the wafers 10B, 10G, and 10B are It will remain as it is.

In the following drawings, one chip 100R, 100G, 100B is illustrated as a chip 100R, 100G, 100B formed in FIG. 4, but is not limited thereto, and the chip etched in the row and column directions in FIG. 2 It may be an (100R, 100G, 100B) array.

Each chip 100R, 100G, and 100B may have a flip chip structure in which a wire is unnecessary.

Electrical connection is possible with pads 14r, 14g, 14b instead of wire, and each of the chips 100R, 100G, 100B emits light of various colors according to an external control signal through pads 14r, 14g, 14b. Can be.

In addition, in the present invention, each of the chips 100R, 100G, and 100B can be packaged in a compact form of a new concept produced in the form of a CSP by configuring subpixels for each R, G, and B.

The R chip 100R, the G chip 100G, and the B chip 100B may constitute one light emitting device or a light emitting body.

By attaching each chip (100R, 100G, 100B) to the carrier substrate in a plurality of row and column directions, a pre-process can be performed to transfer the chip array, and selectively transfer from the carrier substrate to the thermally peeled carrier substrate and , The chip array arranged on the heat-exfoliating carrier substrate may be sequentially transferred to a display panel to be described later.

As shown in FIG. 4, a process of removing wafers is performed by attaching chip arrays etched in the form of chips 100R, 100G, and 100B on each wafer 10B, 10G, and 10B to a carrier substrate, and then heats from the carrier substrate. The process of selectively transferring to a release carrier substrate and sequentially transferring to a display panel will be described.

The following figures are described on the basis of row (horizontal) arrangement in a chip array matrixed on the wafer of FIG. 1.

5 is a process diagram of transferring the etched chip of FIG. 4 from the wafer to the carrier substrate, and FIG. 6 is a process diagram of removing the wafer by the LLO technique.

5 and 6 is a process for removing the wafer (10R, 10G, 10B) to transfer the etched chip to the display panel.

Referring to FIG. 5, after the chip is separated in the matrix direction by etching (as shown in FIG. 4 ), the carrier substrates 210R, 210G, and 210B are placed in the opposite direction of the wafers 10R, 10G, and 10B (100R, 100G, 100B). That is, the carrier substrates 210R, 210G, 210B are attached to the pads 14r, 14g, 14b side of the chips 100R, 100G, 100B.

Here, the carrier substrates 210R, 210G, and 210B may also be referred to as a'base substrate'. Hereinafter, for convenience of description, it will be referred to as a carrier substrate.

Referring to FIG. 6, when the wafers 10R, 10G, and 10B are removed by a laser lift off (LLO) process in the same state as in FIG. 5, the chips 100R, 100G, and 100B are first carrier substrates 210R, 210G , 210B), and in this case, the directions of the chips 100R, 100G, and 100B are disposed with the light emitting body exposed in the opposite direction.

The carrier substrates 210R, 210G, and 210B include a first carrier substrate 210R formed with an R LED chip array, a second carrier substrate 210G formed with a G LED chip array, and a third carrier substrate formed with an array of B LED chips. It may include (210B).

Prior to describing the process of selectively transferring the light-emitting body from the carrier substrates 210R, 210G, and 210B to the thermal release carrier substrate, a step (S150) of preparing the thermal release carrier substrate will be described.

7A and 7B are process diagrams for explaining the step (S150) of preparing the thermal release carrier substrate 220 shown in FIG. 1.

In this specification, the thermal release carrier substrate 220 may also be referred to as a “thermal release substrate”. Therefore, the thermal peeling carrier substrate 220 may also be interpreted as a thermal peeling substrate, hereinafter referred to as thermal peeling carrier substrate 220 for convenience of description.

Referring to (a) and (b) of FIG. 7, the base layer 223 is formed on the substrate 221, and the adhesive layer 227 having the material 225 peeled off by heat on the base layer 223 To form.

The substrate 221 may be made of any one of glass, quartz, synthetic quartz, and metal. The substrate 221 is preferably made of a hard material that is not as flexible as possible.

The base layer 223 is a resin material, for example, polyester (PET), PP (polypropylene), PE (polyethylene), PVC (polyvinyl chloride), polyimide (PI), PEN (polyethylene naphthalene), It may be any one of a film coated with polytetrafluoro ethylene (PTFE) on glass fiber, ETFE (ethylene terafluoroethylene), PEEK (polyether ether keton), PPS (polyphenylene sulfide), or PES (polyether sulfone).

The material 225 that is peeled off by heat may be a material that is peeled off by heat from the outside or a material whose shape is deformed. For example, it may be a foaming agent that is bulky due to heat from the outside.

The adhesive layer 227 may be any one of an acrylic adhesive and a silicone resin composition. A material 225 that is peeled off by heat is included in the adhesive layer 227.

When the adhesive layer 227 and the material 225 exfoliated by heat are 100 (wt%), the material 225 exfoliated by heat may be 5 to 20 (wt%), but is not limited thereto. It may have a different weight ratio as needed.

The size of the material 225 peeled off by heat is smaller than the thickness of the adhesive layer 227. However, when the material 225 peeled by heat receives heat from the outside, the outer shape becomes large and deformed, and the deformed outer shape is larger than the thickness of the adhesive layer 227. As the external shape of the material 225 peeled off by the heat changes, the material 225 peeled off by heat may form a pressure that physically pushes chips attached to the adhesive layer 227. Chips may be separated from the adhesive layer 227 by the formed pressure.

The thermal release carrier substrate 220 may be prepared in plural. For example, a first thermal peeling carrier substrate to which the R emitter is transferred, a second thermal peeling carrier substrate to which the G emitter is transferred, and a third thermal peeling carrier substrate to which the B emitter is transferred may be prepared, respectively.

8 to 10 are exemplary views for explaining a process of selectively transferring the chip array shown in FIG. 1 from a carrier substrate to a thermally peeled carrier substrate.

Referring to FIG. 8, the first thermal release carrier substrate 220R is disposed on the first carrier substrate 210R on which the R LED chip array 100R is formed. The adhesive layers 227 of the first thermal release carrier substrate 220R are contacted on the R LED chips 100R to be attached to each other.

Referring to FIG. 9, a first mask layer 230R is formed on the first thermal release carrier substrate 220R. The first mask layer 230R includes a base layer 231 and metal layers 235a and 235b patterned on the base layer 231.

The base layer 231 may be formed of a material through which photons incident from the outside can pass, for example, may be composed of quartz (Quartz).

The metal layers 235a and 235b may be patterned on the lower surface of the base layer 231. Since the metal layers 235a and 235b reflect or absorb photons, heat is generated. On the other hand, there are no metal layers 235a and 235b, and the transparent base layer 231 hardly generates heat as photons are transmitted. Accordingly, heat is generated in the patterned metal layers 235a and 235b of the R LED chip array 100R, and heat conduction is performed to the chip 100R positioned below, and is not located under the patterned metal layers 235a and 235b. Thermal conductivity does not occur with the chip 100R.

The pitch of the two adjacent metal layers 235a and 235b may correspond to the pitch between two adjacent pads of the display panel, which will be described later. Therefore, when patterning the metal layers 235a and 235b, it is desirable to consider the pitch between two pads of the display panel. For example, the pitch of two neighboring patterned metal layers 235a and 235b may be K times the pitch between two pads of the display panel.

After forming the first mask layer 230R, a predetermined photon is applied over the first mask layer 230R. The photon may be an infrared photon, but is not limited thereto, and the photon may be a visible light or an ultraviolet photon.

Of the applied photons, photons incident on the patterned metal layers 235a and 235b of the first mask layer 230R generate heat in the patterned metal layers 235a and 235b, and are not incident on the patterned metal layers 235a and 235b. The remaining photons pass through the first mask layer 230R but do not generate heat.

Referring to FIG. 10, after photons passing through the first mask layer 230R pass through the substrate 221 and the base layer 223 of the first thermal peeling carrier substrate 220R, the first thermal peeling is performed. It is incident on the material 225 that is peeled off by the heat of the carrier substrate 220R. The material 225 exfoliated by heat is foamed by the incident photons. That is, it is deformed so that the outer shape becomes large. As the size of the material 225 peeled by heat becomes larger than the thickness of the adhesive layer 227, some of the chips 100R' among the chips 100R where the material 225 peeled by heat adheres to the adhesive layer 227 Push it out. That is, the material 225 that is peeled off by the heat whose shape is deformed provides a predetermined pressure to some selected chips 100R'. The pressure provided by the material 225 peeled off by heat separates some of the selected chips 100R' from the adhesive layer 227, and improves the adhesion between the selected some chips 100R' and the first carrier substrate 210R. You can.

As shown in FIG. 10, the adhesion between the chip 100R and the adhesive layer 227 of the first thermal release carrier substrate 220R is greater than that between the chip 100R and the first carrier substrate 210R. Big. Due to this difference in adhesive force, when the first thermal peeling carrier substrate 220R and the first carrier substrate 210R are separated from each other, the chip 100R may be transferred to the first thermal peeling carrier substrate 220R. .

As shown in FIG. 10, some of the chips 100R' among the plurality of chips 100R transferred to the thermal release carrier substrate 220R are transferred to the carrier substrate 210R, and the remaining chips 100R are first It is transferred to the thermal release carrier substrate 220R. In other words, the chip 100R located under the patterned metal layers 235a and 235b is transferred to the first carrier substrate 210R, and the chip 100R' not located under the patterned metal layers 235a and 235b is made of It is transferred to one heat release carrier substrate 220R. This is due to the fact that the material 225 peeled off by heat is transformed into a material peeled off by heat deformed by photons from the outside. The material 225 exfoliated by heat is deformed in size by photons, and a predetermined pressure is generated by deformation of the material 225 exfoliated by heat, and the generated pressure is applied to the chip 100R' to form the chip 100R ') and the adhesive strength between the adhesive layer 227 is reduced. By this process, selected chips 100R (chips 100R not disposed under the patterned metal layers 235a and 235b) among the plurality of chips transferred to the first carrier substrate 210R are first opened. It may be transferred to the release carrier substrate 220R.

Here, a specific row or column unit of the plurality of chips 100R may be selectively transferred by applying a predetermined column in a specific row or column unit.

11 is the same process as that of FIGS. 8 to 10, some G LED chips 100G among the G LED chip arrays formed on the second carrier substrate 210G are selectively transferred to the second thermal peeling carrier substrate 220G. This is a drawing showing what has been transferred.

FIG. 12 is a process similar to FIGS. 8 to 10, in which some of the B LED chips 100B among the B LED chip arrays formed on the third carrier substrate 210B are selectively transferred to the third thermal peeling carrier substrate 220G. This is a drawing showing what has been transferred.

As described above, the step of transferring the chip array formed on the carrier substrate to the thermal peeling carrier substrate may be referred to as'primary transfer', or may be referred to as selective transfer in the sense of being transferred by selecting in units of columns or rows. have.

On the other hand, the thermal release carrier substrate 220 may be a transparent material. When the thermal peeling carrier substrate 220 is a transparent material, when transferring each chip (100R-SP1, 100R-SP2, 100R-SP3) to the thermal peeling carrier substrate 220, position adjustment and misalignment are provided externally. It has the advantage of being able to be adjusted or controlled via a vision system (not shown).

13 to 14 are exemplary views of a process in which the chip array is secondarily transferred from the heat-peel carrier substrate to the display panel.

Referring to FIG. 13, (A) shows pads 31-SP1, ..., 31-SP6 of the display panel 300, and (B) is a first thermal peeling carrier substrate on the display panel 300. The 220R is aligned to show the state in which the R chip array is secondarily transferred onto the display panel 300.

Pads 31-SP1, ..., 31-SP6 are formed in columns 1 to 6 of the display panel 300, and solder pastes 33-SP1 and 33-SP4 are formed in columns 1 and 4, and correspondingly The R chips 100R-SP1 and 100R-SP4 are transferred to the column positions, respectively.

However, although the solder paste is shown to be formed only in the first and fourth rows on the pad of the display panel 300, it is acceptable to use the solder pastes 33-SP1, ..., and 33-SP6 in all rows.

14 illustrates a cross-sectional process in which the R chip array is transferred from the first thermal peeling carrier substrate 220R to the display panel 300 in FIG. 13 in more detail.

Referring to FIG. 14A, solder pastes 33 are applied on a plurality of pads 31 of the display panel 300.

The TFT array substrate 400 may be disposed under the display panel 300.

Here, the solder paste 33 may be applied only on the pads 31-SP1 and 31-SP4 in rows 1 and 4, but may be applied on the remaining pads.

One row of the R chip array is selectively transferred to the first row and fourth row pads (preferably the pads arranged at the intervals of the previous row + the third row), and then the second row and third row pads between the first row and fourth row ( Each column (pads arranged at intervals of the front row + 3 rows) sequentially transfers one row of the G chip array and one row of the B chip array.

The solder paste 33 may be applied to various pads 31 of the display panel 300 through various methods such as screen printing, dispensing, and jetting.

Next, referring to (B) of FIG. 14, the R chip arrays 100R-SP1 and 100R-SP4 attached to the first thermal release carrier substrate 220R are disposed on the display panel 300, and the R chip The pads of the arrays 100R-SP1 and 100R-SP4 are brought into contact with the solder pastes 33-SP1 and 33-SP4 applied on the pad 31 of the display panel 300.

After the pads of the R chip arrays 100R-SP1 and 100R-SP4 are contacted with the solder pastes 33-SP1 and 33-SP4 and the pad 31 of the display panel 300, for example, self-aligning paste (Self Align Paste, SAP) When a certain amount of heat is applied using the soldering method, the solder particles contained in the solder paste (33-SP1, 33-SP4) have some R chip arrays (100R-SP1, 100R) -It may be self-assembled between the pad of SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300.

Meanwhile, the thermosetting resin included in the solder paste 33 may be cured by heat.

Next, referring to (C) of FIG. 14, when the pads of the R chip arrays 100R-SP1 and 100R-SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300 are soldered, the first A predetermined heat is applied on the thermal release carrier substrate 220R. A predetermined photon by the heat is incident on the material 225 that is peeled off by the heat of the first thermal peeling carrier substrate 220R. The material 225 exfoliated by heat is transformed into a material 225' exfoliated by the deformed heat by increasing in size by the incident heat. The material 225' exfoliated by the deformed heat pushes the R chip arrays 100R-SP1 and 100R-SP4, so that the R chip arrays 100R-SP1 and 100R-SP4 are the first thermal peel carrier substrate 220R. It falls from the adhesive layer 227 of the. Thereafter, when the first thermal peeling carrier substrate 220R is separated from the R chip arrays 100R-SP1 and 100R-SP4, the R chip arrays 100R-SP1 and 100R-SP4 are transferred to the display panel 300.

Here, the material 225' exfoliated by the deformed heat pushes the R chip array 100R-SP1, 100R-SP4, so that the R chip array 100R-SP1, 100R-SP4 is the first thermal release carrier substrate ( Since it falls from the adhesive layer 227 of 220R), there is almost no adhesive force between the R chip arrays 100R-SP1 and 100R-SP4 and the first thermal release carrier substrate 220R. Therefore, the R chip arrays 100R-SP1 and 100R-SP4 can be almost completely transferred to the display panel 300 by this process.

15 to 16 are other exemplary views of a process in which a chip array is secondarily transferred from a heat-peel carrier substrate to a display panel.

Referring to FIG. 15, (A) shows the pads 31-SP1, ..., 31-SP6 of the display panel 300, and R sub-pixels in columns 1 and 4 through the process of FIGS. 13 to 14 The array is in a transferred state, and (B) shows a state in which the second sub-column carrier substrate 220G is aligned on the display panel 300 to secondaryly transfer the G sub-pixel array on the display panel 300. will be.

Pads 31-SP1, ..., 31-SP6 are formed in rows 1 to 6 of the display panel 300, and solder pastes 33-SP2 and 33-SP5 are formed in rows 2 and 5, and corresponding The G chip arrays 100G-SP1 and 100G-SP4 are transferred to the column positions, respectively.

FIG. 16 illustrates a cross-sectional process in which the G chip array is transferred from the second thermal release carrier substrate 220G to the display panel 300 in FIG. 15 in more detail.

Referring to FIG. 16A, solder pastes 33 are applied on a plurality of pads 31 of the display panel 300, and in the first row and fourth row, the R chip array 100R- SP1, 100R-SP4) are located in the transferred state.

Here, the solder paste 33 may be applied only on the pads 31-SP2 and 31-SP5 of the second row and the fifth row, but may be applied on the remaining pads.

Next, referring to (B) of FIG. 16, the G chip arrays 100G-SP1 and 100G-SP4 attached to the second thermal peeling carrier substrate 220G are disposed on the display panel 300, and the G chip The pads of the arrays 100G-SP1 and 100G-SP4 are brought into contact with the solder pastes 33-SP2 and 33-SP5 applied on the pads 31 of the display panel 300.

After the pads of the G chip arrays 100G-SP1 and 100G-SP4 are contacted with the solder pastes 33-SP2 and 33-SP5 and the pads 31 of the display panel 300, for example, self-aligning paste (Self Align Paste, SAP) When a predetermined amount of heat is applied using the soldering method, the solder particles contained in the solder pastes 33-SP2 and 33-SP5 become G chip arrays (100G-SP1, 100G-). It may be self-assembled between the pad of SP4) and the pads 31-SP2 and 31-SP5 of the display panel 300.

Next, referring to (C) of FIG. 16, when the pads of the G chip arrays 100G-SP1 and 100G-SP4 and the pads 31-SP2 and 31-SP5 of the display panel 300 are soldered, the second A predetermined heat is applied to the thermal peeling carrier substrate 220G to deform the material 225 peeled off by heat in the second thermal peeling carrier substrate 220G. The material 225' exfoliated by the deformed heat pushes out the G chip array 100G-SP1, 100G-SP4, so that the G chip array 100G-SP1, 100G-SP4 is the second heat release carrier substrate 220G. From the adhesive layer 227. Thereafter, when the second thermal peeling carrier substrate 220G is separated from the G chip arrays 100G-SP1 and 100G-SP4, the G chip arrays 100G-SP1 and 100G-SP4 are transferred to the display panel 300.

17 to 18 are other exemplary views of a process in which a chip array is secondarily transferred from a heat-peel carrier substrate to a display panel.

Referring to FIG. 17, (A) shows the pads 31-SP1, ..., 31-SP6 of the display panel 300, and passes through the process of FIGS. 13 to 14 and the process of FIGS. 15 to 16. The R chip array is transferred to columns 1 and 4, and the G chip array is transferred to columns 2 and 5, and (B) is a B chip array by aligning the third column peeling carrier substrate 220B on the display panel 300. It shows the secondary transfer state on the display panel 300.

Pads 31-SP1, ..., 31-SP6 are formed in columns 1 to 6 of the display panel 300, and solder pastes 33-SP3 and 33-SP6 are formed in columns 3 and 6. The B chip arrays 100B-SP1 and 100B-SP4 are transferred to the column positions, respectively.

FIG. 18 illustrates a cross-sectional process in which the process of transferring from the third thermal release carrier substrate 220B to the display panel 300 in FIG. 17 is described in more detail.

Referring to FIG. 18(A), solder pastes 33 are applied on a plurality of pads 31 of the display panel 300, and the first and fourth columns, the second and fifth columns, respectively, are already applied in the previous step. The R chip array arrays 100R-SP1 and 100R-SP4 and the G chip array arrays 100G-SP1 and 100G-SP4 are located in a transferred state.

Next, referring to (B) of FIG. 18, the B chip arrays 100B-SP1 and 100B-SP4 attached to the third thermal release carrier substrate 220B are placed on the display panel 300, and the B chip The pads of the arrays 100B-SP1 and 100B-SP4 are brought into contact with the solder pastes 33-SP3 and 33-SP6 applied on the pads 31 of the display panel 300.

After the pads of the B chip arrays 100B-SP1, 100B-SP4 and the pads 31 of the display panel 300 are contacted through the solder pastes 33-SP3, 33-SP6, for example, self-aligning paste (Self Align Paste, SAP) When a predetermined amount of heat is applied using the soldering method, the solder particles contained in the solder pastes 33-SP3 and 33-SP6 have B chip arrays (100B-SP1, 100B-). It may be self-assembled between the pad of SP4) and the pads 31-SP3 and 31-SP6 of the display panel 300.

Next, referring to (C) of FIG. 18, when the pads of the B chip arrays 100B-SP1 and 100B-SP4 and the pads 31-SP3 and 31-SP6 of the display panel 300 are soldered, the third A predetermined heat is applied to the thermal peeling carrier substrate 220B to deform the material 225 peeled off by the heat in the third thermal peeling carrier substrate 220B. The material 225' exfoliated by the deformed heat pushes the B chip arrays 100B-SP1, 100B-SP4, so that the B chip arrays 100B-SP1, 100B-SP4 are the third thermal peel carrier substrate 220B From the adhesive layer 227. Thereafter, when the third thermal peeling carrier substrate 220B is separated from the B chip arrays 100B-SP1 and 100B-SP4, the B chip arrays 100B-SP1 and 100B-SP4 are transferred to the display panel 300.

As described above, when the processes of FIGS. 13 to 18 are sequentially applied, it is possible to manufacture the display panel 300 in which one completed pixel CSP array is arranged, and the first of each of FIGS. 10, 11, and 12 is possible. It is possible to sequentially transfer the R, G, and B chip arrays selectively transferred to the third to third thermal peeling carrier substrates 220R, 220G, and 220B from the first column to the last column of the display panel 300.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, and the like exemplified in each embodiment may be combined or modified for other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the embodiments have been mainly described above, these are merely examples and do not limit the present invention, and those of ordinary skill in the art to which the present invention pertains have the above-described scope without departing from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications not illustrated are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And differences related to these modifications and applications should be construed as being included in the scope of the invention defined in the appended claims.

10R, 10G, 10B: Wafer
100R, 100G, 100B: Chip
210R, 210G, 210B: carrier substrate
220R, 220G, 220B: thermal peel carrier substrate
300: display panel
400: TFT array substrate

Claims (15)

A primary transfer step of transferring a plurality of chips formed on the wafer to a carrier substrate by adhesive force; And
Including; a secondary transfer step of transferring a plurality of chips formed or disposed on the carrier substrate onto a thermal release substrate comprising a material peeled off by heat;
The secondary transfer step,
Forming a base layer on the thermal release substrate, and forming a patterned metal layer on the base layer, a mask layer forming step;
A material deformation step of applying a predetermined heat over the mask layer to deform the size of a material located under the metal layer among materials exfoliated by the heat;
A pressure acting step in which the size deformation of the material acts as a pressure to push out some of the plurality of chips so that some of the plurality of chips are separated from the thermal release substrate; And
And a selective transfer step of separating the thermal release substrate from the carrier substrate and transferring some of the chips from the plurality of chips to the thermal release substrate.
According to claim 1,
A transfer method using a thermal release substrate, by selectively transferring a specific row or column unit among the plurality of chips by applying a predetermined column in a specific row or column unit.
According to claim 1,
The material to be peeled off by the heat is a foaming material foamed by the heat, a transfer method using a heat peeling substrate.
The method of claim 3,
The foamable material is bulky by the heat, and acts as a pressure to push out the remaining chips among the plurality of chips, so that the remaining chips among the plurality of chips are separated from the thermal release substrate.
delete delete The method of claim 1, wherein the thermal release substrate,
Board;
A base layer disposed on the substrate; And
It is disposed on the base layer, the adhesive layer having a material peeled off by the heat; includes,
The size before deformation of the material is smaller than the thickness of the adhesive layer,
The size after deformation of the material is larger than the thickness of the adhesive layer,
Transfer method using a thermal release substrate.
The method of claim 7,
The adhesive method between the adhesive layer and the chip is greater than the adhesive force between the carrier substrate and the chip, a transfer method using a thermal release substrate.
A chip forming step of forming a plurality of chips and a protective layer for passivating the plurality of chips on the wafer;
An etching step of etching the protective layer for each chip on the wafer;
Attaching a chip array etched on the wafer and arranged in a matrix to a carrier substrate, a carrier substrate attaching step;
A wafer removal step of removing the wafer from the chip array;
A thermal peeling carrier substrate having a material peeled off by heat is disposed on the chip array, and a predetermined heat is applied to the thermal peeling carrier substrate to apply some of the chip array of the chip array transferred to the carrier substrate to the thermal peeling carrier substrate Selectively transferring, a transfer step; And
Including; a display panel transfer step of transferring the part of the chip array transferred to the heat exfoliating carrier substrate to a display panel;
The transfer step,
Forming a base layer on the heat exfoliating carrier substrate, and forming a patterned metal layer on the base layer, a mask layer forming step;
Modifying the size of the material located under the metal layer among the materials exfoliated by the heat by applying the predetermined heat over the mask layer;
A pressure acting step in which the size deformation of the material peeled off by the heat acts as a pressure to push the rest of the chip array out of the chip array, so that the rest of the chip array in the chip array is separated from the heat peeling carrier substrate; And
And a selective transfer step of separating the thermal peeling carrier substrate from the carrier substrate and transferring some of the chip arrays from the chip array to the thermal peeling carrier substrate.
delete 10. The method of claim 9, wherein the heat-release carrier substrate,
Board;
A base layer disposed on the substrate; And
It is disposed on the base layer, the adhesive layer having a material peeled off by the heat; includes,
The size before deformation of the material is smaller than the thickness of the adhesive layer,
The size after deformation of the material is larger than the thickness of the adhesive layer,
A method of manufacturing a display device, wherein an adhesive force between the adhesive layer and the chip is greater than an adhesive force between the carrier substrate and the chip.
10. The method of claim 9, The display panel transfer step,
A method of manufacturing a display device, in which chip arrays are sequentially provided from a plurality of different thermal peeling carrier substrates to form one display panel.
The method of claim 9,
The wafer is any one of sapphire (Al2O3), silicon, gallium arsenide (GaAs), gallium nitride (GaN), and zinc nitride (ZnN),
The wafer removal step removes the wafer from the chip array through a laser lift off (LLO) process,
Method for manufacturing a display device.
The method of claim 9,
The display panel transfer step,
A solder paste application step of applying solder paste on a plurality of pads of the display panel;
A soldering step of soldering by contacting the pad of the chip array transferred to the heat-exfoliating carrier substrate to the applied solder paste;
A material deformation step of applying a predetermined heat on the heat exfoliating carrier substrate to deform the size of the material exfoliated by the heat; And
A pressure action step in which the size deformation of the material acts as a pressure to push the chip array transferred to the heat release carrier substrate so that the chip array transferred to the heat release carrier substrate is separated from the heat release carrier substrate;
A method of manufacturing a display device comprising a.
delete

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