KR102064105B1 - Dielectric ceramic composition and electronic device using the same - Google Patents

Abstract

The present invention is a dielectric Self-composition and This The present invention relates to an applied electronic device, and more particularly, to a dielectric magnetic composition satisfying X5R, X7R, and X8R characteristics specified in an EIA standard, and an electronic device using the same. According to the present invention, it is possible to realize a characteristic that the Curie temperature rise and the high-temperature dielectric constant becomes flat, without using lead (Pb) harmful to the environment in the base material powder, and can satisfy the X8R temperature characteristics and good high temperature withstand voltage characteristics.

Description

Dielectric self-composition and electronic device using the same {DIELECTRIC CERAMIC COMPOSITION AND ELECTRONIC DEVICE USING THE SAME}

The present invention is a dielectric Self-composition and This The present invention relates to an applied electronic device, and more particularly, to a dielectric magnetic composition satisfying X5R, X7R, and X8R characteristics specified in an EIA standard, and an electronic device using the same.

The composition system of the dielectric material of the conventional high capacity BME multilayer ceramic capacitors such as X5R, X7R or X8R is applied to the base material such as BaTiO ₃ or (Ba _{1 - x} Ca _x ) (Ti _{1 - y} Ca _y ) O ₃ , which is the main component material. And essentially four or more additive subcomponents. The largest proportion of additive additives is Mg, a fixed-valence acceptor, and rare-earth elements, and a small amount of the variable-valence acceptor is added below these amounts. And sintering aids are included to enhance the sinterability. In the conventional composition system, a rare-earth element and a fixed-valence acceptor Mg react with BaTiO ₃ to form a core-shell structure, which is a normal multilayer ceramic capacitor. It is necessary to implement the characteristics of In order to increase the Curie temperature by applying the BaTiO ₃ base material, it is known to add CaZrO ₃ or to add an excessive rare earth element to mitigate the decrease in dielectric constant above the Curie temperature.

Japanese Laid-Open Patent 2008-011254

Yoon et al., J. Mater. Res., 22 [9] 2539 (2007)

The present invention is a dielectric magnetic composition that satisfies the X5R, X7R, and X8R characteristics specified in the EIA standard, and uses a nickel as an internal electrode and is capable of baking in a reducing atmosphere in which the nickel is not oxidized at 1300 ° C. or below, and the same. The purpose is to provide an electronic device used.

In the present invention, BaTiO ₃ and (Na, K) NbO ₃ are mixed at an appropriate ratio, or a solid solution is formed, and a small amount of SiO ₂ and MnO ₂ are added to prepare a sintered body to maintain a relatively high dielectric constant of 1500 or more at room temperature. And at the same time ensure that the X8R temperature characteristics are met.

According to the present invention, it is possible to realize a characteristic that the Curie temperature rise and the high-temperature dielectric constant becomes flat, without using lead (Pb) harmful to the environment in the base material powder, and can satisfy the X8R temperature characteristics and good high temperature withstand voltage characteristics.

Hereinafter, the present invention will be described in more detail.

The present invention relates to a novel dielectric self-composition that satisfies the X8R properties, with guaranteed temperature and reliability up to 150 degrees.

BaTiO ₃ , the main material of high-capacity Ni-MLCC, has a Curie temperature (TC) of around 125 degrees, and the dielectric constant drops rapidly above this temperature. Therefore, the capacity temperature characteristics up to 150 degrees are within ± 15% of the X8R standard. In order to fit, a composition suitable for this is required.

For example, by adding an excessive amount of rare earth elements to BaTiO ₃ base material to alleviate the reduction of dielectric constant above Curie temperature, or by adding an appropriate amount of CaZrO ₃ , the Curie temperature can be increased to improve the high temperature coefficient TCC (Temperature Coefficient of Capacitance). There is a report (Japanese Patent Laid-Open No. 2001-279534, 2004-73856, etc.). However, when excessive amounts of rare earths are added, a secondary phase called Pyrochlore is generated and reliability is deteriorated (Yoon et al., J. Mater. Res., 22 [9] 2539 (2007)), and BaTiO ₃ having a Curie temperature of 125 degrees. When an excessive amount of rare earth is added to the base material or when CaZrO ₃ is added, there is a limit in obtaining excellent high temperature part TCC characteristics even if the X8R characteristics are satisfied.

In another method, a high Curie temperature may be applied to improve the hot portion TCC. It is known that the Curie temperature increases when Ca is dissolved in the A-site of ABO ₃ Perovskite structure. The application of BaTiO ₃ (BCT) powder in which Ca is employed can improve the TCC characteristics of the hot part, suggesting the possibility of X8R material. There is a bar. Yoon et al., J. Mater. Res., 25 [11] 2135 (2010). In the case of synthesizing BaTiO ₃ by calcination in air by the solid phase method, Pb, in addition to Ca mentioned above, is known as an element capable of increasing the Curie temperature. However, Pb is classified as a hazardous substance, and when fired in a reducing atmosphere such as a Ni-laminated ceramic capacitor, it easily becomes volatilized and thus difficult to apply in the process.

According to the present invention, BaTiO ₃ and (Na, K) NbO ₃ are mixed at an appropriate ratio or a solid solution is formed, and a small amount of SiO ₂ and MnO ₂ are added to prepare a sintered body. We present self-composition that can realize characteristics. In other words, X8R characteristics can be realized without adding CaZrO ₃ or excessive rare earth elements, and better TCC characteristics can be realized than the existing BaTiO ₃ base material.

According to an aspect of the invention, first the main component BaTiO ₃ and the second main component (Na1-yKy) NbO ₃ employs chains (1-x) of the BaTiO ₃ -x _{(Na 1 - y K y)} NbO 3 (0.005≤x ≤ 0.5, 0.3 ≤ y ≤ 1.0), the first subcomponent comprising an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu and Zn, and SiO ₂ or A dielectric self composition is provided that includes a glass forming material as a second accessory ingredient.

The range of x and y is based on the composition and the experimental results of Table 1 and Table 2 derived according to the embodiment of the present invention.

The dielectric ceramic composition is composed of a solid solution of the first main component BaTiO ₃ and the second main component (Na, K) NbO ₃ to form a base material, and the additive is a variable-valence acceptor element oxide or and a carbonate, a SiO ₂ second subcomponent. The synthesized base material is in the form of a powder, the particle size of which is preferably 1.0 μm or less.

In one embodiment, the first accessory ingredient may be an oxide or carbonate of an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu, and Zn.

In one embodiment, the first accessory ingredient is MnO ₂ Or MnCO ₃ .

In one embodiment, the content of the first accessory ingredient may be 0.1 to 5.0 at%.

In one embodiment, the content of SiO ₂ in the second subcomponent may be 0.1 to 5.0 at%.

The content range of each component in the above is based on the experimental results of Table 1 and Table 2.

According to another aspect of the present invention, an electronic device including a dielectric formed by using the dielectric magnetic composition may be provided.

In one embodiment, the electronic device may be at least one selected from the group consisting of a multilayer ceramic capacitor, a piezoelectric element, a chip inductor, a chip varistor, a chip resistor, and a PTCT (Positive Temperature Coefficient Resistor).

In particular, the dielectric magnetic composition of the present invention can be used in a laminated dielectric product, an internal electrode layer, for example, a product in which Ni internal electrode layers and dielectric layers are alternately laminated. Too thin a dielectric layer has a small number of grains present in one layer, which may adversely affect reliability. Therefore, the thickness of the dielectric layer is preferably used in a range of 0.1 mu m or more after firing.

EXAMPLE

The main component powder (1-x) BaTiO ₃ -x (Na _{1 - y} K _y ) NbO ₃ mixed solid solution powder was prepared by applying the solid phase method as follows. Starting materials are BaCO ₃ , TiO ₂ , Na ₂ O, K ₂ O, Nb ₂ O ₅ . First, BaCO ₃ and TiO ₂ were mixed in a ball mill and calcined at 900 to 1000 ° C. to prepare BaTiO ₃ powder having an average particle size of 300 nm. In a similar manner, Na ₂ O, K ₂ O, and Nb ₂ O ₅ ball mills were mixed and calcined at 800 to 900 ° C. to prepare (Na _0.5 K _0.5 ) NbO ₃ powder with an average particle size of 300 nm. These were dispersed and mixed in ethanol in accordance with the composition ratios specified in Table 1 below. The mixed powder was calcined in the range of 950 ~ 1050 ℃ in air to prepare a base material powder with an average particle size of about 300 nm. After adding the subsidiary additives MnO ₂ and SiO ₂ powder to the main component base powder according to the composition ratio specified in Table 1, the raw powder containing the main component and the subcomponent was used as a mixing / dispersing media of zirconia balls and ethanol / toluene and dispersant. And the binder were mixed and ball milled for 20 hours. The prepared slurry was manufactured into a sheet having a thickness of 10 μm using a doctor blade coater.

The prepared internal sheet was printed with Ni internal electrodes. The upper and lower covers were manufactured by stacking 25 sheets of cover sheets, and by pressing and stacking 21 layers of printed active sheets, a bar was manufactured. The pressing bar was cut into chips having a size of 3.2 mm x 1.6 mm using a cutter. After fabrication, the 3216 laminated ceramic capacitor (MLCC) chip was calcined for 2 hours at a temperature of 1200 to 1300 ° C in a reducing atmosphere of 0.1% H2 / 99.9% N2 (H ₂ O / H ₂ / N ₂ atmosphere). Thereafter, the reoxidation was heat treated for 3 hours at 1000 ° C. in an N 2 atmosphere. The external electrode was completed through a termination process and electrode firing with Cu paste on the fired chip.

Example Base material molar ratio
(1-x) BaTiO ₃ + x (Na _{1 - y} K _y ) NbO ₃ Base material BT-NKN per 100 mol
Molar number of each additive Primary ingredient Second ingredient 1 part Part 2 Ingredients BaTiO ₃
(1-x) (Na _{1 - y} K _y ) NbO ₃
(x) y MnO ₂ SiO ₂ One 1.000 0.000 0.500 0.50 0.50 2 0.995 0.005 0.500 0.50 0.50 3 0.990 0.010 0.500 0.50 0.50 4 0.980 0.020 0.500 0.50 0.50 5 0.970 0.030 0.500 0.50 0.50 6 0.950 0.050 0.500 0.50 0.50 7 0.900 0.100 0.500 0.50 0.50 8 0.800 0.200 0.500 0.50 0.50 9 0.700 0.300 0.500 0.50 0.50 10 0.600 0.400 0.500 0.50 0.50 11 0.500 0.500 0.500 0.50 0.50 12 0.400 0.600 0.500 0.50 0.50 13 0.950 0.050 0.500 0.00 0.50 14 0.950 0.050 0.500 0.10 0.50 15 0.950 0.050 0.500 0.30 0.50 16 0.950 0.050 0.500 1.00 0.50 17 0.950 0.050 0.500 2.00 0.50 18 0.950 0.050 0.500 5.00 0.50 19 0.950 0.050 0.500 7.00 0.50 20 0.950 0.050 0.500 0.50 0.00 21 0.950 0.050 0.500 0.50 0.10 22 0.950 0.050 0.500 0.50 1.00 23 0.950 0.050 0.500 0.50 2.00 24 0.950 0.050 0.500 0.50 5.00 25 0.950 0.050 0.500 0.00 7.00 26 0.950 0.050 0.200 0.50 0.50 27 0.950 0.050 0.300 0.50 0.50 28 0.950 0.050 0.700 0.50 0.50 29 0.950 0.050 1.000 0.50 0.50

Capacity, DF, insulation resistance, TCC, resistance degradation behavior with increasing voltage step at high temperature 150 ° C. were evaluated for the prototype laminated ceramic capacitor specimens as shown in Table 1 above. The room temperature capacitance and dielectric loss of the multilayer ceramic chip were measured at 1 kHz, AC 0.2V / μm using an LCR meter.

The dielectric constant of the laminated ceramic capacitor chip dielectric was calculated from the capacitance, the dielectric thickness of the multilayer ceramic chip, the internal electrode area, and the number of stacked layers.

The room temperature insulation resistance (IR) was measured after 60 seconds in a state in which 10 samples were taken and DC 10V / µm was applied. The change in capacitance with temperature was measured in the temperature range of -55 ° C to 150 ° C.

In the high temperature IR boost test, the resistance degradation behavior was measured by increasing the voltage step by 5V / μm at 150 ° C. The time of each step was 10 minutes and the resistance value was measured at 5 second intervals. The high temperature withstand voltage was derived from the high temperature IR boost test, which applied a voltage step dc 5V / μm at 150 ° C. for 10 minutes on a 3216 size chip with a 20-layer dielectric having a thickness of 7 μm after firing. When measured in continuous increments, it refers to the voltage at which the IR withstands more than 105Ω.

Table 2 shows the characteristics of the prototype multilayer ceramic capacitor chips corresponding to the compositions specified in Table 1.

room
city
Yes Ni-Laminated Ceramic Capacitor Prototype SPL Characteristics
Dielectric constant / DF measurement condition: AC 0.2V / um, 1kHz
(Room Specific Resistance: DC 10V / um) Firing temperature
(℃) Room temperature
permittivity DF (%) Room temperature resistivity
(Ohm-cm) TCC (%)
(-55 ℃) TCC (%)
(125 ℃) TCC (%)
(150 ℃) High temperature
(150 ℃)
Withstand voltage (V / um) * Judgment One 1250.0 3156.0 3.520 8.221E + 12 -11.7% -12.4% -35.2% 70 X 2 1250.0 2766.0 3.685 8.564E + 12 -12.2% -11.2% -15.0% 70 O 3 1250.0 2751.0 3.580 8.623E + 12 -12.4% -10.4% -14.5% 70 O 4 1250.0 2548.0 3.470 9.630E + 12 -12.5% -9.5% -13.5% 75 O 5 1250.0 2477.0 3.410 1.023E + 13 -12.8% -9.1% -12.8% 70 O 6 1250.0 2348.0 3.260 1.174E + 13 -13.2% -8.8% -11.8% 65 O 7 1250.0 2247.0 3.100 1.210E + 13 -13.4% -8.5% -10.6% 65 O 8 1250.0 2197.0 2.980 1.256E + 13 -13.5% -8.8% -10.2% 65 O 9 1250.0 1948.0 2.840 1.326E + 13 -9.5% -6.2% -9.8% 65 O 10 1250.0 1757.0 2.640 1.335E + 13 -9.2% -5.8% -9.6% 60 O 11 1250.0 1548.0 2.480 1.458E + 13 -8.8% -5.6% -9.5% 55 O 12 1250.0 1284.0 1.820 4.568E + 13 -7.8% -5.1% -9.2% 55 X 13 1250.0 21868.0 126.500 8.480E + 07 - - - 5 X 14 1250.0 2568.0 4.280 5.120E + 11 -13.1% -9.5% -12.5% 50 O 15 1250.0 2437.0 4.020 7.480E + 12 -12.9% -9.4% -11.7% 55 O 16 1250.0 2296.0 2.350 8.308E + 12 -12.8% -2.4% -9.8% 65 O 17 1250.0 1868.0 2.260 6.335E + 11 -11.6% -2.3% -8.5% 65 O 18 1250.0 1567.0 2.170 2.407E + 11 -11.2% -2.1% -8.4% 60 O 19 1250.0 1365.0 1.930 7.408E + 10 -10.4% -1.9% -7.7% 55 X 20 1300.0 2532.0 3.990 5.688E + 12 -13.7% -7.9% -10.1% 45 X 21 1270.0 2417.0 3.840 6.408E + 12 -13.6% -7.8% -11.5% 55 O 22 1240.0 2323.0 3.120 1.245E + 13 -12.8% -8.4% -11.7% 60 O 23 1250.0 2284.0 2.990 1.070E + 13 -11.8% -8.6% -12.2% 55 O 24 1270.0 2187.0 2.970 1.123E + 13 -11.7% -7.4% -11.7% 50 O 25 1290.0 2048.0 2.880 8.887E + 12 -11.4% -7.6% -11.6% 40 X 26 1250.0 1645.0 2.830 6.208E + 12 -11.8% -12.5% -9.9% 35 X 27 1250.0 1948.0 3.030 8.450E + 12 -12.3% -11.1% -12.7% 55 O 28 1250.0 2046.0 1.870 8.550E + 12 -10.7% -10.5% -15.0% 55 O 29 1250.0 1852.0 1.8 9.523E + 12 -9.7% -6.2% -9.9% 50 O

Carried out in Table 1 Examples 1 to 12 is the second main component _{(Na 1 - y K y)} y = 0.5 , and the first subcomponent MnO ₂ and the content of the second subcomponent SiO ₂ base material powder (1-x) BaTiO ₃ in NbO ₃ Contents of the first main component BT 1-x and the second main component (Na _{1 -y} K _y ) NbO ₃ at 0.5 at% and 0.5 at% relative to -x (Na _{1 - y} K _y ) NbO ₃ , respectively The characteristics of the prototype chip according to the change are shown. As the content of x gradually increases from 0 (Example 1) to 0.6 (Example 12), the dielectric constant decreases gradually. When x is 0 (Example 1), the dielectric constant is very high as 3156, but the TCC (150 degrees) ) Is outside the ± 15% X8R standard at -35.2%, and if x is 0.6 (Example 12), the room temperature dielectric constant is too low to less than 1500.

In the specimens of Examples 2 to 11, X8R temperature characteristics of 1500 or higher at room temperature dielectric constant, 50 V / um at high temperature, and TCC (150 degrees) ≤ ± 15% are satisfied. Therefore, the range of proper x can be described as 0.005≤x≤0.5. have.

Examples 13 to 19 of Table 1 are y = 0.5 in the second main component (Na _{1 - y} K _y ) NbO ₃ and its content x = 0.05, and the content of the second sub ingredient SiO ₂ is 0.5at% relative to the base powder. When the first accessory component MnO ₂ content is changed, the prototype chip is characterized. When the Mn content is 0 (Example 13), the specific resistance value of the room temperature is very low as 8.480E7, and from the Mn content of 0.1at% (Example 14) or more, it can be confirmed that insulation characteristics of 1E11 or more are realized. As the Mn content increases, the dielectric constant and room temperature resistivity continue to decrease so that the Mn content increases to 7at% (Example 19). The dielectric constant decreases to 1365, which is less than 1500, and the room temperature resistivity becomes less than 1E11. Occurs.

In the specimens of Examples 14 to 18, the dielectric constant, high temperature withstand voltage, and TCC characteristics satisfy the target characteristics of the present invention, so that the Mn content may be selected in the range of 0.1 to 5.0 at%.

Examples 20 to 25 of Table 1 are obtained when y = 0.5 and x = 0.05 in the second main component (Na _{1 - y} K _y ) NbO ₃ , and the content of the first minor component MnO ₂ is 0.5at% relative to the base powder. The characteristics of the prototype chip according to the variation of the content of two subsidiary components SiO ₂ are shown. When the content of SiO ₂ is 0 (Example 20), when the appropriate firing temperature is increased to about 1300 degrees, and when SiO ₂ is added (Examples 21 to 24), the sinterability is improved. When the SiO ₂ content is 7at% (Example 25), the effect of improving the sinterability is almost eliminated, and the high temperature withstand voltage property is deteriorated to less than 50 V / um. Therefore, from the results of Examples 20 to 25, the preferable SiO ₂ content in consideration of dielectric constant, high temperature withstand voltage, TCC characteristics, and sintering properties may be selected in the range of 0.1 to 5.0 at%.

Examples 26 to 29 of Table 1 have a second main component (Na _{1 - y} K _y ) NbO ₃ content x = 0.05, and the content of the first subcomponent MnO ₂ and the second subcomponent SiO ₂ is 0.5at% and the base powder, respectively. when 0.5at%, the second principal component (Na _{1 - y} Ky) the properties of the prototype chip according to the content of K y and 1-y Na content in NbO _3. The dielectric constant decreases and the high temperature withstand voltage property decreases as the second main component (Na _{1 - y} K _y ) NbO ₃ decreases from 0.3 (Example 27) to 0.2 (Example 26) based on the K content y = 0.5. In the case of y = 0.2 (Example 26), it can be seen that a problem occurs that the high temperature withstand voltage characteristic is less than 50 V / um. Although the dielectric constant and high temperature withstand voltage characteristics are slightly lowered with increasing from 0.7 (Example 28) to 1.0 (Example 29) based on the K content y = 0.5, the dielectric constant, high temperature withstand voltage, and TCC characteristics satisfy the target characteristics of the present invention. do. Therefore, in consideration of the permittivity, high temperature withstand voltage, and room temperature resistivity, the preferred range of K content y can be selected from 0.3≤y≤1.0.

The present invention is a dielectric Self-composition and This The present invention relates to an applied electronic device, and more particularly, to a dielectric magnetic composition satisfying X5R, X7R, and X8R characteristics specified in an EIA standard, and an electronic device using the same. According to the present invention, it is possible to realize a characteristic that the Curie temperature rise and the high-temperature dielectric constant becomes flat, without using lead (Pb) harmful to the environment in the base material powder, and can satisfy the X8R temperature characteristics and good high temperature withstand voltage characteristics.

As described above in detail specific parts of the present invention, it is apparent to those skilled in the art that such specific descriptions are merely preferred embodiments, and thus the scope of the present invention is not limited thereto. something to do. Thus, the substantial scope of the present invention will be defined by the appended claims and their equivalents.

Claims (7)

(1-x) BaTiO ₃ -x (Na _1-y K _y ) NbO ₃ (0.005≤x≤0.3, 0.3≤, which is a solid solution of the first main component BaTiO ₃ and the second main component (Na _1-y K _y ) NbO ₃ ) y≤1.0),
A first subcomponent which is an oxide or carbonate of an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu and Zn, and
A dielectric self-composition comprising SiO ₂ or a glass forming material comprising the same as a second accessory ingredient.
delete The method of claim 1, wherein the first subcomponent is MnO ₂ Or MnCO ₃ dielectric self-composition.
The dielectric magnetic composition of claim 1, wherein the content of the first accessory ingredient is 0.1-5.0 moles per 100 moles of the solid solution.
The dielectric ceramic composition of claim 1, wherein the content of SiO ₂ in the second subcomponent is 0.1-5.0 mol per 100 mol of the solid solution.
An electronic device comprising a dielectric formed by using the dielectric magnetic composition according to claim 1.
The electronic device of claim 6, wherein the electronic device is at least one selected from the group consisting of a multilayer ceramic capacitor, a piezoelectric device, a chip inductor, a chip varistor, a chip resistor, and a PTCT (Positive Temperature Coefficient Resistor).