KR102041968B1 - Timing controller, driving method thereof, and display device using the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device. In particular, a comparison value is accumulated in a block memory matched with a block corresponding to the pixel by comparing the amount of change of each pixel corresponding to each frame and stored in each block memory. A timing controller capable of determining whether a logo is output on a block matched with the block memory using a cumulative value, and correcting luminance of a block including the logo according to the determination result; It is a technical problem to provide a driving method and a display device using the same. To this end, a timing controller according to the present invention includes a frame memory unit for storing input image data included in an N-1 frame; A block that compares the amount of change of the input image data in each of the pixels corresponding to each other in the N-1 frame and the N frame currently being input, and accumulates a comparison value in a block memory matched with the block corresponding to the pixel. An accumulator; A logo block determination unit that determines whether a logo is included in a block matched with the block memory by using a cumulative value stored in each block memory; A luminance correction unit for correcting luminance of input image data included in a block including a logo as a result of the determination; And an output unit for outputting image data whose luminance is corrected by the luminance correction unit.

Description

Timing controller and its driving method and display device using the same {TIMING CONTROLLER, DRIVING METHOD THEREOF, AND DISPLAY DEVICE USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a timing controller, a driving method thereof, and a display device using the same that can improve an afterimage problem.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic electroluminescent display (OLED), and more recently, an electrophoretic display ( EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among them, OLEDs have advantages of fast response speed and high luminous efficiency, luminance, and viewing angle by using self-luminous devices that emit light by themselves.

FIG. 1 is a circuit diagram illustrating one pixel structure of a general organic light emitting display device, and illustrates a pixel structure composed of two N-type transistors. FIG. 2 is an exemplary view illustrating an image output through a panel of a general organic light emitting display, and shows a state in which logos 10 and 20 are output on a specific portion of the image.

As shown in FIG. 1, the pixel 50 of a typical organic light emitting display device is connected to an organic light emitting diode OLED, a data line DL, and a gate line GL to control the organic light emitting diode OLED. It may be composed of at least two transistors (T1, T2) for.

The anode electrode of the organic light emitting diode OLED is connected to the first power source VDD, and the cathode electrode is connected to the second power source VSS. The organic light emitting diode OLED generates light having a predetermined luminance in response to a current supplied from the second transistor T2.

Various circuits formed in the pixel 50 control the amount of current supplied to the organic light emitting diode in response to an image signal supplied to the data line DL when a scan signal is supplied to the gate line GL. To this end, the pixel 50 includes a second transistor T2 (driving transistor), a second transistor T2, a data line DL, and a gate line Gn connected between the first power supply VDD and the organic light emitting diode. A storage capacitor Cst connected between the first transistor T1 (switching transistor) and the gate electrode of the second transistor T2 and the organic light emitting diode OLED connected to each other is provided.

On the other hand, since the organic light emitting display device as described above uses an organic light emitting diode (OLED), which is a self-light emitting device, deterioration may occur due to various causes. If deterioration occurs and a deterioration difference between each pixel occurs, a difference in brightness and color is recognized, and a permanent afterimage remains.

That is, due to the self-luminous property of the organic light emitting diode OLED, when the same data of high brightness is maintained, deterioration occurs due to an object having a certain shape, and a regular afterimage in which the shape is recognized as an afterimage occurs. .

Such an afterimage becomes more severe as the organic light emitting diode (OLED) deteriorates, and it is recognized that the life of the organic light emitting diode is at the limit when the decrease in brightness is perceived by a human. This concept is called orthopedic persistence limit.

As described above, the atypical afterimage is caused by a logo or the like, and these logos shorten the recognition limit of the atypical afterimage, thereby shortening the product life of the organic light emitting display device.

For example, as shown in FIG. 2, when a logo or various subtitles 10, 20, etc. (hereinafter, simply referred to as 'logo') is continuously output to a certain area for a long time, an area where the logo is outputted OLEDs may deteriorate. In this case, the afterimage of the logo may remain in the area even if the logo disappears.

In order to prevent the afterimage caused by the logo as described above, a method of comparing the pixel data every frame to find the position of the logo and lowering the luminance of the image data corresponding to the position of the logo is conventional. It is used.

That is, the conventional method compares all the pixel data of the current frame and the pixel data of the previous frame, determines the area having the same pixel data for a predetermined frame or more as a logo area, and then displays the luminance of the image data output to the logo area By lowering, the logo area is prevented from deteriorating.

The conventional method as described above has the following problems.

That is, since the conventional method compares all the pixel data included in one frame as a whole, the comparison operation is not only complicated, but also has a problem that the capacity of the memory required for the comparison is increased.

For example, in case of Full-HD (1920x1080 (resolution)) using WRGB, the timing controller must compare data corresponding to (1920x1080 x 4 (sub-pixel) x 10bit) pixels every frame. Computation becomes complicated, and a high capacity and expensive frame memory capable of storing the data corresponding to the number must be provided in the timing controller.

Meanwhile, the deterioration due to the logo as described above is seriously occurring in the organic light emitting display, but may also occur in a display such as a liquid crystal display.

The present invention has been proposed to solve the above-described problem, and compares the amount of change of each pixel corresponding to each frame, accumulates a comparison value in a block memory matched with a block corresponding to the pixel, and stores each block. By using the accumulated value stored in the memory, it is determined whether the logo is output to the block matching the block memory, and the luminance of the block containing the logo can be corrected according to the determination result, It is a technical problem to provide a timing controller, a driving method thereof, and a display device using the same.

In accordance with another aspect of the present invention, a timing controller includes: a frame memory unit configured to store input image data included in an N-1 frame; A block that compares the amount of change of the input image data in each of the pixels corresponding to each other in the N-1 frame and the N frame currently being input, and accumulates a comparison value in a block memory matched with the block corresponding to the pixel. An accumulator; A logo block determination unit that determines whether a logo is included in a block matched with the block memory by using a cumulative value stored in each block memory; A luminance correction unit for correcting luminance of input image data included in a block including a logo as a result of the determination; And an output unit for outputting image data whose luminance is corrected by the luminance correction unit.

According to an aspect of the present invention, there is provided a method of driving a timing controller, the method including: storing input image data included in an N-1 frame; Comparing an amount of change of input image data in each of the pixels corresponding to each other in the N-1 frame and the N frame currently being input, and accumulating a comparison value in a block memory matched with a block corresponding to the pixel. ; Determining whether a logo is included in a block matched to the block memory using the accumulated value stored in each block memory; Correcting luminance of input image data included in a block including a logo as a result of the determination; And outputting image data whose luminance is corrected.

According to an aspect of the present invention, there is provided a display device including: a panel in which pixels are formed at regions where a gate line and a data line cross each other; The timing controller; A data driver for converting the image data transmitted from the timing controller into an analog image signal and outputting the analog image signal to the data line; And a gate driver for outputting a scan signal to the gate line every one horizontal period in which the image signal is output according to a control signal transmitted from the timing controller.

According to the present invention, the amount of change of each pixel corresponding to each frame is compared, the comparison value is accumulated in a block memory matched with a block corresponding to the pixel, and the accumulated value stored in each block memory is used. By determining whether or not the logo is output to the block matched with the block memory, and correcting the luminance of the block containing the logo according to the determination result, delayed display time of the image recognition by the logo is displayed The life of the device can be increased.

1 is a circuit diagram illustrating a pixel structure of a general organic light emitting display device.
2 is an exemplary view illustrating an image output through a panel of a general organic light emitting display device.
3 is an exemplary view showing a configuration of a display device using a timing controller according to the present invention.
4 is an exemplary view showing an internal configuration of a timing controller according to the present invention.
5 is an exemplary view showing in detail the configuration of the data alignment unit of the timing controller according to the present invention;
6 is a flowchart illustrating an embodiment of a timing controller driving method according to the present invention;
7 is an exemplary diagram for describing a concept of a block applied to a timing controller driving method according to the present invention.
8 is an exemplary diagram for explaining a relationship between a block and a block memory applied to a driving method in a timing controller according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is an exemplary view illustrating a configuration of a display device using a timing controller according to the present invention.

The timing controller 400 according to the present invention may be applied to a liquid crystal display (LCD), but may be particularly applied to an organic light emitting display device driven by WRGB data using a color filter. That is, deterioration due to a still image such as a logo may occur in a liquid crystal display, but particularly in an organic light emitting display. Therefore, hereinafter, the present invention will be described with an example of an organic light emitting display device driven with WRGB data using a color filter.

As shown in FIG. 3, the display device according to the present invention includes a panel 100, a gate driver 200 including at least one gate drive IC for driving gate lines of the panel, and data of the panel. The data driver 300 includes at least one source drive IC for driving lines, and a timing controller 400 for controlling the gate drive IC and the source drive IC.

First, the panel 100 is composed of subpixels 110 formed at respective regions where the gate lines and the data lines intersect. The subpixels 110 may include W subpixels, R subpixels, G subpixels, and B subpixels. The arrangement of the subpixels may be variously changed. Each of the subpixels 110 may output light having a unique color, or may output white light. In the latter case, the panel 100 may be provided with a color filter for outputting a white (W) color, a red (R) color, a green (G) color, and a blue (B) color.

Each of the subpixels is connected to the organic light emitting diode OLED, the data line DL, and the gate line GL, as shown in the enlarged circle 1 of FIG. 3 to form the organic light emitting diode OLED. It may be composed of at least two transistors T1 and T2 for controlling.

The anode electrode of the organic light emitting diode OLED is connected to the first power source VDD, and the cathode electrode is connected to the second power source VSS. The organic light emitting diode OLED generates light having a predetermined luminance in response to a current supplied from the second transistor T2.

Various circuits formed in the subpixel 110 control the amount of current supplied to the organic light emitting diode in response to an image signal supplied to the data line DL when a scan signal is supplied to the gate line GL. To this end, the subpixel 110 includes a second transistor T2 (driving transistor), a second transistor T2, a data line DL, and a gate line connected between the first power supply VDD and the organic light emitting diode. A storage capacitor Cst connected between the gate electrode of the first transistor T1 (switching transistor) and the second transistor T2 and the organic light emitting diode OLED connected between the first and second transistors GL is provided.

Next, the timing controller 400 operates the gate drive ICs by using a timing signal input from an external system, that is, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The gate control signal GCS for controlling the timing and the data control signal DCS for controlling the operation timing of the source drive ICs are generated, and input image data is received from the external system, and the data driver 300 Generates image data to be transmitted to the source drive ICs.

The timing controller 400 according to the present invention, before converting the input image data to the image data, by comparing each frame consisting of the input image data in each block unit, to the image to be output to the panel, Compares whether there is a still image (hereinafter simply referred to as a logo) such as a logo. As a result of the comparison, if there is a logo, the timing controller 400 lowers the luminance of the input image data to be output to the pixels included in the block in which the logo is displayed, and adjusts the input image data according to the characteristics of the panel. The rearranged images are output to the data driver 300.

Detailed configurations and functions of the timing controller 400 according to the present invention, which perform the above functions, will be described in detail with reference to FIGS. 4 to 8.

Next, each of the gate drive ICs constituting the gate driver 200 supplies a scan signal to the gate lines using the gate control signals GCS generated by the timing controller 400.

As the gate drive IC applied to the present invention, the gate drive IC used in the conventional flat panel display may be applied as it is. Meanwhile, the gate drive IC applied to the present invention may be formed independently of the panel 100 and may be configured to be electrically connected to the panel in various ways. However, the gate in IC may be mounted in the panel. It may be configured by a panel (Gate In Panel: GIP) method.

Lastly, the source drive IC constituting the data driver 300 converts the output image data transmitted from the timing controller 400 into an analog image signal every horizontal period during which a scan signal is supplied to the gate line. The video signal for one horizontal line is supplied to the data lines.

That is, the source drive IC converts the output image data into the image signal using the gamma voltages supplied from a gamma voltage generator (not shown) and outputs the image signal to the data line. To this end, the source drive IC includes a shift register part, a latch part, a digital analog converter, and an output buffer.

4 is an exemplary view showing an internal configuration of a timing controller according to the present invention.

As shown in FIG. 4, the timing controller 400 according to the present invention compares a change amount of each pixel corresponding to each frame with a receiver 410 for receiving a timing signal and the input image data from an external system. Storing a comparison value in a block memory matched with a block corresponding to the pixel, and using the comparison value stored in each block memory, whether a logo is output to a block matched with the block memory. A data alignment unit 430 for correcting the luminance of a block including a logo according to the determination result, and a gate control signal GCS and a data control signal using the timing signal transmitted from the receiver. The control signal generator 420 for generating the DCS and the image data output from the data aligner 430 and the control signal generator 420. And a transmitter 440 for transmitting the data control signal outputted from the data driver 300 to the data driver 300, and for transmitting the gate control signal output from the control signal generator 420 to the gate driver 200. do.

First, the receiver 410 receives the input image data and the timing signal from the external system and transmits the input image data to the data alignment unit 420. The timing signal received through the receiver 410 may be directly transmitted from the receiver 410 to the control signal generator 420, but the control signal generator 420 passes through the data aligner 420. Can be primed).

Next, the control signal generator 420 controls the timing of the gate control signal and the data driver 300 to control the timing of the gate driver 200 using the timing signals received from the receiver 410. The gate control signal to be generated is generated.

Finally, the data aligning unit 430 compares the amount of change of each pixel corresponding to each frame, stores the comparison value in a block memory matched with a block corresponding to the pixel, and stores the comparison value in each block memory. By using the comparison value, it is determined whether or not the logo is output to the block matching the block memory, and according to the determination result, the luminance of the block containing the logo is corrected, and the luminance is corrected. Performs a function to output video data. Specific configurations and functions of the data alignment unit 430 will be described in detail with reference to FIGS. 5 to 8.

FIG. 5 is an exemplary view showing in detail the configuration of the data alignment unit of the timing controller according to the present invention. FIG. 6 is a flowchart illustrating an embodiment of a method for driving a timing controller according to the present invention, and FIG. 7 is an exemplary view for explaining a concept of a block applied to the method for driving a timing controller according to the present invention. It is an exemplary diagram for explaining the relationship between a block and a block memory applied to a driving method in a timing controller.

As illustrated in FIG. 5, the data arranging unit 430 may include a frame memory unit 431 for storing input image data included in an N-1 frame, and an N frame currently being input with the N-1 frame. A block accumulation unit 432 for comparing the amount of change of the input image data in each of the pixels corresponding to each other and accumulating the comparison value in a block memory matched with the block corresponding to the pixel, is stored in each block memory. Logo block determination unit 434 for determining whether a logo is included in the block matched to the block memory using the accumulated value, and the input result included in the block including the logo as a result of the determination. A luminance correction unit 435 for correcting the luminance of the image data and an output unit 436 for outputting the image data, the luminance is corrected.

First, the frame memory 431 stores the input image data included in the frame for each frame (S602).

Here, the input image data may be input image data input from an external system, but may be primarily converted data before being input into the frame memory 431 in the timing controller.

When a frame currently stored in the frame memory 431 is referred to as an N-1 frame, a frame currently newly input into the frame memory 431 is referred to as an N frame.

Next, the block accumulation unit 432 inputs the N-1 frame stored in the frame memory 431 and the input image data included in the N frame currently being input to the frame memory 431. Received (S604).

Next, the block accumulator 432 compares the change amount of the input image data in each of the N frames and the pixels corresponding to each other in the N-1 frame, and matches the block corresponding to the pixel. The comparison value is accumulated and stored in the block memory (S606).

As shown in FIG. 7 and FIG. 8A, the block refers to areas in which one screen divided through the panel 100 is divided.

For example, when the panel 100 shown in FIGS. 7 and 8A is a panel configured with Full-HD using WRGB, the number of pixels in the horizontal is 1,920, the number of pixels in the vertical is 1,080, The pixels include four subpixels (W subpixel, R subpixel, G subpixel, and B subpixel), and each of the image data constituting the subpixels includes 10 bits. Therefore, the number of pixels included in one frame is 1920 (horizontal pixels) x 1080 (vertical pixels). Here, the number of subpixels (four) is not considered.

In this case, if one block is composed of 8x8 pixels, as shown in the enlarged circle of Figs. 7 and 8 (a), the one block or the horizontal line of the panel or screen A total of 240 blocks (= 1920/8) are generated, and a total of 135 (= 1080/8) blocks are generated in the vertical line.

In the following, the present invention will be described by taking the above-described example as an example of the present invention.

The block accumulator 432 calculates a change amount of the input image data by comparing input image data of pixels corresponding to each other in an N-1 frame and an N frame.

In this case, the block accumulation unit 432 sets the value for the pixel to 0 when the difference value of the two input image data is smaller than a preset value, and the block corresponding to the pixel. The value 0 can be stored in a memory. That is, if 'Pixel Difference value <Threshold', the comparison value for the pixel may be set to zero. Here, the preset value is a factor for adjusting the characteristics of the image or the accuracy of logo detection, and may be variously set in consideration of various factors.

In addition, the block accumulation unit 432 sets the value for the pixel to 1 if the difference value of the two input image data is greater than or equal to a preset value, and corresponds to the pixel. The value 1 may be stored in the block memory. That is, if 'Pixel Difference value ≥ Threshold', the comparison value for the pixel may be set to 1.

For example, the enlarged circle of FIGS. 7 and 8 shows input image data of each pixel of the first block 1B among the entire blocks of FIGS. 7 and 8, and among the enlarged circles, black is shown. The portion may be a portion where the comparison value is determined to be 0, and the white portion may be a portion where the comparison value is determined to be 1.

In this case, the comparison values in the first block 1B are stored in a first block memory BM corresponding to the first block 1B.

That is, the block accumulation section 432 has a block memory section 433 formed of the block memories corresponding to the number of blocks formed in each of the frames.

In this case, since the total sum of the comparison values for the pixels included in the first block 1B, that is, the cumulative sum of the comparison values included in the enlarged circle is 48, is a cumulative value of the comparison values. 48 is stored in the first block force memory 1BM.

That is, in each of the block memories, comparison values for each pixel included in a block corresponding to the block memory are accumulated and stored.

The method of accumulating the comparison value may proceed sequentially with respect to pixels of the entire panel.

For example, in the case of the panel shown in FIG. 8, a comparison value is calculated for pixels formed in the first horizontal line, and the calculated comparison value is stored separately in a corresponding block memory.

Therefore, comparison values calculated for the first to eighth pixels (pixels formed in the first block 1B) from the left in the first horizontal line are accumulated in the first block memory 1BM, and then Comparison values calculated for the ninth to sixteenth pixels (pixels formed in the second block 2B) are accumulated in the second block memory 2BM, and the 1913 to 1920th pixels (the first pixel) are accumulated. The comparison values calculated for the pixels formed in the 240 block 240B are accumulated in the 240 block memory 240BM.

The cumulative values for each of the pixels formed in the second horizontal line are also accumulated and stored in each block memory in the same order as described above.

By the above-described method, comparison values for pixels formed in each of the 1080th horizontal lines from the first horizontal line are sequentially arranged in each of the first block memory 1BM to the 32400 block memory 32400BM. Is accumulated as.

As described above, when using a block formed of 8x8 pixels, it can be seen that the memory usage rate is reduced to about 1/64 based on Full HD when compared with the conventional pixel unit operation.

That is, in the conventional pixel-by-pixel operation, 1920 x 1080 x 10 bit memory is required. However, in the present invention as described above, since (1920 x 1080 x 10 bit) / 8 x 8 memory are required, it corresponds to the number of pixels of the block memory The memory usage rate can be reduced by this ratio.

As described above, in N-1 frames and N frames, the comparison value of each pixel is accumulated in each block memory of the block memory unit 433 for each block.

After the process is completed, input image data of N frames is stored in the frame memory 431 (S602), and input image data of N + 1 frames are sequentially input (S604).

Accordingly, the block accumulator 432 repeatedly performs the comparison value storing process S606 for the N frames and the N + 1 frames.

Next, the logo block determination unit 434, when the comparison values are accumulated in each block memory of the block memory unit 433 by the above-described step (S606), are stored in each of the block memory. Using the cumulative value, it is determined whether or not the logo is included in each block (S608).

The logo block determination unit 434 calculates a cumulative average of the number of pixels that can determine whether a logo exists in each block by using an IIR filter, and extracts a block on which a logo is displayed. That is, the logo block determination unit 434 performs a function of determining the existence of the logo for each block 1B to 32400BM.

Here, the IIR filter (Infinite Impulse Response Filter) is an infinite impulse response filter, and refers to a digital filter whose duration of impulse response is infinite.

The formula of the IIR filter is the same as [Equation 1].

If you rearrange Equation 1,

IIR_Block_Countn =

IIR_Block_Countn-1 x (0.06) + avg (IIR_Block_Countn) x (0.994)

It can be expressed as.

In Equation 1, An is Block_Count, k = 0.06 (parameter), and Sn-1 = An is an average of previous data. Here, the block count (Block_Count) refers to a cumulative value stored in the block memory.

That is, the logo block determination unit 434 uses a cumulative value of the comparison values calculated for each frame. In particular, considering that frames are continuously input and the cumulative value is continuously changed, the logo block determination unit 434 may accumulate a past cumulative value (a cumulative value calculated in N-1 frames) and a current cumulative value. A weight is assigned to the value (the cumulative value calculated in N frames) to determine whether or not the logo of each block is determined. In this way, by assigning a weight to the cumulative value, it is possible to prevent noise data and to prevent a logo judgment error.

In detail, the present invention uses an IIR filter to determine a block containing a logo, and in particular, by giving different weights to the cumulative values of the past (N-1 frames) and the present (N frames). By excluding noise data, the accuracy and stability of logo detection are ensured.

As described above, the logo block determination unit 434 calculates comparison values stored for each block memory using an IIR filter to determine whether a logo is included for each block connected to the block memory. Perform the function.

Next, when the luminance correction unit 435 receives information that the logo is included in the frame from the logo block determination unit 434, the luminance (gradation) of the input image data of the block including the logo is received. To lower the luminance of the image data. In addition, the luminance compensator 435 converts the input image data into image data and outputs the received information that no logo is included in any block of the frame.

The alignment process for the image data may be performed by the luminance corrector 435 or may be performed by the output unit 436. In addition, the alignment process may be already applied to the input image data input to the frame memory unit 431.

The luminance correction method in the luminance correction unit 435 may be formed in various forms.

For example, a method of uniformly lowering luminance (gradation) of input image data included in a block determined to include a logo may be applied.

The luminance compensator 435 may perform an additional function to prevent side effects. That is, the luminance compensator 435 may determine whether an image is an edge and convert the edge degree into a gain to use the values in the correction process.

Finally, the image data output from the luminance compensator 435 is transmitted to the data driver 300 through the output unit 436. In this case, the image data output from the luminance compensator 435 may be directly transmitted to the data driver 300 through the output unit 436, but may be transmitted to other components inside the timing controller. After another conversion process, the data driver 300 may be transmitted to the data driver 300.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100 panel 200 gate driver
300: data driver 400: timing controller
430: data alignment unit 431: frame memory unit
432: block accumulation section 433: block memory section
434: Logo block judging unit 435: Luminance correction
436: output unit

Claims (10)

A frame memory unit for storing input image data included in an N-1 frame;
In the N-1 frame and the N frame currently being input, the difference value (Pixel Difference Value) of the input image data is greater than a preset value by comparing the input image data of each pixel corresponding to each other. A block accumulation unit which calculates a comparison value as 1 when the value is equal to 0 and a comparison value as 0 when it is smaller, and stores an accumulated value obtained by adding the comparison values to a block memory matched with a block corresponding to the pixel;
A logo block determination unit determining whether a logo is included in a block matched with the block memory using the cumulative value stored in each block memory;
A luminance correction unit for correcting luminance of input image data included in a block including a logo as a result of the determination; And
An output unit for outputting image data whose luminance is corrected by the luminance correction unit; Timing controller comprising a. The method of claim 1,
The block accumulation portion,
And a block memory portion formed of the block memories corresponding to the number of blocks formed in each of the frames. The method of claim 1,
And a comparison value of each of the pixels included in the block is accumulated and stored in each of the block memories. The method of claim 1,
The logo block determination unit,
And calculating a cumulative value stored for each block memory using an IIR filter to determine whether a logo is included for each block connected to the block memory. The method of claim 4, wherein
The logo block determination unit,
And assigning different weights to the cumulative value calculated in the N-1 frame and the cumulative value calculated in the N frame and substituting different weights into the IIR filter. Storing input image data included in an N-1 frame;
In the N-1 frame and the current N frame, input image data of each pixel corresponding to each other is compared, and a difference value of the input image data is larger than a preset value. Equal to or less than 1, calculating a comparison value as 0, and storing a cumulative value obtained by adding the comparison values to a block memory matched with a block corresponding to the pixel;
Determining whether a logo is included in a block matched with the block memory by using the accumulated value stored in each block memory;
Correcting luminance of input image data included in a block including a logo as a result of the determination; And
And outputting image data whose luminance is corrected. The method of claim 6,
And a comparison value for each of the pixels included in the block is accumulated in each of the block memories. The method of claim 6,
Determining whether or not a logo is included in the block,
And calculating a cumulative value stored for each block memory using an IIR filter to determine whether a logo is included for each block connected to the block memory. The method of claim 8,
Determining whether or not a logo is included in the block,
And assigning different weights to the cumulative value calculated in the N-1 frame and the cumulative value calculated in the N frame and substituting the weighted value into the IIR filter. A panel in which pixels are formed at respective regions where the gate lines and the data lines cross each other;
The timing controller according to any one of claims 1 to 5;
A data driver for converting the image data transmitted from the timing controller into an analog image signal and outputting the analog image signal to the data line; And
And a gate driver for outputting a scan signal to the gate line every one horizontal period in which the image signal is output according to a control signal transmitted from the timing controller.

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