KR102032221B1 - Capacitorless 1t dram cell device using tunneling field effect transistor, fabrication method thereof and memory array using the same - Google Patents

Abstract

The present invention forms a lower source region with an impurity of a type opposite to that of the source region and the same type as the drain region in the lower portion of the source region, and a potential well is formed under the body region between the lower source region and the drain region. The present invention provides a 1T DRAM cell device using a tunneling field effect transistor, which has a potential well in a body region like a 1T DRAM cell device using a structure, and can be operated like a TFET, a method of manufacturing the same, and a memory array using the same.

Description

1T DRAM Cell Device Using Tunneling Field Effect Transistor, Method for Fabrication and Memory Array Using The Same [1]

The present invention relates to a semiconductor memory device, and more particularly, to a 1T DRAM cell device using a tunneling field effect transistor without a capacitor, a method of manufacturing the same, and a memory array using the same.

Currently, a commercial DRAM (DRAM) is composed of a cell device that records one bit of information using one transistor and one capacitor (1T / 1C), and there is a difficulty in minimizing the capacitor as well as the transistor during the miniaturization process. High integration has been limited.

Therefore, recently, researches on 1T DRAMs in which a cell capable of storing one bit of information with only one transistor without a capacitor have been actively conducted. Compared with the existing 1T / 1C DRAM cells, the 1T DRAM cell has the advantage of being easy to be miniaturized, fast operating speed, and easy to integrate into the CMOS process, thereby reducing the production cost.

In the conventional 1T DRAM cell device, as shown in FIG. 1, sources / drains 10 and 40 doped with a high concentration of impurities opposite to the body are formed on both sides of the floating body 30 on the buried oxide film 2. By using the SOI MOSFET structure in which the gate 60 is formed on the body 30 with the gate insulating film 50 interposed therebetween, the electric charge in the potential well naturally formed in the floating body 30 isolated through source and drain doping. It has been implemented as a structure for storing.

However, since the conventional DRAM cell device as shown in FIG. 1 uses the structure and operating principle of the MOSFET, there is a fundamental limitation in further minimizing the DRAM cell. As the temperature increases, the read current and the leakage current in the idle state increase very much. Because of this, there is a limit that stable operation is difficult.

Meanwhile, in the field of logic devices, as shown in FIG. 2, a tunneling field effect transistor (TFET) having an asymmetric structure in which the source 20 and the drain 40 are formed of impurities of opposite types has been extensively studied. .

The present inventor has received Korean Patent No. 10-1085155 for the first time suggesting that the TFET can be used as a 1T DRAM cell device away from the switching device.

However, the patent allows a potential well to be formed in the body by inserting the isolation semiconductor region between the source or drain region and the body region, thereby requiring a new formation of the isolation semiconductor region. In addition, when the respective regions are stacked vertically, one cell element occupies an area of 4F ² , and thus high integration is possible, but a manufacturing process is not easy.

Accordingly, the present invention proposes a structure using a lower portion of the body as a potential well by doping with impurities of the same type as the drain region in the lower portion of the source region according to a conventional TFET manufacturing process, thereby having a structure of TFET instead of the conventional MOSFET. 1T DRAM cell device using tunneling field effect transistor that overcomes limitations of MOSFET reduction by replacing 1T DRAM cell device, operates at lower voltage than MOSFET, and enables stable operation even at high temperature by band-to-band tunneling. It is an object of the present invention to provide a manufacturing method and a memory array using the same.

In order to achieve the above object, the 1T DRAM cell device according to the present invention comprises: a source region and a drain region formed by being doped with impurities of opposite types to a semiconductor substrate at a predetermined distance; A body region in which a channel is formed between the source region and the drain region; A gate formed on the body region with a gate insulating layer interposed therebetween; A lower source region formed below the source region opposite to the source region and doped with impurities of the same type as the drain region; A bottom insulating film formed under the lower source region, the body region and the drain region; And a potential well formed to be electrically isolated from the lower portion of the body region between the lower source region and the drain region.

The source region is a P-type impurity high concentration doping layer (P + region), the lower source region and the drain region are an N-type impurity high concentration doping layer (N + region), and the body region is P doped at a lower concentration than the source region. It may be a type impurity low concentration doping layer (P region), or may be formed by being doped with impurities having opposite conductivity types, respectively.

The potential well may be electrically isolated by side insulating films formed on both sides of the body region and the drain region or by side insulating films formed on both sides of the source region, the lower source region, the body region, and the drain region. Can be.

The semiconductor substrate may be a silicon-on-insulator (SOI) substrate, and the bottom insulating layer may be a buried oxide layer of the SOI substrate.

The gate may have a shape of one of a finFET, a triple-gate, and a gate-all-around (GAA).

A method of manufacturing a 1T DRAM cell device according to the present invention includes a first step of defining an active region by etching a semiconductor substrate and forming a side insulating film; Forming a gate insulating film on the active region; Forming a gate on the gate insulating film; A fourth step of forming a drain region by forming an ion implantation shielding layer on the gate insulating layer and the gate, and then opening only one side of the gate to form an implant region having an impurity having a first conductivity type; And forming an ion implantation shielding layer on the gate insulating layer and the gate, and then opening only the other side of the gate to form an impurity implantation having the first conductivity type, the second conductivity type opposite to the lower source region and the first conductivity type. And a fifth step of forming source regions with different implantation energies by impurity implantation.

The semiconductor substrate is a silicon-on-insulator (SOI) substrate, and the etching of the semiconductor substrate and the formation of the side insulating layer in the first step are performed in the fifth step except for the lower source region and the source region. It can be formed to be electrically isolated from the.

In the memory array according to the present invention, a plurality of 1T DRAM cell elements are arranged, wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate, the bottom insulating film is a buried oxide film of the SOI substrate, A back bias contact and a back bias line are formed on one side to apply a voltage to the lower silicon layer of the SOI substrate, and the potential well of each 1T DRAM cell device is controlled through the back bias line.

In the memory array according to the present invention, a gate of each of the 1T DRAM cell elements arranged in a column direction is formed of a word line, and a drain region of each of the 1T DRAM cell elements arranged in a row direction is connected to the word line through a contact plug. The source region of each of the 1T DRAM cell elements connected to a vertical bit line is formed as a common source line in parallel with the word line in a column direction.

The lower source region of each of the 1T DRAM cell elements may be formed as an integral conductive line in parallel with the word line in the column direction, thereby controlling the potential well of each of the 1T DRAM cell elements.

The present invention forms a lower source region with an impurity of a type opposite to that of the source region and the same type as the drain region in the lower portion of the source region, and a potential well is formed under the body region between the lower source region and the drain region. By having a potential well in the body region like a 1T DRAM cell device using a structure, the operation can be performed like a TFET, overcoming the limitations of the cell shrinkage of the MOSFET, and operating at a lower voltage than the MOSFET. Band tunneling enables the realization of a 1T DRAM cell device capable of stable operation even at high temperatures. The manufacturing process can also use a conventional TFET process and can simplify array wiring.

1 is a cross-sectional view showing the structure of a 1T DRAM cell device using a conventional MOSFET.
2 is a cross-sectional view illustrating a structure of a conventional tunneling field effect transistor (TFET).
3 is a cross-sectional view illustrating a structure of a 1T DRAM cell device according to an embodiment of the present invention.
4 is a cross-sectional view illustrating a case in which impurity conductivity types of a source region, a lower source region, a body region, and a drain region are reversed in the embodiment of FIG. 3.
FIG. 5 is an electrical characteristic diagram comparing the concentration of holes (holes) accumulated in the potential well according to the information storage state in the embodiment of FIG. 3.
6 is an electrical characteristic diagram comparing potentials of a substrate according to concentrations of holes accumulated in a potential well according to an information storage state in the embodiment of FIG. 3.
7 is an electrical characteristic diagram comparing energy band diagrams of a channel surface according to an information storage state in the embodiment of FIG. 3.
FIG. 8 is an electrical characteristic diagram comparing band-to-band tunneling ratio of electrons on a channel surface according to an information storage state in the embodiment of FIG. 3.
9 is an electrical characteristic diagram comparing retention characteristics according to an information storage state in the embodiment of FIG. 3.
10 to 14 are cross-sectional views illustrating a process of manufacturing a 1T DRAM cell device according to the embodiment of FIG. 3.
FIG. 15 is a layout illustrating an example of a memory array in which a 1T DRAM cell device is a unit cell according to the exemplary embodiment of FIG. 3.
FIG. 16 is a cross-sectional view illustrating the array cut along the line AA ′ in FIG. 15.
FIG. 17 is a cross-sectional view illustrating the array cut vertically along the line BB ′ in FIG. 15.
FIG. 18 is a cross-sectional view illustrating the array cut along the line CC ′ in FIG. 15.
19 is a cross-sectional view illustrating the array cut along the line DD ′ in FIG. 15.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

1T DRAM cell device according to an embodiment of the present invention, as shown in Figure 3, the source region 20 and the drain region 40 formed by being doped with impurities of opposite types (polarity) to a predetermined distance apart from the semiconductor substrate 3, as shown in FIG. ); A body region 30 in which a channel is formed between the source region and the drain region; A gate 60 formed on the body region with a gate insulating layer 50 interposed therebetween; A lower source region 10 formed below the source region 20 and opposite to the source region 20 and doped with impurities of the same type as the drain region 40; A bottom insulating film (2) formed under the lower source region (10), the body region (30) and the drain region (40); And a potential well 32 formed to be electrically isolated under the body region 30 between the lower source region 10 and the drain region 40.

The core technical idea of the present invention is to form the lower source region 10 with impurities of the same type as the source region 20 and the same type as the drain region 40 below the source region 20, and the lower source region 10. The potential well 32 is formed below the body region 30 between the drain region 40 and the drain region 40, so that the potential well isolated to the body region 30, such as a 1T DRAM cell device using the MOSFET structure of FIG. 1. While having (32), the operation is made possible by the TFET of Fig. 2, so that the advantages of both can be utilized.

3, the source region 20 is a P-type impurity high concentration doping layer (P + region), the lower source region 10 and the drain region 40 are an N-type impurity high concentration doping layer (N + region). The region 30 is a 1T DRAM cell device formed of a P-type impurity low concentration doping layer (P region) doped at a lower concentration than the source region 20 and operating as an N-channel TFET.

The embodiment of FIG. 4 reverses the conductivity of each region in the embodiment of FIG. 3 so that the source region 20 'is an N-type impurity high concentration doping layer (N + region), and the lower source region 10' and the drain region. 40 'is a P-type impurity high concentration doping layer (P + region), and the body region 30' is formed of an N-type impurity low concentration doping layer (N region) doped at a lower concentration than the source region 20 '. It can also be implemented as a 1T DRAM cell device operating as a channel TFET.

In each of the embodiments described herein, including the embodiments of FIGS. 3 and 4, the body regions 30 and 30 ′ may include the source regions 20 and 20 ′, among the regions defined as active regions in the semiconductor substrate 3. It is defined as a portion excluding portions in which the lower source regions 10 and 10 'and the drain regions 40 and 40' are formed, and among the body regions 30 and 30 ', the source regions 20 and 20' and the drain region ( A channel region (not shown) is secured between 40 and 40 'to form a channel on the upper surface, and at the same time, a body region 30 is formed between the lower source region 10 and 10' and the drain region 40 and 40 '. 30 ') to form an isolated potential well 32, 32' with a depletion layer (not shown) that occurs at the junction.

Thus, in the embodiments of FIGS. 3 and 4, the body regions 30, 30 ′, in particular the lower region under the channel region, are between the lower source regions 10, 10 ′ and the drain regions 40, 40 ′, respectively. Since it is sufficient that the depletion layer can be formed by the junction of, it may be formed doped at a much lower concentration than the intrinsic semiconductor or source regions 20, 20 ′.

3 and 4, the semiconductor substrate 3 is preferably a silicon-on-insulator (SOI) substrate, but is not limited thereto. A semiconductor substrate deposited on the bottom insulating film 2 may also be used. . As is well known, the SOI substrate is composed of the lower silicon layer 1, the buried oxide film BOX 2, and the upper silicon layer 3, as shown in FIG. 16. Source regions 10 and 10 ', body regions 30 and 30', potential wells 32 and 32 'and drain regions 40 and 40' may be formed in upper silicon layer 3, for example.

When the semiconductor substrate 3 is an SOI substrate, the bottom insulating film 2 may be formed as a buried oxide film 2 of the SOI substrate. At this time, as described below, the potential wells 32 and 32 'may be controlled by making a contact with the lower silicon layer 1 of the SOI substrate and applying a voltage. An example of controlling the potential wells 32 and 32 'by making contact with the lower silicon layer 1 is shown in the dotted box B of FIGS. 15 and 16.

The bottom insulating layer 2 may exist only below the body regions 30 and 30 ', but as shown in FIGS. 3 and 4, the lower source regions 10 and 10' and the drain regions 40 and 40 ', respectively. It is also preferable in the process that it is formed also in the lower part.

The potential wells 32 and 32 'are shown in FIG. 3 or 4 in addition to the lower source regions 10 and 10', the bottom insulating film 2 and the drain regions 40 and 40 'shown in FIGS. 3 and 4. It is electrically isolated by the side insulating film (91 in FIG. 18) provided on both sides in the direction perpendicular to the cross sectional view of FIG.

FIG. 18 is a cross-sectional view of an array, which is vertically cut along a line CC ′ of FIG. 15, as described below. FIG. 15 is a unit cell of a 1T DRAM cell device according to the embodiment of FIG. 3. This is a layout showing an example of a memory array referred to as A).

FIG. 16 is a cross-sectional view of the array vertically cut along the AA ′ line in FIG. 15, FIG. 17 is a cross-sectional view of the array vertically cut along the BB ′ line in FIG. 15, and FIG. 19. A cross-sectional view of the array showing vertical cut along line DD 'at 15.

Referring to FIG. 16, it can be seen that the unit cell A of the memory array has a structure according to the embodiment of the above-described 1T DRAM cell device.

15 to 19, both side surfaces of the source region 20, the lower source region 10, the body region 30, and the drain region 40 of the above-described 1T DRAM cell device A (of FIG. 16). Side insulating films 91 are formed on both sides in a direction perpendicular to the cross-sectional view, whereby the potential wells 32 and 32 'are electrically isolated from both sides.

The side insulating layer 91 may be formed when defining an active region of each cell of the memory array.

According to an embodiment of the memory array described below, the side insulating layer 91 is formed only on both sides of the body region 30 and the drain region 40 of each cell (not shown), and the source region 20 of each cell. And / or the lower source region 10 may be configured to be electrically connected to each corresponding region of the cells arranged in the column direction (word line direction) in FIG. 14.

In this case, the source region 20 of each 1T DRAM cell element may be formed as a buried source line (not shown) parallel to the word line 60 in the column direction, so that the source line 100 and the source shown in FIG. It is not necessary to form the line contact plug 84 separately. In addition, the lower source region 10 of each 1T DRAM cell element is formed of an integral conductive line (not shown) in parallel with the word line 60 in the column direction, and in this case, the lower silicon layer 1 of the SOI substrate described above. Alternatively, the potential well 32 may be controlled by applying a voltage to the conductive line.

The gate 60 may be formed in the shape of one of finFET, triple-gate, and gate-all-around (GAA) like a conventional MOSFET or TFET device.

Referring to FIGS. 15 and 16, the memory array including the 1T DRAM cell device as the unit cell A according to the embodiment of FIG. 3 is a word line of the gate 60 of each 1T DRAM cell device arranged in the column direction. The drain region 40 of each 1T DRAM cell element formed in the row direction and connected to the bit line 200 perpendicular to the word line 60 through the contact plug 82 is connected to each of the 1T DRAM cell elements. The source region 20 may be wired to be connected to the source line 100 which is parallel to the word line 60 and perpendicular to the bit line 200 through the contact plug 84.

The memory array may be formed on one SOI substrate, and as described above, the buried oxide film 2 of the SOI substrate is used as the bottom insulating film, and the lower silicon layer of the SOI substrate is formed on one side B of the memory array. A back bias contact 86 and a back bias line 120 for applying a voltage to (1) are formed to be configured to control the potential well 32 of each 1T DRAM cell element via the back bias line 120. Can be.

In this case, the back bias contact 86 may be directly in the lower silicon layer 1, which is a rear surface of the SOI substrate. However, as shown in FIG. 16, the back bias contact 86 is deeply formed to penetrate the buried oxide film 2 at one side B of the memory array. It may be surrounded by the insulating insulating film 90 and connected to the doping layer (P + region) 22 having the same type of impurities (eg, P-type impurities) as the lower silicon layer 1.

When the back bias line 120 is formed to be parallel to the source line 100 and perpendicular to the bit line 200 as shown in FIGS. 15 and 16, the source line 100 and the back bias line ( Since the wiring 120 is formed by different layers from the bit line 200, the first interlayer insulating layer 92 and the second interlayer insulating layer 94 are formed to divide the layers.

In the embodiment of FIG. 16, since the source region 20 of each 1T DRAM cell device is connected to the source line 100 through the contact plug 84, the contact plug 84 may include a gate ( In order to be electrically isolated from the word line 60, the sidewall insulating layer 70 and the upper insulating layer 72 are formed on both sidewalls and the upper side of the gate (word line 60) of each 1T DRAM cell element.

15 to 19, both side surfaces of the source region 20, the lower source region 10, the body region 30, and the drain region 40 of each 1T DRAM cell element A (FIG. 16). As described above, the side insulating film 91 is formed on both side surfaces in the direction perpendicular to the cross-sectional view of the cross-sectional view of the cross-sectional view of the cross section of the side surface insulating film 91 so that the potential well 32 of each 1T DRAM cell element A is electrically connected to both sides. Isolate.

Although not shown in the drawings, an embodiment of another memory array including the 1T DRAM cell device of the present invention as the unit cell A, as described above, the source region 20 of each 1T DRAM cell device is a word line in a column direction. Parallel to 60 may be formed as a buried source line (not shown). In this case, it is not necessary to separately form the source contact plug 84 and the source line 100 shown in FIG. 16, and further, the back bias line 120 formed on one side B of the array also includes the contact plug 86. When the highly doped layer (P + region) 22 is formed as a back bias line without a process, a process such as forming the sidewall insulating film 70 and the upper insulating film 72 of the first interlayer insulating film 92 and the gate (word line) 60 is performed. There is an advantage that can be reduced.

In the latter embodiment, the lower source region 10 of each 1T DRAM cell element may also be formed as an integral conductive line (not shown) parallel to the word line 60 in the column direction, and may be formed through the conductive line. The potential well 32 of each 1T DRAM cell element A may be controlled.

3 and 16, the basic operation principle of the 1T DRAM cell device of the present invention will be briefly described.

The basic operation principle is to change the electric potential of the channel surface in accordance with the amount of charge stored in the isolated potential well 32 of the body region 30 to change the amount of current flowing in the drain during the read operation, thereby providing information of '0' and '1'. Read them separately. The following is a description of the operation of a 1T DRAM cell device of an N-channel TFET with electrons as the majority carrier.

<Write '1' action>

When a negative voltage (eg, -3.0 V) is applied to the word line 60 connected to the gate and a positive voltage (eg 1.0 V) is applied to the bit line 200 connected to the drain 40, holes in the drain region are provided. (Holes) enter the channel through tunneling. At this time, when a high negative voltage (eg, −5.0 V) is applied to the back bias line 120 connected to the lower silicon layer 1 of the SOI substrate, the introduced holes are applied to the potential well 32 of the body region 30. Will be saved.

<Hold operation>

It is to retain holes before the read (read) or write '0' operation after the holes are trapped in the potential well 32 of the body region 30, and the retention time characteristics of the 1T DRAM cell are determined. To this end, a negative voltage is applied to the back bias line 120.

<Read operation>

This is to check whether holes are stored in the potential well 32 of the body region 30. The back bias line 120 is applied with the same voltage as the hold operation (for example, -5.0 V) to hold the stored holes. In the state, a predetermined read voltage (eg, 1.0 V) is applied to the gate 60, and a driving voltage (eg, 1.0 V) is applied between the drain region 40 and the source region 20 through the selected bit line and the source line. The storage state of the hole is read by applying and sensing the drain current flowing between the drain region 40 and the source region 20.

<Write '0' action>

Since the holes stored in the potential well 32 of the body region 30 are discharged to the source region 20, a word (eg, 3.0 V) is applied to the back bias line 120, and the word is connected to the gate. A negative voltage (eg, -1.0 V) is applied to the bit line 100 connected to the line 60 and the source region 20.

After storing the information of '0' and '1' by the above method, and comparing the states of each cell during the read operation, there is a difference in the electrical characteristics as shown in FIGS. That is, as shown in FIG. 5, when the information of '1' is stored, a lot of holes are accumulated in the potential well 32 of the body region 30 as compared with the case where '0' is stored. As shown in Fig. 6, the potential of the potential well 32 of the cell in which '1' is stored increases significantly.

As a result, as shown in FIG. 7, the potential of the channel surface increases together under the influence of the positive charge stored in the potential well 32, thereby increasing the incidence of band-to-band tunneling as shown in FIG. 8. In addition, both retaining capability characteristics are as shown in FIG.

Next, referring to FIGS. 10 to 14, a method of manufacturing the 1T DRAM cell device according to the exemplary embodiment of FIG. 3 will be briefly described.

First, as shown in FIG. 10, the semiconductor substrate is etched and a side insulating film (not shown) is formed to define the active region 31 (first step). In this case, the active region 31 is a region of a semiconductor substrate on which a source region, a lower source region, a channel region, and a potential well including a potential well are to be formed. Both sides of the all regions or the source region and The side insulating layer may be formed on both sides of the remaining region except for the lower source region (both sides in a direction perpendicular to the surface of FIG. 10). When the semiconductor substrate is an SOI substrate, the active region 31 is defined on the buried oxide film, which is the bottom insulating film 2.

Next, as shown in FIG. 11, a gate insulating film 50 is formed on the active region 31 (second step), and a gate 60 is formed on the gate insulating film 50 (third step). The gate insulating film 50 emerging from the side of the gate 60 may be removed immediately before the next step after the formation of the gate 60, but may be removed after a subsequent ion implantation process to be used as a surface protection layer during ion implantation. This is preferable.

Next, after forming an ion implantation shielding layer (not shown) on the gate insulating film 50 and the gate 60, only one side of the gate 60 is opened to impurity implantation having a first conductivity type, FIG. As described above, the drain region 40 is formed (fourth step).

Subsequently, as shown in FIG. 13, an ion implantation shielding layer (not shown) is formed on the gate insulating layer 50 and the gate 60, and only the other side of the gate 60 is opened to provide relatively high implantation energy. When the impurity having the first conductivity type is implanted to form the lower source region 10, as shown in FIG. 14, when the impurity having the second conductivity type opposite to the first conductivity type is formed, the lower source region 10 is formed. The source region 10 is formed by implanting with a smaller implantation energy (fifth step).

The fourth step and the fifth step may be performed in reverse order. In the fifth step, the order of forming the lower source region 10 and the source region 10 may also be changed.

The rest of the process is according to the manufacturing method of the 1T DRAM cell device of the MOSFET, so the description thereof will be omitted.

1: bottom silicon layer of SOI substrate 2: bottom insulating film (burying oxide film)
3: semiconductor substrate (top silicon layer of SOI substrate) 10, 10 ': bottom source region
20, 20 ': source area 30, 30': body area
31: active area 32, 32 ': potential well
40, 40 ': drain region 50: gate insulating film
60: gate (word line) 82, 84, 86: contact plug
90: insulating film 100: source line
120: back bias line 200: bit line

Claims (14)

A source region and a drain region formed on the semiconductor substrate by being doped with impurities of opposite types to each other at a distance horizontally;
A body region in which a channel is formed between the source region and the drain region;
A gate formed on the body region with a gate insulating layer interposed therebetween;
A lower source region formed below the source region opposite to the source region and doped with impurities of the same type as the drain region;
A bottom insulating film formed under the lower source region, the body region and the drain region; And
A potential well formed to be electrically isolated from a lower portion of the body region between the lower source region and the drain region,
The potential well is electrically isolated from the lower source region and the drain region by a pn junction, but is formed of an impurity of the same type as the source region and electrically connected thereto.
And the lower source region is formed of an integral conductive line to be electrically connected to cells arranged in one direction to control the potential well by voltage application.
The method of claim 1,
The source region is a P-type impurity high concentration doping layer (P + region),
The lower source region and the drain region are N-type impurity high concentration doping layer (N + region),
And the body region is a P-type impurity low concentration doping layer (P region) doped at a lower concentration than the source region.
The method of claim 1,
The source region is an N-type impurity high concentration doping layer (N + region),
The lower source region and the drain region are P-type impurity high concentration doping layer (P + region),
And the body region is an N-type impurity low concentration doping layer (N region) doped at a lower concentration than the source region.
The method according to any one of claims 1 to 3,
And the potential well is electrically isolated by side insulating films formed on both sides of the body region and the drain region.
The method of claim 4, wherein
The semiconductor substrate is a silicon-on-insulator (SOI) substrate,
And the bottom insulating film is a buried oxide film of the SOI substrate.
delete delete The method according to any one of claims 1 to 3,
And the gate has a shape of one of finFET, triple-gate and gate-all-around (GAA).
A first step of etching the semiconductor substrate and forming a side insulating film to define an active region;
Forming a gate insulating film on the active region;
Forming a gate on the gate insulating film;
A fourth step of forming a drain region by forming an ion implantation shielding layer on the gate insulating layer and the gate, and then opening only one side of the gate to form a drain region by impurity implantation having a first conductivity type opposite to the active region; And
After forming an ion implantation shielding layer on the gate insulating film and the gate, only the other side of the gate is opened, and impurity implantation having the first conductivity type is opposite to the lower source region and the first conductivity type and is the same as the active region. And a fifth step of forming source regions with different implantation energies by impurity implantation having a second conductivity type.
A first step of etching the semiconductor substrate and forming a side insulating film to define an active region;
Forming a gate insulating film on the active region;
Forming a gate on the gate insulating film;
A fourth step of forming a drain region by forming an ion implantation shielding layer on the gate insulating layer and the gate, and then opening only one side of the gate to form a drain region by impurity implantation having a first conductivity type opposite to the active region; And
After forming an ion implantation shielding layer on the gate insulating film and the gate, only the other side of the gate is opened, and impurity implantation having the first conductivity type is opposite to the lower source region and the first conductivity type and is the same as the active region. A fifth step of forming source regions with different implantation energies by impurity implantation having a second conductivity type,
The semiconductor substrate is a silicon-on-insulator (SOI) substrate,
The etching of the semiconductor substrate and the formation of the side insulating layer in the first step may be performed to electrically isolate the neighboring cell except for the lower source region and the source region in the fifth step. Manufacturing method.
delete In a memory array in which a plurality of 1T DRAM cell elements of claim 1 are arranged,
The gates of each of the 1T DRAM cell elements arranged in the column direction are formed of word lines,
The drain region of each of the 1T DRAM cell elements arranged in a row direction is connected to a bit line perpendicular to the word line through a contact plug,
And the source region of each of the 1T DRAM cell elements is formed as a common source line in parallel with the word line in a column direction.
The method of claim 12,
And a lower source region of each of the 1T DRAM cell elements is formed as an integral conductive line in parallel with the word line in a column direction.
The method of claim 13,
And a potential well of each of the 1T DRAM cell elements through the conductive line.

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