KR102034660B1 - Method for controlling accelerator of heterogeneous system, and heterogeneous system for performing the same - Google Patents

Abstract

A host processor coupled to the plurality of computing devices and the plurality of computing devices for executing an application, the host processor controlling power supplied to the plurality of computing devices, the host processor comprising: the plurality of computing devices Among these, it provides a heterogeneous system for identifying at least one calculation device used for the execution of the application, and controlling the idle power of the remaining calculation device other than the at least one calculated device is minimized during execution of the application. .

Description

Accelerator control method for heterogeneous systems and heterogeneous systems for performing the same {METHOD FOR CONTROLLING ACCELERATOR OF HETEROGENEOUS SYSTEM, AND HETEROGENEOUS SYSTEM FOR PERFORMING THE SAME}

Embodiments disclosed herein relate to a method of controlling a plurality of accelerators included in a heterogeneous system and a heterogeneous system for performing the same.

Heterogeneous system means a system including a CPU and a plurality of accelerators.

When running an application in a heterogeneous system, only some accelerators are typically used that can achieve the highest performance among a plurality of accelerators included in the heterogeneous system. However, unused accelerators can also consume a few to tens of watts of idle power, accounting for a significant portion of the overall power consumption.

Also, accelerators are typically connected to the CPU via a PCI-E bus, which limits the number of PCI-E lanes supported by the CPU. The bandwidth must be divided, and thus, the speed and quality of communication may be degraded and power consumption may increase. In particular, in a situation where only some of the accelerators included in the heterogeneous system are used to execute an application, maintaining connection with the CPU through the PCI-E switch to the unused accelerators is unnecessary for time delays, power consumption, and interconnection. There is a problem that interference occurs.

All of these problems arise because accelerators that are not used by applications consume hardware resources of the system.

Related prior art document US Pat. No. 9,672,046 includes a power plane associated with one of a plurality of processor components for performing a plurality of processor functions, for each power plane based on workload characteristics and power constraints, and the like. Disclosed is the adjustment of power dynamically.

On the other hand, the background art described above is technical information that the inventors possess for the derivation of the present invention or acquired in the derivation process of the present invention, and is not necessarily a publicly known technique disclosed to the general public before the application of the present invention. .

Embodiments disclosed herein relate to a method for controlling a plurality of accelerators included in a heterogeneous system to increase power efficiency and communication performance, and a heterogeneous system for performing the same.

As a technical means for achieving the above-described technical problem, according to an embodiment, the heterogeneous system is connected to the plurality of computing devices and the plurality of computing devices for executing an application, and to the plurality of computing devices And a host processor for controlling the power supplied, wherein the host processor identifies at least one computing device used to execute the application among the plurality of computing devices, and wherein the at least one identified during execution of the application. It is possible to control so that the idle power of the remaining calculation device except for the calculation device of the minimum.

According to another embodiment, the method for controlling a computing device of a heterogeneous system includes identifying at least one computing device used to execute an application among a plurality of computing devices included in the heterogeneous system, and during the execution of the application. And controlling the idle power of the remaining computing devices to be minimum except the identified at least one computing device.

According to yet another embodiment, a computer program for performing a method for controlling a computing device of a heterogeneous system, wherein the method for controlling a computing device of a heterogeneous system includes at least one of a plurality of computing devices included in the heterogeneous system for execution of an application. Identifying one computing device and controlling the idle power of the remaining computing devices to be minimum except for the at least one checked computing device during execution of the application.

According to yet another embodiment, a computer-readable recording medium on which a program for performing a method for controlling a computing device of a heterogeneous system is recorded. Identifying at least one computing device used for the execution of and controlling the idle power of the remaining computing devices other than the identified at least one computing device to be minimum during execution of the application.

According to any one of the aforementioned problem solving means, among the plurality of accelerators included in the heterogeneous system, the average power consumption of the heterogeneous system can be reduced by controlling the idle power of the accelerators not used to execute the application to be minimum. You can expect.

In addition, among the plurality of accelerators included in the heterogeneous system, only the accelerators used to execute the application maintain the connection with the CPU, and thus, mutual interference, time delay, and the like that may occur in the process of switching the connection between the CPU and the accelerators. The effect of reducing power consumption can be expected.

In addition, you are not limited to the overall system power budget and the number of PCI-E lanes provided by the CPU (or PCI-E controller), and only the accelerators that your application actually uses after you have installed all the accelerators in your system By consuming power and getting PCI-E lanes allocated, it is possible to run various applications that require different accelerators in one heterogeneous system.

The effects obtainable in the disclosed embodiments are not limited to the effects mentioned above, and other effects not mentioned above are apparent to those skilled in the art to which the embodiments disclosed from the following description belong. Can be understood.

1 is a diagram illustrating a configuration of a heterogeneous system according to an embodiment.
2 is a flowchart illustrating an accelerator control method of a heterogeneous system according to an exemplary embodiment.
3 is a diagram illustrating a state in which idle power of some accelerators included in a heterogeneous system is minimized according to an embodiment.
4 is a flowchart illustrating a method of controlling a connection between a CPU and an accelerator in a heterogeneous system according to an embodiment.
FIG. 5 is a diagram illustrating a state in which only accelerators used to execute an application in a heterogeneous system are controlled to maintain a connection with a CPU. Referring to FIG.

Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. The embodiments described below may be embodied in various different forms. In order to more clearly describe the features of the embodiments, detailed descriptions of the matters well known to those skilled in the art to which the following embodiments belong are omitted. In the drawings, parts irrelevant to the description of the embodiments are omitted, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a configuration is "connected" to another configuration, this includes not only 'directly connected' but also 'connected' between different configurations. In addition, when a configuration "includes" a certain configuration, this means that, unless specifically stated otherwise, it may further include other configurations other than the other configuration.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a heterogeneous system according to an embodiment. Referring to FIG. 1, a heterogeneous system 100 according to an embodiment includes a CPU 110, a PCI-E controller 120, a PCI-E switch 130, and a plurality of accelerators 141, 142, 143, and 144. ) May be included. In FIG. 1, the heterogeneous system 100 is illustrated as including four accelerators 141, 142, 143, and 144, but it is obvious that the heterogeneous system 100 may include various numbers of computing devices.

The CPU 110 is a general purpose processor that controls the overall operation of the heterogeneous system 100 and is also referred to as a "host processor." An operating system of the heterogeneous system 100 may be executed in the CPU 110. The CPU 110 may control the operations of the accelerators 141, 142, 143, and 144. In addition, a main memory (not shown) may be connected to the CPU 110.

The PCI-E controller 120 is an interface for providing a connection between the CPU 110 and the accelerators 141, 142, 143, and 144. The PCI-E controller 120 may exist separately from the CPU 110 or may be integrated in the CPU 110. That is, in FIG. 1, the PCI-E controller 120 is illustrated as a separate configuration from the CPU 110, but the CPU 110 may directly perform the role of the PCI-E controller 120. The PCI-E controller 120 provides a predetermined number of PCI-E lanes.

The PCI-E switch 130 is a component that relays communication between the CPU 100 and the accelerators 141, 142, 143, and 144. That is, as shown in FIG. 1, the PCI-E controller 120 and the PCI-E switch 130 are connected through the first lane, and the PCI-E switch 130 and the accelerators 141, 142, 143, 144 is connected through a second lane, and the PCI-E switch 130 relays between the first lane and the second lane.

The reason for using the PCI-E switch 130 is that the number of PCI-E lanes required by the accelerators 141, 142, 143, and 144 (the number of PCI-E lanes included in the second lane) is PCI. This is because the number of PCI-E lanes provided by the -E controller 120 is greater than the number of PCI-E lanes included in the first lane. That is, when all the accelerators 141, 142, 143, and 144 cannot be connected using only the PCI-E lanes provided by the PCI-E controller 120, the PCI-E controller 120 is connected to the PCI-E switch 130. PCI-E lanes coming from the ()), PCI-E switch 130 is connected to the accelerators (141, 142, 143, 144) again.

The accelerators 141, 142, 143, and 144 may also be referred to as computing devices, and, unlike general purpose CPUs, may be configured as processors specialized for a specific pattern of computation. For example, an accelerator could be a GPU, an Intel Xeon Phi coprocessor, or an FPGA.

The accelerators 141, 142, 143, and 144 perform operations specific to each under the control of the CPU 110. In other words, when an application is executed in the heterogeneous system 100, each of the accelerators 141, 142, 143, and 144 performs a specific pattern of operations specific to itself, and the remaining operations and I / O tasks are executed by the CPU 110. It can be performed by). In addition, a device memory (not shown) may be connected to each of the accelerators 141, 142, 143, and 144.

The accelerators 141, 142, 143, and 144 included in the heterogeneous system 100 may have different operating methods, the same operating methods, but different detailed architectures, and different operating methods and detailed architectures. It may be. Thus, by choosing and implementing the best accelerator for your application, you can maximize the efficiency of your entire system.

As such, when only some of the accelerators 141, 142, 143, and 144 included in the heterogeneous system 100 may be selected and used to obtain the highest performance, the remaining accelerators may be idle and consume idle power. Done. Accordingly, one embodiment described below provides a method of reducing the average power consumption of the heterogeneous system 100 by minimizing the idle power of the accelerator that is not used to run the application.

In addition, when only some of the accelerators 141, 142, 143, and 144 included in the heterogeneous system 100 are selected and used to obtain the highest performance, the remaining accelerators that are not used are connected to the CPU 110. Since the PCI-E switch 130 must continue to perform routing operations between the CPU 110 and the accelerators 141, 142, 143, and 144, the overhead of the PCI-E switch 130 is increased. In other words, interference between communication occurs, and a routing operation may cause time delay and additional power consumption. Therefore, the embodiment described below proposes a method of improving communication performance and power efficiency by allowing only the accelerator used to execute an application to maintain the connection with the CPU 110.

Hereinafter, a method of controlling the accelerators 141, 142, 143, and 144 included in the heterogeneous system 100 will be described in detail with reference to FIGS. 2 to 5. In the embodiments described below, it is assumed that only the first accelerator 141 and the third accelerator 143 are used when executing an application in the heterogeneous system 100.

2 is a flowchart illustrating an accelerator control method of a heterogeneous system according to an exemplary embodiment. 2, in operation 201, the CPU 110 determines at least one accelerator used by an application from among a plurality of accelerators 141, 142, 143, and 144 included in the heterogeneous system 100. That is, the CPU 110 confirms that only the first accelerator 141 and the third accelerator 143 are used among the plurality of accelerators 141, 142, 143, and 144 when the application is executed in the heterogeneous system 100.

In this case, the CPU 110 may check whether each accelerator is used before or while the application is executed in the heterogeneous system 100. Which accelerator to use may be specified in the application, in the runtime system running the application, or by the user of the heterogeneous system 100.

In operation 202, the CPU 100 controls the idle power of the remaining accelerators 142 and 144 other than the determined accelerators 141 and 143 to be minimum. For example, the CPU 110 may control the power supplied to the accelerators 141, 142, 143, and 144 in accordance with the Advanced Configuration and Power Interface (ACPI) standard.

At this time, ACPI is a standard specification that enables power management of hardware components constituting a computer by software, and includes a power management specification for each individual device mounted in a computer such as an accelerator. ACPI defines four power states for the device: D0, D1, D2, and D3. D0 means the device is turned on and working, and D3 means the device is turned off and not working. D1 and D2 mean an intermediate state between D0 and D3. In other words, the power consumed by the device decreases from D0 to D3.

The CPU 110 may control the power state of the accelerators 141, 142, 143, and 144 to any one of D0 to D3 by transmitting a command to the device driver of the accelerators 141, 142, 143, and 144.

Therefore, in step 202, the CPU 110 transmits a command to the first accelerator 141 and the third accelerator 143 to switch to the D0 state, and the D3 state to the second accelerator 142 and the fourth accelerator 144. Command to switch to. Alternatively, if the second accelerator 142 and the fourth accelerator 144 that are not used require a power state higher than D3, the CPU 110 may issue a command to switch to the D1 or D2 state to the second accelerator 142 and the second accelerator 142 and the fourth accelerator 144. Transmit to the fourth accelerator 144. That is, the CPU 110 may control the accelerators 142 and 144 that are not used to consume as minimum power only the minimum power required by the accelerators 142 and 144 that are not used.

3 illustrates a state in which the CPU 110 controls idle power of some accelerators 142 and 144 to a minimum, according to an exemplary embodiment. Referring to FIG. 3, it can be seen that the first accelerator 141 and the third accelerator 143 are controlled to the D0 state, and the second accelerator 142 and the fourth accelerator 144 are controlled to the D3 state.

In the above embodiment, the power supply of the accelerators 141, 142, 143, and 144 is controlled according to the ACPI standard. However, this is merely an example, and the CPU 110 may not use the accelerators 142 in various ways. , 144 can be controlled to minimize the idle power.

In operation 203, the PCI-E switch 130 may control only the accelerators 141 and 143 determined to be used when the application is executed to maintain the connection with the CPU 110. A detailed method of controlling the connection between the CPU 110 and the accelerators 141, 142, 143, and 144 by the PCI-E switch 130 will be described with reference to FIGS. 4 and 5.

4 is a flowchart illustrating a method of controlling a connection between a CPU and an accelerator in a heterogeneous system according to an embodiment, and includes detailed steps of step 203 of FIG. 2. FIG. 5 is a diagram illustrating a state in which only accelerators used to execute an application in a heterogeneous system are controlled to maintain a connection with a CPU. Referring to FIG.

Referring to FIG. 4, in operation 401, the PCI-E switch 130 determines the number M of PCI-E lanes required by the accelerators 141 and 143 used by the application, and the PCI-E controller 120. Compare with the number N of PCI-E lanes provided.

Referring to FIG. 5, since the first accelerator 141 and the third accelerator 143 each require 16 PCI-E lanes, M becomes 32. In addition, in FIG. 5, since the number of PCI-E lanes provided by the PCI-E controller 120 is 32, N is 32. Therefore, according to the embodiment shown in FIG. 5, the PCI-E switch 130 determines that M is less than or equal to N.

In step 402, the PCI-E switch 130 determines whether M is less than or equal to N, and if it is determined that M is less than or equal to N, the process proceeds to step 403.

In operation 403, the PCI-E switch 130 may select PCI-E lanes connected to the accelerators 141 and 143 used by the application among the PCI-E lanes included in the second lane, and the PCI-E included in the first lane. Match E lanes one-to-one.

In operation 404, the PCI-E switch 130 may relay data transmission between the CPU and the accelerator according to a one-to-one correspondence between the first lane and the second lane. For example, the PCI-E switch 130 may store a routing table including a one-to-one correspondence between the first lane and the second lanes and relay data transmission according to the stored routing table. Alternatively, if the PCI-E switch 130 supports the function of setting the one-to-one correspondence between the PCI-E lanes, the PCI-E switch 130 may relay data transmission using the same.

On the other hand, if M is greater than N as a result of the determination in step 402, the process proceeds to step 405 in which the PCI-E switch 130 switches between the first line and the second line according to the conventional method to relay data transmission. Can be.

As such, the PCI-E switch 130 may minimize the overhead of the PCI-E switch 130 by allowing only the accelerators 141 and 143 used to execute the application to maintain the connection with the CPU 110. In addition, the limited PCI-E lane of the CPU 110 can be utilized efficiently. As a result, an effect of reducing power consumption, time delay, and mutual interference due to the routing operation of the PCI-E switch 130 may be expected.

The term '~' used in the above embodiments refers to software or a hardware component such as a field programmable gate array (FPGA) or an ASIC, and '~' serves a part. However, '~' is not meant to be limited to software or hardware. '~ Portion' may be configured to be in an addressable storage medium or may be configured to play one or more processors. Thus, as an example, '~' means components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, procedures, and the like. Subroutines, segments of program patent code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

The functionality provided within the components and 'parts' may be combined into a smaller number of components and 'parts' or separated from additional components and 'parts'.

In addition, the components and '~' may be implemented to play one or more CPUs in the device or secure multimedia card.

The accelerator control method of the heterogeneous system according to the embodiments described with reference to FIGS. 2 to 5 may also be implemented in the form of a computer readable medium for storing instructions and data executable by a computer. In this case, the command and data may be stored in the form of program code, and when executed by the processor, a predetermined program module may be generated to perform a predetermined operation. In addition, computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. In addition, the computer readable medium may be a computer recording medium, which is volatile and non-implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. It can include both volatile, removable and non-removable media. For example, the computer recording medium may be a magnetic storage medium such as HDD and SSD, an optical recording medium such as CD, DVD and Blu-ray Disc, or a memory included in a server accessible through a network.

Also, the accelerator control method of the heterogeneous system according to the embodiments described with reference to FIGS. 2 to 5 may be implemented as a computer program (or computer program product) including instructions executable by a computer. The computer program includes programmable machine instructions processed by the processor and may be implemented in a high-level programming language, an object-oriented programming language, an assembly language, or a machine language. . The computer program may also be recorded on tangible computer readable media (eg, memory, hard disks, magnetic / optical media or solid-state drives, etc.).

Therefore, the accelerator control method of the heterogeneous system according to the embodiments described with reference to FIGS. 2 to 5 may be implemented by executing the computer program as described above by the computing device. The computing device may include at least a portion of a processor, a memory, a storage device, a high speed interface connected to the memory and a high speed expansion port, and a low speed interface connected to the low speed bus and the storage device. Each of these components are connected to each other using a variety of buses and may be mounted on a common motherboard or otherwise mounted in a suitable manner.

Here, the processor may process instructions within the computing device, such as to display graphical information for providing a graphical user interface (GUI) on an external input, output device, such as a display connected to a high speed interface. Instructions stored in memory or storage. In other embodiments, multiple processors and / or multiple buses may be used with appropriately multiple memories and memory types. The processor may also be implemented as a chipset consisting of chips comprising a plurality of independent analog and / or digital processors.

The memory also stores information within the computing device. In one example, the memory may consist of a volatile memory unit or a collection thereof. As another example, the memory may consist of a nonvolatile memory unit or a collection thereof. The memory may also be another form of computer readable medium, such as a magnetic or optical disk.

In addition, the storage device can provide a large amount of storage space to the computing device. The storage device may be a computer readable medium or a configuration including such a medium, and may include, for example, devices or other configurations within a storage area network (SAN), and may include a floppy disk device, a hard disk device, an optical disk device, Or a tape device, flash memory, or similar other semiconductor memory device or device array.

The above-described embodiments are for illustrative purposes, and those of ordinary skill in the art to which the above-described embodiments belong may easily change to other specific forms without changing the technical spirit or essential features of the above-described embodiments. I can understand. Therefore, it is to be understood that the above-described embodiments are illustrative in all respects and not restrictive. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope to be protected by the present specification is represented by the following claims rather than the above description, and should be construed to include all changes or modifications derived from the meaning and scope of the claims and their equivalents. .

100: heterogeneous system 110: CPU
120: PCI-E controller 130: PCI-E switch
141, 142, 143, 144: accelerator

Claims (15)

In heterogeneous systems,
A plurality of computing devices for executing the application;
A host processor coupled to the plurality of computing devices, the host processor controlling power supplied to the plurality of computing devices; And
A connection switch for controlling a connection between the host processor and the plurality of computing devices,
The host processor identifies at least one computing device used to execute the application among the plurality of computing devices, and during execution of the application, the idle power of the remaining computing devices other than the at least one checked computing device is determined. Control it to the minimum,
And the connection switch controls such that only the identified at least one computing device maintains a connection with the host processor during execution of the application. delete The method of claim 1,
The host processor,
And controlling power supplied to the computing devices through a power management standard defining at least three power states of the computing devices. The method of claim 3,
The host processor,
Heterogeneous system, characterized in that for transmitting the transition command to the power supply state with the lowest power consumption among the three or more power states defined in the power management standard, except for the at least one identified computing device. . The method of claim 1,
The connection switch,
And at least one lane connected between the identified at least one computing device and the connection switch in a one-to-one correspondence with at least one lane connected between the connection switch and a host processor. The method of claim 5,
A routing table including a one-to-one correspondence between the lanes is stored in the connection switch, and the connection switch relays data communication between the host processor and a plurality of computing devices according to the stored routing table. system. The method of claim 5,
The connection switch is a heterogeneous system, characterized in that for supporting the function of establishing a one-to-one correspondence between the lanes. In the computing device control method of heterogeneous system,
Identifying, by a host processor included in the heterogeneous system, at least one computing device used to execute an application among a plurality of computing devices included in the heterogeneous system;
During execution of the application, the host processor controlling the idle power of the remaining computing devices to be minimum except for the at least one identified computing device; And
During execution of the application, a connection switch for controlling a connection between the host processor and the plurality of computing devices controls only the identified at least one computing device to maintain a connection with a host processor included in the heterogeneous system. Comprising a step. delete The method of claim 8,
The controlling step,
Controlling power supplied to the computing devices through a power management specification that defines at least three power states of the computing devices. The method of claim 10,
The controlling step,
And transmitting a command for switching to a power state having the lowest power consumption among three or more power states defined in the power management standard, to the other computing devices except the at least one calculated device. The method of claim 8,
Controlling to maintain the connection,
And at least one lane connected between the identified at least one computing device and the connection switch in a one-to-one correspondence with at least one lane connected between the connection switch and a host processor. The method of claim 12,
Controlling to maintain the connection,
Storing a routing table including a one-to-one correspondence between the lanes; And
Relaying data communication between the host processor and a plurality of computing devices in accordance with the stored routing table. A computer-readable recording medium having recorded thereon a program for causing a heterogeneous system to perform the method of claim 8. A computer program executed by a heterogeneous system and stored on a medium for carrying out the method of claim 8.

Images