KR102029395B1 - Gate driver and liquid crystal display device inculding thereof - Google Patents

Abstract

The present invention discloses a gate driver. More specifically, the present invention relates to a gate-in-panel (GIP) gate driver mounted in a liquid crystal panel as a thin film transistor to supply a gate driving signal to a pixel, and a liquid crystal display including the same.
According to an exemplary embodiment of the present invention, the gate driving unit is minimized by replacing the dummy stage of the gate driver with a structure for generating a gate driving signal, that is, a reset signal, rather than an even-odd sharing structure. There is an effect to reduce the area.

Description

GATE DRIVER AND LIQUID CRYSTAL DISPLAY DEVICE INCULDING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver, and more particularly, to a gate-in-panel (GIP) gate driver that is mounted as a thin film transistor in a liquid crystal panel to supply a gate driving signal to a pixel, and a liquid crystal display including the same.

Various portable devices such as mobile phones and laptop computers, and information electronic devices that realize high resolution and high quality images such as HDTVs, have been developed and used as flat panel display devices. The demand for) is increasing. Such flat panel displays include liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), and organic light emitting diodes (Organic Light Emitting Diodes); OLED). Among them, liquid crystal displays (LCDs) are currently being most widely studied for reasons of mass production technology, ease of driving means, high definition, and large screen realization.

In particular, an active matrix liquid crystal display device using a thin film transistor (TFT) as a switching element is suitable for displaying a dynamic image. In order to control such switching elements, a liquid crystal display device includes a gate driver, and recently, a gate driver is provided in the form of a thin film transistor on a liquid crystal panel rather than a driving IC separate from the liquid crystal panel.

1 is a view schematically illustrating a structure of a gate driver included in a conventional liquid crystal display.

Referring to FIG. 1, a conventional gate driver may include a plurality of stages that output gate driving voltages Vg1 to Vg n to gate wirings formed on a display panel in synchronization with predetermined clock signals CLK1 to CLK8. It is a shift register composed of ST1 to STn (n is a natural number). Each of the stages ST1 to STn described above is composed of a plurality of transistors.

Here, the clock signals CLK1 to CLK8 are eight-phase structures using eight different timing signals. A four-phase or six-phase six-phase structure with four clock signals is also widely used according to design intention. The gate driver using the signals CLK1 to CLK8 has an advantage of lower power consumption than other methods.

In addition, although a conventional gate driver has one output having one output, in the drawing, a predetermined number of thin film transistors in two neighboring stages are shared, and Qb nodes (not shown) are alternately driven by being divided into even and odd numbers. The gate driver, which reduces the size of the gate driver by reducing the number of thin film transistors, is illustrated.

The gate driver of this structure receives the start signal (not shown) and the first and second clock signals CLK1 and CLK2 from the first stage ST1 and overlaps the three horizontal periods 3H for four horizontal periods 4H. The high level first and second gate driving signals Vg1 and Vg2 having a section are output, and the second stage ST2 outputs the high level third gate driving signal Vg3. Here, the third gate driving signal Vg3 is a signal overlapping the second gate driving signal Vg2 with the three horizontal periods 3H, and the second stage ST2 subsequently orders the fourth gate driving signal Vg4. Will output

In particular, when driving the next stage STn-1 of the second stage ST2, the gate driving signal thereof is applied to the front stage again as a reset signal so that the first stage ST1 and the second gate driving signals Vg1 and Vg2 are reset. ) To low level output.

When the m-th gate driving signal (Vgm, m is a natural number) is outputted to the nth stage n ST repeatedly, the operation for one frame is completed. In this case, since the subsequent stages do not exist in the nth and nth-1th stages n ST, dummy stages DT1 and DT2 for separately generating a reset signal should be provided.

However, the dummy stages DT1 and DT2 have the same structure as the other stages ST1 to STn in the gate driver and occupy the same area, even though they do not directly generate and output gate driving signals. In this case, it serves as a disadvantageous factor in minimizing the width of the non-display area excluding the display area, but cannot be removed because of the above-described reset signal providing role.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the structure of the dummy stage for generating the reset signal supplied to the last two stages of the gate driver is simplified to minimize the number of thin film transistors, thereby reducing the area of the gate driver. It is an object of the present invention to realize a narrow bezel type liquid crystal display device.

In order to achieve the above object, a gate driver according to an embodiment of the present invention includes a plurality of stages in which one stage is connected to two of the plurality of gate wirings formed on the liquid crystal panel to output a gate driving signal; And a dummy stage having one output for applying a reset signal to at least one of the plurality of stages.

In addition, in order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention, the liquid crystal panel in which a plurality of gate wiring and data wiring is formed in a matrix form, the pixel is defined at the intersection; A gate driver including a plurality of stages in which one stage is connected to two of the plurality of gate gate lines to sequentially supply a gate driving signal to the pixel; A data driver connected to the data line to supply a data signal to the pixel; And a timing controller configured to control the gate driver and the data driver, wherein the gate driver includes a dummy part formed from a dummy stage having one output for applying a reset signal to at least one of the plurality of stages. do.

According to an exemplary embodiment of the present invention, the gate driving unit is minimized by replacing the dummy stage of the gate driver with a structure for generating one gate driving signal, that is, a reset signal, rather than an even-odd sharing structure. There is an effect to reduce the area.

1 is a view schematically illustrating a structure of a gate driver included in a conventional liquid crystal display.
2 is a diagram illustrating an overall structure of a liquid crystal display device including a gate driver according to an exemplary embodiment of the present invention.
3A is a diagram illustrating the structure of a gate driver and a dummy part of the present invention, and FIG. 3B is a diagram illustrating a clock signal and a gate driving signal input and output to and from the gate driver of FIG. 3A.
4 is a diagram illustrating an example of an equivalent circuit diagram of one stage of a gate driver of the present invention, and FIG. 5 is a diagram illustrating an example of an equivalent circuit diagram of one stage of a dummy unit of the present invention.

Hereinafter, a gate driver and a liquid crystal display including the same according to an exemplary embodiment of the present invention will be described with reference to the drawings.

2 is a diagram illustrating an overall structure of a liquid crystal display device including a gate driver according to an exemplary embodiment of the present invention.

Referring to FIG. 2, in the liquid crystal display of the present invention, a plurality of pixels P are formed to display an image, and a non-display area N / that is an outer portion of the display area A / A. The liquid crystal panel 100 in which A) is defined, the timing control unit 110 which controls each driving unit, and the gate driving signal Vg mounted in the liquid crystal panel 100 and supplied to the pixel P, The gate driver 120 includes a dummy stage for supplying a reset signal to the stage, and a data driver 130 connected to the liquid crystal panel 100 to supply a data signal Vdata to the pixel P.

In the liquid crystal panel 100, a plurality of gate lines GL and a plurality of data lines DL are arranged in a matrix in a direction perpendicular to the gate lines GL on the transparent substrate, and pixels (at the intersection points) P) is defined. A plurality of pixels P constitute one display area A / A, and at least one thin film transistor T serving as a switching element is formed in each pixel P, and the thin film transistor T The screen is displayed through the liquid crystal capacitor LC controlled by the LCD. An image is not displayed outside the display area A / A, and a non-display area N / A defined by extending the gate driver 120 and various wirings is defined.

The thin film transistor T is turned on according to the high level gate driving signal Vg from the gate line GL, and in synchronization with the liquid crystal capacitor, the thin film transistor T receives the data signal Vdata supplied from the data line DL. LC). The liquid crystal capacitor LC is a capacitor structure formed of a common electrode facing the liquid crystal material and a pixel electrode connected to the thin film transistor T. Although not shown, the liquid crystal capacitor LC may be further connected to a storage capacitor (not shown) in order to stably maintain the voltage level at which the charged data signal Vdata is charged until the next frame.

Each pixel P has an arrangement state of the liquid crystal material varying according to the data signal Vdata charged through the thin film transistor T, thereby adjusting the light transmittance of the liquid crystal capacitor LC to realize gray scale.

The timing controller 110 receives an image signal applied from the outside and a predetermined timing signal to generate an aligned image signal RGB, a gate control signal GCS, and a data control signal DCS, thereby generating respective drivers 120. , 130).

In addition, the timing controller 110 generates and supplies not only the gate control signal GCS for controlling the gate driver 120 but also one or more clock signals CLK for driving the gate driver VG. In an embodiment, an eight-phase structure of eight clock signals CLK may be applied.

On the other hand, although not shown, the timing controller 110 is designed to be connected to an external system through a predetermined interface and to receive image-related signals and timing signals outputted therefrom at high speed without noise. These interfaces include LVDS (Low Voltage Differential Signal) or TTL (Transistor-Transistor Logic) interface.

In addition, a gate driver 120 including a plurality of thin film transistors is formed on the non-display area N / A of at least one side end of the liquid crystal panel 100, and the output terminals of the liquid crystal panel 100 are formed in the display area A / A. Is electrically connected to the gate wiring GL.

The gate driver 120 applies the gate driving signal Vg to the gate line GL arranged on the liquid crystal panel 100 in response to the gate control signal GCS applied from the timing controller 110, thereby applying a thin film transistor ( T) is turned on or off, and accordingly, an analog waveform data signal Vdata supplied from the data driver 140 is connected to each thin film transistor T. It is applied to the liquid crystal capacitor (CLC).

The gate control signal GCS described above includes a gate start signal, a gate shift clock, a gate output enable, and the like.

In addition, the gate driving signal VG has two voltage levels of high level and low level, and the gate wiring GL is sequentially formed at every high level for 1 to 4 horizontal periods (1 to 4H) at a high level for one frame. Is output to Here, the gate driving signal VG outputted to the adjacent gate line GL overlaps one to three horizontal periods (1 to 3H), and the data signal Vdata is one horizontal period with respect to pixels on one horizontal line. (1H) each.

The gate driver 120 may be set such that there is no overlap period between the gate driving signals VG, but as the liquid crystal panel 100 realizes a high resolution image and is formed in a large area, the charging time of the gate line GL is increased. In order to prevent malfunction due to the lack of, it is preferable that the supply time of each gate driving signal Vg is increased and overlapped with each other.

In addition, the gate driver 120 is composed of a double output stage of a shared Qb node, one of which outputs two gate driving signals Vg, and two dummy supplies respectively supplying reset signals to the last two stages. It further includes a stage 125. Here, unlike the other stages, the dummy stage 125 has a small number of thin film transistors provided as a single output structure in which one stage outputs only one signal, rather than a Qb node shared structure, and thus the liquid crystal panel ( The width in the longitudinal direction of the 100) is to be implemented smaller than the conventional.

Meanwhile, the data driver 130 converts the aligned image signal RGB inputted according to the data control signal DCS input from the timing controller 110 into an analog data signal Vdata using a reference voltage. . The data signal Vdata is latched by one horizontal period 1H, and is simultaneously output to the liquid crystal panel 100 through all of the data lines DL in response to the gate driving signal Vg.

The data control signal DCS includes a source start pulse SSP, a source shift clock SSC, a source output enable SOE, and the like.

According to the above structure, the liquid crystal display device including the gate driver of the present invention implements two dummy stages connected to the last stage of the gate driver 120 in a single output structure instead of a double output structure, thereby reducing the number of thin film transistors. Minimizing and thus reducing the width of the liquid crystal panel in the vertical direction.

Hereinafter, a gate driver of a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

3A is a diagram illustrating the structure of a gate driver and a dummy part of the present invention, and FIG. 3B is a diagram illustrating a clock signal and a gate driving signal input and output to and from the gate driver of FIG. 3A.

Referring to FIGS. 3A and 3B, the gate driver 120 of the present invention may include gate driving voltages Vg1 to Vg m on gate wirings formed on a display panel in synchronization with predetermined clock signals CLK1 to CLK8. It includes a plurality of stages (ST1 ~ STn) for outputting.

In the drawing, the configuration of the present invention is described as an example of an eight-phase structure gate driver that drives in synchronization with eight clock signals CLK1 to CLK8. However, the clock signal has a two-phase, four-phase or six-phase structure instead of an eight-phase structure. The technical idea of the present invention can also be applied to a gate driver.

In addition, although not shown, each of the stages ST1 to STn is supplied with a normal power supply voltage VDD and a ground voltage VSS for driving the gate driver 120. Each of the stages ST1 to STn shares a predetermined number of thin film transistors in one stage, divides the Qb node (not shown) into even and odd numbers, and alternates the two output terminals to a high level gate driving signal Vg1 to STn. It consists of a double output structure that outputs Vgm).

The first and second start signals Vst1 and 2 are input to the first stage ST1 as start signals, and the first and second gate driving signals are synchronized with the first and second clock signals CLK1 and CLK2. Outputs (Vg1, Vg2) sequentially. In addition, the first stage ST1 receives the m-th gate driving signal Vgm-2 of the n-th stage STn-1 as a reset signal.

That is, each stage receives the second gate driving signal of the rear stage stage as a reset signal, outputs a low level gate driving signal, and supplies the gate driving signal as a start signal of the rear stage stage.

The n-th stage STn-1 outputs the m-th and m-th gate driving signals Vgm-3 and Vgm-2 and the m-th gate driving signal Vgm-2. Is supplied to the reset signal of the first stage ST1 and the start signal of the first dummy stage DT1. In addition, the n-th stage STn outputs the m-th and m-th gate driving signals Vgm-1 and Vgm, and outputs the m-th gate driving signal Vgm to the reset signal and the th-th stage of the second stage ST2. The second dummy stage DT2 is supplied as a start signal.

The first and second dummy stages DT1 and DT2 receive the m-th and m-th gate driving signals Vgm-2m and Vgm as start signals, respectively, and the n-th stage and the n-th stage STn- The first and second reset signals rst1 and rst2 are output to 1, STn. In addition, the first and second dummy stages DT1 and DT2 receive the first and second start signals Vst1 and Vst2 as reset signals.

According to this structure, the gate driver 120 of the present invention receives the start signals Vst1 and Vst2 and the first and second clock signals CLK1 and CLK2 during the four horizontal periods 4H. The high level first and second gate driving signals Vg1 and Vg2 having three overlapping periods of 3 horizontal periods 3H are output to each other, and then the second stage ST2 outputs the high level third and fourth gate driving signals. This structure outputs (Vg3, Vg4). The first and second gate driving signals Vg1 and Vg2 may be signals overlapping each other by three horizontal periods 3H.

When the m-th gate driving signal Vgm is outputted to the n-th stage n ST repeatedly, the operation for one frame is completed, and the first and second reset signals rst1 and rst2 of the dummy stage are When output, the next frame begins.

In particular, the dummy part 125 of the present invention has a single output structure in which one stage has one output signal. Therefore, the number of the thin film transistors is smaller than in the related art, and the overall area of the gate driver 120 can be designed smaller. Will be.

On the other hand, the gate driving signals Vgm-3 to Vgm are output in synchronization with the clock signals CLK1 to CLK8, and the data signal Vdata of the horizontal line corresponding to each gate driving signal Vgm-3 to Vgm is one. Images are displayed as they are output by the horizontal period 1H.

Hereinafter, an example of a gate driver and a dummy part according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating an example of an equivalent circuit diagram of one stage of a gate driver of the present invention, and FIG. 5 is a diagram illustrating an example of an equivalent circuit diagram of one stage of a dummy unit of the present invention.

First, referring to FIG. 4, one stage STn included in the gate driver of the present invention includes an even end (ODD) and an nth gate driving signal Vgn for outputting the m-1 gate driving signal Vgm-1. The means for outputting is made (EVEN).

In particular, the illustrated stage STn is a double output structure in which the Qb_o node Qb_o and the Qb_e node Qb_e are shared with each other and the number of thin film transistors is reduced, and the thin film is provided in the even end and the means EVEN. The total number of transistors is 26, with 13 each. In addition, the even end (ODD) and the base unit (EVEN) has the same structure in addition to the connection structure of the shared Qb_o node (Qb_o) and Qb_e node (Qb_e).

The first_1 thin film transistor T1_1 is turned on by the first start signal Vst1 to charge the Q1 node Q1 with the power supply voltage VDD, and the first_2 thin film transistor T1_2 has the second start signal Vst2. Is turned on to charge the Q2 node Q2 to the power supply voltage VDD.

The second thin film transistor T2 receives the rear gate driving signal Vnext to discharge the Q1 node Q1 to the ground voltage VSS.

The third o thin film transistor T3o conducts as the Qb_o node Qb_o is charged to discharge the Q1 and Q2 nodes Q1 and Q2, and the third e thin film transistor T3e conducts as the Qb_e node Qb_e is charged. To discharge the Q1 and Q2 nodes Q1 and Q2.

The 4A thin film transistor T4A turns on the 4_1 and 4_2 thin film transistors T4_1 and T4_2 as the even power supply voltage VDD_O and the odd power supply voltage VDD_E alternately transition to a high level. In addition, the 4_1 and 4_2 thin film transistors T4_1 and T4_2 charge the Qb_o node Qb_o or Qb_e node Qb_e through the high power supply voltage VDD_O or the odd power supply voltage VDD_E. In addition, the fourth Q thin film transistor T4Q discharges the Q2 node Q2 when the Q1 node Q1 is charged, or discharges the Q1 node Q1 when the Q2 node Q2 is charged.

As the first start signal Vst1 is applied, the fifth thin film transistor T5 discharges the Qb_o node Qb_o and Qb_e node Qb_e to the ground voltage VSS, and the fifth Q thin film transistor T5Q transmits Q1. As the node Q1 or the Q2 node Q2 is charged, the Qb_o node Qb_o or Qb_e node Qb_e is discharged, and the fifth QI thin film transistor T5QI is discharged by the Q1 node Q1 or Q2 node Q2. As the battery is charged, the fourth transistor T4 is turned off.

The sixth_1 thin film transistor T6_1 functions as a pull-up buffer, and is turned on as the Q1 node Q1 is charged to turn on the first clock signal CLK1 having a high level. It outputs as one gate drive signal Vgm-1. In addition, the sixth_2th thin film transistor T6_2 is turned on as the Q2 node Q2 is charged to output the high level second clock signal CLK2 as the mth gate driving signal Vgm.

The seventh thin film transistor T7o functions as a pull-up buffer and outputs the m-1 gate driving signal Vgm-1 to a low level as the Qb_o node Qb_o is charged. At the same time, the m-th gate driving signal Vgm is maintained at a low level. In addition, the seventh thin film transistor T7e maintains the m-1 gate driving signal Vgm-1 at a low level as the Qb_e node Qb_e is charged, and at the same time, the mth gate driving signal Vgm is Allow low level output.

The driving of the stage of the gate driver according to the above-described structure will be described below.

First, as the first start signal Vst1 of the high level is input, the first_1 thin film transistor T1_1 of the even end (ODD) is turned on to charge the Q1 node Q1 to the high level, and the fourth Q thin film. The transistor T4Q and the fifth Q thin film transistor T5Q are turned on to discharge the Qb_o node Qb_o and the Qb_e node Qb_e. At this time, the excellent power supply voltage (VDD_O) is a high level state, the 4A thin film transistor (T4A) is a diode state, but the current flows through the 4Q thin film transistor (T4Q) 4th and 4_2 thin film transistors (T4_1, T4_2) Will remain turned off.

Next, when the high level first clock signal CLK1 is applied, the gate-source voltage of the sixth thin film transistor T6_1 is changed to output the m-1 gate driving signal Vgm-1 of the high level. .

Subsequently, as the high level second start signal Vst2 is input, the first_2 thin film transistor T1_2 of the base unit EVEN is turned on to charge the Q2 node Q2 to the high level, and the fourth Q thin film transistor T4Q and the fifth Q thin film transistor T5Q are turned on to maintain the discharge state of the Qb_o node Qb_o and Qb_e node Qb_e. Next, when the high level second clock signal CLK2 is applied, the gate-source voltage of the sixth second thin film transistor T6_2 is changed to output the m-th gate driving signal Vgm of the high level. Here, the second start signal Vst2 and the second clock signal CLK2 are delayed by the first start signal Vst1 and the first clock signal CLK1 signal and one horizontal period 1H, so that the four horizontal periods 4H are delayed. M-th gate driving signal Vgm-1 and m-th gate driving signal Vgm are output so that three horizontal periods 3H overlap each other.

When the three horizontal periods 3H have elapsed, although not shown, the second thin film as the post-stage stage signal Vnext is transmitted from the n + 2th stage STn + 2 to the m + 3th gate driving signal Vgm + 3. It is applied to the transistor T2, and the Q1 node Q1 and the Q2 node Q2 are discharged. At this time, since the excellent power supply voltage VDD_O is in a high level state and the fifth QI thin film transistor T5QI is turned off, the fourth_1 thin film transistor T4_1 is turned on to turn the Qb_o node Qb_o into the excellent power supply voltage VDD_O. ) Will be charged.

Accordingly, the seventh thin film transistor T7o is turned on to sequentially transition the m-th gate driving signal Vgm-1 and the m-th gate driving signal Vgm to a low level in sequence. The seventh thin film transistor T7o and the sevene thin film transistor T7e have their power-on voltage VDD_O and the odd power supply voltage VDD_E determined their turn-on and turn-off times.

Hereinafter, a structure of a dummy stage according to an embodiment of the present invention will be described with reference to the drawings. Although only the first dummy stage DT1 is shown in the drawing, the second dummy stage (not shown) also has the same circuit structure.

Referring to FIG. 5, the dummy stage DT1 included in the gate driver of the present invention supplies the first reset signal rst1 to the front stage.

In particular, the dummy stage DT1 of the present invention is a single output structure in which one stage outputs one reset signal, and the number of thin film transistors provided is 17. Therefore, compared with the stage of the double output structure having 26 thin film transistors, nine thin film transistors can be omitted, and at least two reset signals are required, thereby reducing 18 thin film transistors. It can be seen.

The first thin film transistor T1 is turned on by the m-2 gate driving signal Vgm-2 to charge the Q node Q with the power supply voltage VDD.

The 2N thin film transistor T2N is turned on by the start signal Vst to discharge the Q node Q to the ground voltage VSS.

The third_O thin film transistor T3_O conducts as the Qb_O node Qb_O is charged to discharge the Q node Q, and the third_E thin film transistor T3_E conducts as the Qb_E node Qb_E is charged to the Q node (Q3). Q) is discharged.

The 4N_O thin film transistor T4N_O and the 4N_E thin film transistor T4N_E respectively charge the Qb_O node Qb_O and Qb_E node Qb_E with the excellent power supply voltage VDD_O and the odd power supply voltage VDD_E according to the start signal. Play a role.

In addition, the fourth_O thin film transistor T4_O and the fourth_E thin film transistor T4_E charge the Qb_O node Qb_O and Qb_E node Qb_E with the excellent power supply voltage VDD_O and the odd power supply voltage VDD_E, respectively. .

 The fifth Vdd_O thin film transistor T5Vdd_O and the fifth Vdd_E thin film transistor T5Vdd_E are connected to the Qb_O node Qb_O and Qb_E node Qb_E according to the odd power supply voltage VDD_E and the even power supply voltage VDD_O, respectively. To discharge. In addition, the fifth Q_O thin film transistor T5Q_O and the fifth Q_E thin film transistor T5Q_E discharge the Qb_O node Qb_O and Qb_E node Qb_E to the ground voltage VSS as the Q node Q is charged, respectively. do. In addition, the fifth_O thin film transistor T5_O and the fifth_E thin film transistor T5_E receive the Qb_O node Qb_O and Qb_E node Qb_E as the high level m-2 gate driving signal Vgm-2 is applied. Discharges to ground voltage VSS.

The sixth thin film transistor T6 functions as a pull-up buffer and is turned on as the Q1 node Q1 is charged to reset the second clock signal CLK2 of the high level to the first reset. Output as signal rst1.

The seventh_O thin film transistor T7_O functions as a pull-up buffer and, as the Qb_O node Qb_O is charged, outputs the first reset signal rst1 to a low level. The 7_E thin film transistor T7_E outputs the first reset signal rst1 to a low level as the Qb_E node Qb_E is charged.

The driving of the dummy stage of the gate driver according to the above-described structure will be described below.

First, as the high level m-2 start signal Vgm-2 is input, the first thin film transistor T1 is turned on to charge the Q node Q to a high level, and the fifth Q_O thin film transistor ( T5Q_O) and the fifth Q_E thin film transistor T5Q_E are turned on to discharge the Qb_o node Qb_o and Qb_e node Qb_e. At this time, when the excellent power supply voltage VDD_O is in the high level state, the fourth_O thin film transistor T4_O is in the diode state, but current flows through the fifth Q_O thin film transistor T5Q_O so that the Qb_O node Qb_O is at the low level, that is, the ground. The discharge state corresponding to the voltage VSS is maintained. This is the same as maintaining the low level of the Qb_E node Qb_E even if the fourth power supply voltage VDD_E is in the high level, even if the fourth_E thin film transistor T4_E is in the diode state.

Next, when the second clock signal CLK2 at the high level is applied, the gate-source voltage of the sixth thin film transistor T6 is changed to output the first reset signal rst1 at the high level.

Subsequently, as the high level start signal Vst is input, the 2N thin film transistor T2N is turned on so that the Q node Q is discharged to the ground voltage VSS level, and thus, the sixth thin film transistor. T6 is turned off. At the same time, the excellent power supply voltage VDD_O is charged to the Qb_O node Qb_O, and the Qb_E node Qb_E maintains a discharge state.

Accordingly, the seventh_O thin film transistor T7_O is turned on to transition the first reset signal rst1 to a low level. The seventh_O thin film transistors T7_O and the seventh_E thin film transistors T7_E have their power-on voltage VDD_O and the odd power supply voltage VDD_E determined their turn-on and turn-off times.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

A / A: display area N / A: non-display area
P: Pixel GL: Gate Wiring
DL: Data Wiring GCS: Gate Control Signal
DCS: Data Control Signal RGB: Image Signal
Vg: Gate drive signal Vdata: Data signal
100: liquid crystal panel 110: timing control unit
120: gate driver 125: dummy part
130: data driver

Claims (10)

N stages in which each stage is connected to two of the plurality of gate wirings and outputs a gate driving signal (n is a natural number of two or more); And
It includes a plurality of dummy stages having a single output structure for outputting only one reset signal,
The plurality of dummy stages
A first dummy stage configured to supply one first reset signal to an n-1th stage among the n stages, and
A second dummy stage configured to supply one second reset signal to an nth stage of the n stages,
The first dummy stage is a gate driver positioned between the nth stage and the second dummy stage. The method of claim 1,
The gate driver,
And an eight-phase clock signal structure. delete The method of claim 1,
The first and second dummy stages,
And a base gate driving signal (Vgm-2, Vgm (m is a natural number)) of the n-th stage and the n-th stage, respectively, as a start signal to drive the gate driver. The method of claim 1,
The first and second dummy stages,
And driving in synchronization with the second clock signal and the fourth clock signal, respectively. delete The method of claim 1,
The first and second dummy stages,
And driving the start signals of the plurality of stages as a reset signal. The method of claim 1,
The one stage,
Basic means on which a Q1 node, a Qb_o node and a Qb_e node are formed; And
A Q2 node is formed, and is divided into even ends that share the Qb_o node and the Qb_e node,
A first first thin film transistor T1_1 turned on by a first start signal to charge the Q1 node with a power supply voltage;
A first second thin film transistor T1_2 turned on by a second start signal to charge the Q2 node with a power supply voltage;
A second thin film transistor T2 receiving a gate driving signal from a rear stage stage and discharging the Q1 node to a ground voltage;
A third thin film transistor T3o that is turned on as the Qb_o node is charged to discharge the Q1 and Q2 nodes;
A third e thin film transistor (T3e) that conducts as the Qb_e node is charged to discharge the Q1 and Q2 nodes;
4th and 4_2 thin film transistors T4_1 and T4_2 that charge the Qb_o node or the Qb_e node, respectively, in response to a high power supply voltage or odd power supply voltage;
A fourth 4th thin film transistor T4A for turning on the fourth and fourth second thin film transistors T4_1 and T4_2 according to the even power supply voltage and the odd power supply voltage;
A fourth Q thin film transistor (T4Q) configured to discharge the Q2 node when the Q1 node is charged, and discharge the Q1 node (Q1) when the Q2 node is charged;
A fifth thin film transistor T5 configured to discharge the Qb_o node and the Qb_e node to a ground voltage when the first start signal is applied;
A fifth Q thin film transistor (T5Q) configured to discharge the Qb_o node or the Qb_e node as the Q1 or Q2 node is charged;
A fifth QI thin film transistor T5QI turning off the fourth Q thin film transistor T4Q as the Q1 node or the Q2 node is charged;
A sixth thin film transistor T6_1 turned on as the Q1 node is charged to output a high level clock signal as the m-1 gate driving signal Vgm-1;
A sixth second thin film transistor T6_2 that is turned on as the Q2 node is charged to output a high level clock signal as an mth gate driving signal Vgm;
A seventh thin film transistor T7o configured to output the m-1 th gate driving signal Vgm-1 to a low level as the Qb_o node is charged; And
As the Qb_e node is charged, the seventh e thin film transistor T7e outputs the m-th gate driving signal Vgm to a low level.
Gate driver comprising a. The method of claim 1,
In the dummy stage, a Q node, a Qb_O node, and a Qb_E node are formed.
A first thin film transistor T1 that is turned on by an m-th gate driving signal Vgm-2 to charge the Q node with a power supply voltage;
A 2N thin film transistor (T2N) turned on by a start signal to discharge the Q node to a ground voltage;
A third _O thin film transistor (T3_O) which is turned on as the Qb_O node is charged to discharge the Q node;
A third_E thin film transistor (T3_E) which is turned on as the Qb_E node is charged to discharge the Q node;
A fourth N_O thin film transistor T4N_O and a fourth N_E thin film transistor T4N_E, which charge the Qb_O node and the Qb_E node with an excellent power supply voltage and an odd power supply voltage, respectively, according to a start signal;
A fourth_O thin film transistor T4_O and a fourth_E thin film transistor T4_E charging the Qb_O node and the Qb_E node, respectively, according to the excellent power supply voltage and the odd power supply voltage;
A fifth Vdd_O thin film transistor (T5Vdd_O) and a fifth Vdd_E thin film transistor (T5Vdd_E) for discharging the Qb_O and Qb_E nodes to a ground voltage, respectively, according to an odd power supply voltage and a good power supply voltage;
A fifth Q_O thin film transistor T5Q_O and a fifth Q_E thin film transistor T5Q_E which discharge the Qb_O node and the Qb_E node Qb_E to ground voltages as the Q node is charged;
A fifth_O thin film transistor T5_O and a fifth_E thin film transistor T5_E for discharging the Qb_O node and the Qb_E node to ground voltages as the high level m-2 gate driving signal Vgm-2 is applied;
A sixth thin film transistor T6 turned on as the Q node is charged to output a clock signal as a first reset signal;
A seventh_O thin film transistor (T7_O) configured to output the first reset signal to a low level as the Qb_O node is charged; And
As the Qb_E node is charged, the seventh_E thin film transistor T7_E outputs the first reset signal to a low level.
Gate driver comprising a. A liquid crystal panel in which a plurality of gate lines and data lines are cross-formed in a matrix form and pixels are defined at intersections thereof;
A gate driver comprising n stages in which each stage is connected to two of the plurality of gate gate wirings and sequentially supplies a gate driving signal to the pixel (n is a natural number of two or more);
A data driver connected to the data line to supply a data signal to the pixel; And
A timing controller for controlling the gate driver and the data driver;
The gate driver,
It includes a dummy portion consisting of a plurality of dummy stages having a single output structure for outputting only one reset signal,
The plurality of dummy stages
A first dummy stage configured to supply one first reset signal to an n-1th stage among the n stages, and
And a second dummy stage configured to supply one second reset signal to an nth stage of the n stages,
And the first dummy stage is positioned between the nth stage and the second dummy stage.

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