KR102028719B1 - Method for manufacturing FBAR - Google Patents

Abstract

According to the present invention, a method for manufacturing a FBAR comprises the steps of: forming a cavity on one surface of a first substrate; forming a piezoelectric layer on one surface of a second substrate; forming a first electrode on the piezoelectric layer; disposing the surface of the first substrate and surface of the second substrate to face each other for bonding one surface of the first substrate to the first electrode; removing the second substrate for the piezoelectric layer to be exposed; and forming the second electrode on an exposed surface of the piezoelectric layer.

Description

FBAR manufacturing method {Method for manufacturing FBAR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film bulk acoustic resonator (FBAR) for use in filters, duplexers, and the like for communication in a radio frequency (RF) band, and more particularly, to a method for manufacturing a FBAR.

Wireless mobile communication technology requires a variety of RF (Radio Frequency) components that can efficiently transmit information in a limited frequency band. In particular, the filter among the RF components is one of the core components used in the mobile communication technology, and enables a high quality communication by selecting a signal required by the user or filtering a signal to be transmitted among a myriad of air waves.

The most widely used RF filters for wireless communication are dielectric filters and surface acoustic wave (SAW) filters. Dielectric filters have the advantages of high dielectric constant, low insertion loss, high temperature stability, vibration resistance and impact resistance. However, dielectric filters have limitations in recent technological advances such as miniaturization and monolithic microwave IC (MMIC). In addition, the SAW filter has advantages in that it is smaller in size, easier in signal processing, simpler in circuit, and mass-produced by using a semiconductor process. In addition, the SAW filter has a high side rejection in the passband compared to the dielectric filter, and thus has an advantage of exchanging and receiving high quality information. However, since the SAW filter process involves exposure using ultraviolet (UV) light, the line width of IDT (Inter Digital Transducer) is limited to about 0.5 μm. Therefore, there is a problem that it is impossible to cover the ultra-high frequency band (more than 5 kHz) by using the SAW filter, and there is a difficulty in forming a single chip and an MMIC structure formed in a semiconductor substrate.

In order to overcome the above limitations and problems, a FBAR (Film Bulk Acoustic Resonator) filter has been proposed that can be integrated with other active elements on an existing semiconductor (Si, GaAs) substrate to fully MMIC the frequency control circuit.

FBAR is a thin film device that can be used for wireless communication devices and military radars in various frequency bands (900MHz ~ 10kHz) because it can be characterized by low cost, small size, and high Q coefficient. In addition, it can be downsized to one hundredth of the size of the dielectric filter and the lumped constant (LC) filter, and has the characteristics that the insertion loss is much smaller than that of the SAW filter. Therefore, FBAR is the most suitable device for MMIC requiring high stability and high quality factor.

Film Bulk Acoustic Resonator (FBAR) filter deposits piezoelectric materials zinc oxide (ZnO) and aluminum nitride (AlN) on silicon (Si) and gallium arsenide (GaAs) semiconductor substrates by RF sputtering method. Cause resonance. That is, the FBAR deposits a piezoelectric thin film between both electrodes, and induces a bulk acoustic wave to generate resonance.

1 shows the structure of a typical FBAR. The FBAR typically includes a lower electrode 21, a piezoelectric layer 22, an upper electrode 23, and the electrodes 21, deposited on a substrate 10 on which a cavity 11 and an insulating film 12 are formed. And a metal pad 24 to which a signal line of an external circuit device connected to 23 is connected.

Silicon (Si), high resistance silicon (HRS), gallium arsenide (Ge-As), glass, or ceramics may be used as the substrate 10, and low temperature oxide (LTO) may be used as the insulating layer 12. Silicon oxide, silicon nitride (SiXNY), etc. are used.

The electrodes 21 and 23 include molybdenum (Mo), ruthenium (Ru), aluminum (Au), gold (Au), platinum (Pt), tungsten (W), tantalum (Ta), and platinum-tantalum (Pt- Metals having excellent electrical conductivity such as Ta), titanium (Ti), platinum-titanium (Pt-Ti), and the like are used.

Aluminum piezoelectric layer (AlN) or zinc oxide (ZnO) is used as the piezoelectric layer 22, and gold (Au) is most used as the metal pad 24.

In a conventional FBAR manufacturing process, in order to make the cavity 11 in the substrate 10, the surface of the substrate 10 is etched to form pits, and then the poly-silicon, in-silicate glass ( A sacrificial layer is formed by depositing phosphor-silicate glass (PSG), zinc oxide, or polymer by chemical vapor deposition (CVD), sputtering, or spin coating. Then, the surface of the substrate 10 and the sacrificial layer are planarized through a chemical mechanical polishing (CMP) process, and then the insulating film 12, the lower electrode 21, the piezoelectric layer 22, and the upper electrode 23 are disposed thereon. Deposited in turn, and then forming a cavity 11 by removing the sacrificial layer through the via hole.

According to the conventional FBAR manufacturing process as described above, in the CMP process for planarization of the substrate including the sacrificial layer, there is a discontinuity of the material properties such as strength on the polished surface due to the difference between the material of the sacrificial layer and the substrate, the surface off phenomenon ( Dishing, boundary protrusion, etc. occur. 2A, 2B, and 2C are enlarged photographs of the boundary between the sacrificial layer and the substrate, and show such phenomenon.

In order to solve this problem, it may be considered that the mechanical strength of the sacrificial layer is the same as that of the substrate by a high temperature annealing process, but in this case, the chemical etching characteristics of the substrate and the sacrificial layer are the same, and thus the sacrificial layer is removed in the process of removing the sacrificial layer. It becomes impossible to selectively remove only the layer, making the device impossible.

In addition, in order to form a piezoelectric layer having good performance, it is necessary to grow the piezoelectric layer by a method such as CVD or MBE at a high temperature of 800 ° C. or higher. In this case, the sacrificial layer is denatured by heat and sacrificial in the process of removing the sacrificial layer. It becomes impossible to selectively remove only the layer, making the device impossible. Therefore, there is a limitation in improving the performance of the piezoelectric layer since the method of growing the piezoelectric layer and a subsequent method using only a low temperature below 500 ° C. can be used.

As described above, the conventional FBAR manufacturing method of forming a cavity through the sacrificial layer has a problem of surface off phenomenon, piezoelectric layer growth method, and the like, which lowers the crystallinity of the piezoelectric layer, thereby lowering the resonator or filter.

The technical problem to be achieved by the present invention is to provide a FBAR manufacturing method that can eliminate the surface off phenomenon caused by the formation of a cavity through the sacrificial layer, the constraints of the piezoelectric layer growth method, etc. at once and further improve the productivity.

The FBAR manufacturing method according to the present invention for solving the above technical problem, forming a cavity on one surface of the first substrate; Forming a piezoelectric layer on one surface of the second substrate; Forming a first electrode on the piezoelectric layer; Arranging one surface of the first substrate and one surface of the second substrate to bond one surface of the first substrate to the first electrode; Removing the second substrate to expose the piezoelectric layer; And forming a second electrode on the exposed surface of the piezoelectric layer.

The bonding may use a wafer bonding technique.

In the bonding step, a bonding metal may be used.

The bonding step may use an epoxy adhesive.

In the bonding step, direct bonding may be used.

In the bonding step, anodizing bonding may be used.

The removing of the second substrate may be performed by mechanical polishing until the second substrate remains a predetermined thickness and then by chemical polishing until the piezoelectric layer is exposed.

The FBAR manufacturing method may include forming a protective layer on the first electrode and the second electrode to expose a portion of the first electrode and the second electrode; And forming metal pads on exposed portions of the first electrode and the second electrode, respectively.

The piezoelectric layer may be formed by using a CVD, MOCVD, or MBE method.

According to the present invention, since the FBAR is manufactured without the process of forming the sacrificial layer, the surface off phenomenon caused by the sacrificial layer, the limitation of the piezoelectric layer growth method, etc. can be eliminated at once, and the process of forming the sacrificial layer and etching Since the process of removing the sacrificial layer is omitted, productivity is improved.

1 shows the structure of a typical FBAR.
2A shows the appearance of surface off phenomenon.
Figure 2b shows the appearance of the boundary protrusion (Protrusion).
Figure 2c shows the appearance of the surface off (Dishing) and the boundary protrusion (Protrusion) together.
3A shows a first substrate 100 '.
3B shows the first substrate 100 on which the cavities 100a are formed.
3C illustrates a state in which the first bonding metal 130 is formed on one surface of the first substrate 100 on which the cavity 100a is formed.
4A shows a second substrate 200.
4B illustrates a state in which a piezoelectric layer 210 ′ is formed on one surface of the second substrate 200.
4C illustrates the first electrode 220 ′ formed on the piezoelectric layer 210 ′.
4D illustrates a state in which the second bonding metal 230 is formed on the first electrode 220 ′.
FIG. 5 shows the structure of FIG. 3C and the structure of FIG. 4D bonded together.
6A illustrates a state in which the second substrate 200 is removed from the structure of FIG. 5.
6B shows the piezoelectric layer 210 patterned.
FIG. 6C illustrates a pattern in which the first electrode 220 is patterned.
6D illustrates a state in which the insulating film 240 is formed.
6E illustrates a state in which the second electrode 250 ′ is formed.
FIG. 6F illustrates the patterning of the second electrode 250.
6G shows a state in which the protective layer 260 'is formed.
6H shows the protective layer 260 patterned.
7 shows the appearance of the completed FBAR by forming the metal pads 270_1 and 270_2.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the accompanying drawings, the substantially identical components are represented by the same reference numerals, and thus redundant description will be omitted. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3A to 3C, 4A to 4D, 5, 6A to 6H, and 7 are cross-sectional views illustrating a method of manufacturing FBAR according to an embodiment of the present invention. 7 is a cross-sectional view of the FBAR completed through the FBAR manufacturing method according to an embodiment of the present invention.

Referring to FIG. 3A, a first substrate 100 ′ is prepared. As the first substrate 100 ′, silicon (Si), high resistance silicon (HRS), gallium arsenide (Ge-As), glass, ceramic, or the like may be used. An insulating layer may be formed on one surface of the first substrate 100 ′ using Low Temperature Oxide (LTO), silicon oxide, silicon nitride (SiXNY), or the like. However, in some embodiments, an insulating film may not be formed.

Referring to FIG. 3B, the cavity 100a is formed on one surface of the first substrate 100 ′. The cavity 100a may be formed, for example, via anisotropic etching.

Referring to FIG. 3C, a first bonding metal 130 is formed on one surface of the first substrate 100 on which the cavity 100a is formed.

Referring to FIG. 4A, a second substrate 200 is prepared. As the second substrate 200, silicon (Si), high resistance silicon (HRS), gallium arsenide (Ge-As), glass, ceramics, or the like may be used.

Referring to FIG. 4B, the piezoelectric layer 210 ′ is formed on one surface of the second substrate 200. The piezoelectric layer 210 'may be formed by depositing aluminum nitride (AIN) or zinc oxide (ZnO). Since there is no sacrificial layer, high temperature methods such as chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), and molecular beam epitaxy (MBE) may be used to maximize the crystallinity of the piezoelectric layer 210 '.

Referring to FIG. 4C, the first electrode 220 ′ is deposited on the piezoelectric layer 210 ′. The first electrode 220 'includes aluminum (Al), tungsten (W), gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), chromium (Cr), palladium (Pd), and molybdenum (Mo) or the like can be used.

Referring to FIG. 4D, a second bonding metal 230 is formed on a portion of the first electrode 220 ′ corresponding to the first bonding metal 130 (see FIG. 3C) of the first substrate 100. do.

Referring to FIG. 5, one surface of the first substrate 100 ′ on which the cavity 100a and the first bonding metal 130 are formed, the piezoelectric layer 210 ′, the first electrode 220 ′, and the second bonding metal One surface of the first substrate 100 and the first electrode are disposed by bonding the first bonding metal 130 and the second bonding metal 230 to each other so as to face one surface of the second substrate 200 on which the 230 is formed. Join (220 ').

In the above-described embodiment of the present invention, the bonding of the structure of FIG. 3C and the structure of FIG. 4D by the wafer bonding technique using the bonding metal may be used, but other wafer bonding techniques may be used depending on the embodiment. For example, an adhesive such as epoxy may be used instead of the bonding metal. Alternatively, the structure of FIG. 3B and the structure of FIG. 4C may be directly bonded without using a bonding metal or an adhesive. For example, direct bonding (bonding by applying a temperature) or anode bonding (bonding) by applying a voltage may be used. In this case, in FIG. 5, the substrate 100 and the first electrode 220 ′ may be directly bonded without the first bonding metal 130 and the second bonding metal 230.

Referring to FIG. 6A, the second substrate 200 is removed to expose the piezoelectric layer 210 ′ in the structure of FIG. 5. The second substrate 200 may be removed through mechanical polishing and chemical polishing. For example, mechanical grinding or polishing is performed until the thickness of the second substrate 200 remains at a predetermined thickness, for example, 50 to 150 µm, and then the gas is removed until the piezoelectric layer 210 'is exposed. It may be removed by using dry etching or wet etching with acid.

Referring to FIG. 6B, a portion of the piezoelectric layer 210 ′ is patterned through etching to form the patterned piezoelectric layer 210.

Referring to FIG. 6C, a portion of the first electrode 220 ′ is patterned through etching to form the patterned first electrode 220.

Referring to FIG. 6D, an insulating layer 240 is formed on the exposed portion of the second bonding metal 230 and the portion of the piezoelectric layer 210.

Referring to FIG. 6E, a second electrode 250 ′ is deposited on the insulating layer 240, the exposed surface of the piezoelectric layer 210, and the first electrode 220. Like the first electrode 220, the second electrode 250 ′ also has aluminum (Al), tungsten (W), gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), and chromium (Cr). , Palladium (Pd), molybdenum (Mo) and the like can be used.

Referring to FIG. 6F, a portion of the second electrode 250 ′ is patterned through etching to form the patterned second electrode 250.

Referring to FIG. 6G, a protective layer 260 ′ is formed on the second electrode 250, the piezoelectric layer 210, and the first electrode 220.

Referring to FIG. 6H, the protective layer 260 ′ is patterned through etching so that a portion of the first electrode 220 and a portion of the second electrode 250 are exposed to form a patterned protective layer 260.

Referring to FIG. 7, metal pads 270_1 and 270_2 are formed in the exposed portion of the first electrode 220 and the exposed portion of the second electrode 250 to connect the signal lines of the external circuit device.

According to the embodiment of the present invention, since the FBAR is manufactured without the process of forming the sacrificial layer, the surface off phenomenon caused by the sacrificial layer, the limitation of the piezoelectric layer growth method, and the like can be eliminated at once. Therefore, it is possible to improve the performance of the FBAR by improving the crystallinity of the piezoelectric layer.

In addition, according to the exemplary embodiment of the present invention, the process of forming the sacrificial layer and the process of removing the sacrificial layer through etching are omitted, and the process of manufacturing a passage of an etching material such as a via hole for removing the sacrificial layer is also omitted, thereby improving productivity. do. In addition, conventionally, foreign matter may be introduced through the via hole, or the piezoelectric layer and the bottom portion of the cavity may be adsorbed. However, in the embodiment of the present invention, the cavity is completely sealed, so there is no fear of such a problem.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

Claims (9)

Forming a cavity in one surface of the first substrate;
Forming a piezoelectric layer on one surface of the second substrate;
Forming a first electrode on the piezoelectric layer;
Arranging one surface of the first substrate and one surface of the second substrate to bond one surface of the first substrate to the first electrode;
Removing the second substrate to expose the piezoelectric layer; And
Forming a second electrode on the exposed side of the piezoelectric layer. The method of claim 1,
The bonding step, FBAR manufacturing method using a wafer bonding technique. The method of claim 2,
The bonding step, FBAR manufacturing method using a bonding metal. The method of claim 2,
The bonding step, FBAR manufacturing method using an epoxy adhesive. The method of claim 2,
The bonding step, FBAR manufacturing method using direct bonding (direct bonding). The method of claim 2,
The bonding step, FBAR manufacturing method using anodizing bonding (anodic bonding). The method of claim 1,
The removing of the second substrate may include removing the second substrate by mechanical polishing until the predetermined thickness remains, and then removing the second substrate by chemical polishing until the piezoelectric layer is exposed. The method of claim 1,
Forming a protective layer on the first electrode and the second electrode to expose a portion of the first electrode and the second electrode; And
And forming metal pads on exposed portions of the first electrode and the second electrode, respectively. The method of claim 1,
Forming the piezoelectric layer, FBAR manufacturing method using a CVD, MOCVD, or MBE method.

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