KR102005571B1 - Solar cell and method for manufacturing the same - Google Patents

Abstract

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A control passivation film formed on one surface of the semiconductor substrate, the control passivation film comprising an amorphous structure and composed of a dielectric material; A semiconductor layer formed on the control passivation film and including a first conductive type region having a first conductivity type and a second conductive type region having a second conductive type opposite to the first conductive type; And an electrode including a first electrode connected to the first conductive type region and a second electrode connected to the second conductive type region. A first diffusion region formed adjacent to the control passivation film at a portion corresponding to the first conductivity type region in the semiconductor substrate and having a doping concentration lower than that of the first conductivity type region, And a second diffusion region formed adjacent to the control passivation film at a portion where the control passivation film is formed.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a manufacturing method thereof, and more particularly, to a solar cell capable of improving efficiency and a manufacturing method thereof.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. The solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize solar cells, it is required to overcome low efficiency, and various layers and electrodes are required to be designed and manufactured so as to maximize the efficiency of the solar cell.

For example, in order to increase the light receiving area, the carrier formed by the photoelectric conversion in the rear electrode type solar cell whose front surface is located on the rear surface may be difficult to move to the conductive type region. This has been a problem when the conductive region is formed as a separate layer from the semiconductor substrate and can be further enhanced by a discontinuous energy band diagram, especially where another layer is located between the conductive region and the semiconductor substrate. As a result, even though the area of the light receiving area is enlarged in the back electrode type solar cell, there is a problem in that the efficiency improvement effect is not large.

The present invention provides a solar cell having excellent efficiency and a manufacturing method thereof.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A control passivation film formed on one surface of the semiconductor substrate, the control passivation film comprising an amorphous structure and composed of a dielectric material; A semiconductor layer formed on the control passivation film and including a first conductive type region having a first conductivity type and a second conductive type region having a second conductive type opposite to the first conductive type; And an electrode including a first electrode connected to the first conductive type region and a second electrode connected to the second conductive type region. A first diffusion region formed adjacent to the control passivation film at a portion corresponding to the first conductivity type region in the semiconductor substrate and having a doping concentration lower than that of the first conductivity type region, And a second diffusion region formed adjacent to the control passivation film at a portion where the control passivation film is formed.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: forming a control passivation film having an amorphous structure on one surface of a semiconductor substrate; Forming a semiconductor layer on the control passivation film, the semiconductor layer including a first conductive type region having a first conductivity type and a second conductive type region having a second conductive type opposite to the first conductive type; And forming an electrode including a first electrode connected to the first conductive type region and a second electrode connected to the second conductive type region. And a second diffusion region formed adjacent to the control passivation film at a portion corresponding to the first conductivity type region and having a doping concentration lower than that of the first conductivity type region, And a second diffusion region formed adjacent to the control passivation film at a portion corresponding to the first passivation film.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: forming a control passivation film on one surface of a semiconductor substrate; Forming a semiconductor layer on the control passivation film; And forming an electrode on the semiconductor layer. In the step of forming the control passivation film, the control passivation film is formed by a thermal oxidation process at a normal pressure and a temperature of 600 캜 to 800 캜.

According to this embodiment, the conductive type region is formed on the semiconductor substrate with the control passivation film interposed therebetween, so that the loss due to the recombination can be minimized. At this time, the control passivation film has an amorphous structure, and the diffusion region can be easily formed in the semiconductor substrate corresponding to the conductive type region. The open area and the density of the solar cell can be improved by the diffusion region, thereby improving the efficiency of the solar cell.

Also, the semiconductor layer or the conductive region includes a polycrystalline portion having a small grain size, so that even when a high-temperature heat treatment or the like is performed, the crystallinity is less changed and the passivation property can be maintained excellent. Thus, the open-circuit voltage of the solar cell can be improved and the efficiency of the solar cell can be greatly improved.

1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.
2 is a partial rear plan view of the solar cell shown in Fig.
FIG. 3 (a) is an energy band diagram of the solar cell according to the present embodiment, and FIG. 3 (b) is an energy band diagram of the solar cell having no diffusion region.
4 is a graph showing a doped profile of a conductive type region, a control passivation film and a diffusion region in the solar cell shown in Fig.
5A to 5F are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a solar cell according to another embodiment of the present invention.
7 is a plan view of the solar cell shown in Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a solar cell and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG.

1 and 2, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10 and a dopant control passivation film (hereinafter referred to as " A semiconductor layer 30 or conductive type regions 32 and 34 located on the control passivation film 20 and a semiconductor layer 30 or conductive type regions 32 and 34 located on the control passivation film 20 And electrodes 42 and 44 electrically connected to each other. The conductive regions 32 and 34 include a first conductive type region 32 having a first conductivity type and a second conductive type region 34 having a second conductive type. Includes a first electrode 42 electrically connected to the first conductive type region 32 and a second electrode 44 electrically connected to the second conductive type region 34. The solar cell 100 further includes a front passivation film 24 and an antireflection film 26 located on the front surface of the semiconductor substrate 10 and a semiconductor layer 30 on the semiconductor layer 30 including the conductive regions 32 and 34 A rear passivation film 40, and the like. This will be explained in more detail.

The semiconductor substrate 10 may include a base region 110 having a first or second conductivity type including a first or a second conductivity type dopant at a relatively low doping concentration. As an example, the base region 110 may have a second conductivity type. The base region 110 may be comprised of a crystalline semiconductor (e.g., a single crystal or polycrystalline semiconductor, e.g., single crystal or polycrystalline silicon, particularly monocrystalline silicon) comprising a first or second conductivity type dopant. The base region 110 having a high degree of crystallinity and having few defects or the solar cell 100 based on the semiconductor substrate 10 has excellent electrical characteristics.

In this embodiment, the front electric field area 130 is located on the front side of the semiconductor substrate 10. The front electric field region 130 is a doping region having a doping concentration higher than that of the base region 110 with a first or second conductivity type (for example, a second conductivity type) which is the same as the base region 110, (10).

An anti-reflection structure capable of minimizing reflection can be formed on the front surface of the semiconductor substrate 10. For example, a texturing structure having a concavo-convex shape in the form of a pyramid or the like may be provided as an antireflection structure. The texturing structure formed in the semiconductor substrate 10 may have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane (e.g., (111) plane) of the semiconductor. When the surface roughness of the semiconductor substrate 10 is increased by the irregularities formed on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced to minimize the optical loss.

The rear surface of the semiconductor substrate 10 may be made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like. When the first and second conductivity type regions 32 and 34 are formed together on the rear side of the semiconductor substrate 10 as in the present embodiment, the characteristics of the solar cell 100 This can vary greatly. As a result, unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that passivation characteristics can be improved and the characteristics of the solar cell 100 can be improved. However, the irregularities due to texturing may be formed on the rear surface of the semiconductor substrate 10 as the case may be. Various other variations are possible.

A control passivation film 20 may be formed on the rear surface of the semiconductor substrate 10. For example, the control passivation film 20 may be formed entirely in contact with the rear surface of the semiconductor substrate 10. Then, the control passivation film 20 can be easily formed without patterning, the structure can be simplified, and the carrier can be stably moved.

The control passivation film 20 located between the semiconductor substrate 10 and the conductive regions 32 and 34 serves as a dopant control function to prevent the dopants of the conductive regions 32 and 34 from diffusing too much into the semiconductor substrate 10. [ Or as a diffusion barrier. The control passivation film 20 may include various materials capable of controlling the diffusion of the dopant and capable of transporting a plurality of carriers. For example, the control passivation film 20 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like.

In this embodiment, the growth rate of at least one of the semiconductor layer 30 and the first and second conductivity type regions 32 and 34 is set to a certain level or less so as to have specific crystal characteristics. This specific crystallization characteristic will be described in more detail later. At this time, the presence of the control passivation film 20 controls the reactivity at the time of forming the semiconductor layer 30 so that at least one of the semiconductor layer 30 or the first and second conductivity type regions 32, Thereby helping to have crystal properties. That is, when the semiconductor layer 30 is formed in direct contact with the semiconductor substrate 10 without the control passivation film 20, since the material for forming the semiconductor layer 30 has high reactivity with the semiconductor substrate 10, The growth rate of the layer 30 becomes large and it may be difficult to control the growth rate to a certain level or less. In this embodiment, the passivation film 20 prevents the semiconductor layer 30 from directly contacting the semiconductor substrate 10, thereby lowering the reactivity, so that the semiconductor layer 30 has low crystallinity or crystallinity.

In one example, the control passivation film 20 may be a dielectric film or an insulating film including a dielectric material having a dielectric constant higher than a certain level to enable movement of the carrier. If the dielectric constant is set to a certain level as described above, polarization may occur when an electric field is applied, so that the carrier can easily move or pass through. The control passivation film 20 may be an oxide film, a dielectric film including silicon, an insulating film, a nitrided oxide film, a carbonized oxide film, or the like. For example, the control passivation film 20 may be formed of a metal oxide film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a metal nitride oxide film, a silicon carbide oxide film, or the like. At this time, the metal included in the metal oxide film or the metal nitride oxide film may be aluminum, titanium, hafnium, or the like. When the metal is included, the control passivation film 20 may be formed of an aluminum oxide film, a titanium oxide film, a hafnium oxide film, an aluminum nitride oxide film, a titanium nitride oxide film, a hafnium nitride oxide film, or the like.

In one example, the control passivation film 20 may be a silicon oxide film containing silicon oxide. This is because the silicon oxide film has excellent passivation characteristics and is a smooth film of the carrier. In addition, the silicon oxide film can be easily formed on the surface of the semiconductor substrate 10 by various processes. At this time, in this embodiment, the control passivation film 20 composed of a silicon oxide film can be formed under specific process conditions, so that the dopant can be smoothly moved through the control passivation film 20. Specific process conditions for this will be described in more detail later. Thus, the formula of the silicon oxide film formed under the specific process conditions is SiOx and x can be 1.1 or more (1.1 to 2.0). The refractive index of the silicon oxide film constituting the control passivation film 20 may be 1.5 or more (for example, 1.5 to 1.7). At this time, the refractive index of the control passivation film 20 made of a silicon oxide film is set to a refractive index (for example, 1.4 or more) of the other insulating film (the antireflection film 26 or the front and rear passivation films 24 and 40) , Less than 1.5). However, the present invention is not limited thereto, and the silicon oxide film used as the control passivation film 20 may have various chemical formulas or refractive indices.

At this time, the control passivation film 20 may have an amorphous structure. More specifically, the control passivation film 20 may be an amorphous film consisting of only an amorphous structure or an amorphous film including a partially crystallized portion.

The control passivation film 20 having such an amorphous structure can contribute to forming the diffusion portions 320 and 340 located inside the semiconductor substrate 10. More specifically, when the control passivation film 20 has an amorphous structure, the first or second conductivity type dopant included in the conductive type regions 32 and 34 can easily pass through the control passivation film 20. [ The first or second conductive type dopant included in the conductive type regions 32 and 34 is diffused into the semiconductor substrate 10 through the control passivation film 20 and diffused into the semiconductor substrate 10 Regions 320 and 340 can be easily formed. The control passivation layer 20 may include a first doped portion 202 and / or a second doped portion (not shown) including a first or a second conductive dopant included in the first or second conductivity type regions 32 and 34 204). The first doped portion 202 and the second doped portion 204 have a higher doping concentration than the other insulating films (the antireflection film 26, the front and rear passivation films 24 and 40) . The diffusion regions 320 and 340 and the doped portions 202 and 204 will be described in more detail later.

At this time, as described above, the first and / or second doped portions 202 and 204 and the diffusion regions 320 and 340 can be formed more easily by forming the control passivation film 20 under specific process conditions. These process conditions will be described in more detail later.

In addition, when the control passivation film 20 has an amorphous structure, the crystallinity of the semiconductor layer 30 formed on the control passivation film 20 may be lowered so that the semiconductor layer 30 has desired crystallization characteristics.

The control passivation film 20 having an amorphous structure may have a small thickness for carrier movement through the control passivation film 20, diffusion control of the dopant, and the like. The thickness of the control passivation film 20 may be smaller than the thickness of the other insulating film (the antireflection film 26, the front and rear passivation films 24 and 40, and particularly, the insulating film including the oxide film). For example, the thickness of the control passivation film 20 may be 5 nm or less (more specifically, 2 nm or less, for example, 0.5 to 2 nm). If the thickness of the control passivation film 20 is more than 5 nm, the carrier may not move and the solar cell 100 may not operate. If the thickness of the control passivation film 20 is less than 0.5 nm, a control passivation film 20 may be difficult to form. The control passivation film 20 may have a thickness of 2 nm or less (more specifically, 0.5 nm to 2 nm) in order to facilitate carrier movement and dopant diffusion. At this time, the control passivation film 20 may have a thickness of 0.5 nm to 1.5 nm so as to make carrier migration and dopant diffusion more smooth. However, the present invention is not limited thereto, and the thickness of the control passivation film 20 may have various values.

On the control passivation film 20, the semiconductor layer 30 including the conductive regions 32 and 34 may be located. In this embodiment, the first and second conductivity type regions 32 and 34 are formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically on the control passivation film 20) 1 or a semiconductor layer 30 doped with a second conductive dopant. In one example, the semiconductor layer 30 (or the conductive regions 32 and 34) may be formed in contact with the control passivation film 20 to simplify the structure and allow the carrier to be easily transferred.

Since the semiconductor layer 30 is formed by a process different from that of the semiconductor substrate 10 in the present embodiment, the semiconductor layer 30 has a different crystal structure or crystallinity from the semiconductor substrate 10. In one example, the semiconductor layer 30 may include a polycrystalline portion 302 having a polycrystalline structure having a relatively small grain size, which may be formed in the semiconductor layer 30 ). At this time, if the control passivation film 20 has an amorphous structure as described above, the crystallinity of the semiconductor layer 30 can be controlled. The method of manufacturing the semiconductor layer 30 will be described later in more detail.

More specifically, the semiconductor layer 30 may include a polycrystalline portion 302 having a polycrystalline structure having a grain size (for example, an average grain size) of nanometer level (1 nm or more and less than 1um). At this time, the grain size can be measured or evaluated by a transmission electron microscope (TEM). For example, the semiconductor layer 30 may be formed of a polycrystalline semiconductor layer having a grain size of 300 nm or less (for example, 1 nm to 300 nm). Alternatively, the semiconductor layer 30 may have a grain size equal to or less than the thickness of the semiconductor layer 30. When the grain size of the semiconductor layer 30 is 300 nm or less or the thickness of the semiconductor layer 30 is less than the thickness of the semiconductor layer 30, the effect of the polycrystalline portion 302 can be greatly increased. For reference, the thickness of the semiconductor layer 30 may be 100 nm to 500 nm (e.g., 150 nm to 500 nm). The processing time can be minimized while sufficiently performing the role of the semiconductor layer 30 in such a thickness range. However, the present invention is not limited thereto.

The change in crystallinity of the semiconductor layer 30 is minimized even in the presence of a temperature change in the semiconductor layer 30 including the polycrystalline portion 302 having a relatively small crystal grain size. In manufacturing the solar cell 100, a high-temperature heat treatment process for passivation using hydrogen is performed immediately before or after the formation of the electrodes 42 and 44 in order to improve the passivation property. The crystallinity of the semiconductor layer 30 A large number of deep trap sites (for example, (111) surface) may be formed during the high-temperature heat treatment process if the crystal grain size is large (i.e., the crystal grain size is large). Hydrogen penetrates through the trap site, but when it gets caught in the dip trap site it does not exit the dip trap site and remains at the dip trap site. As a result, hydrogen is not sufficiently penetrated, and hydrogen passivation can not be sufficiently realized. Taking this into consideration, in this embodiment, the grain size of the semiconductor layer 30 is reduced to minimize the formation of deep trap sites, so that hydrogen permeation can be smoothly performed, thereby maximizing the hydrogen passivation effect.

Accordingly, even if the high-temperature heat treatment process is performed after the semiconductor layer 30 is formed, the semiconductor layer 30 may exhibit excellent passivation characteristics. Therefore, the solar cell 100 can have a high implied Voc regardless of whether or not the high temperature heat treatment process is performed.

On the other hand, when the grain size of the semiconductor layer 30 is on the micrometer level (that is, 1um or more), the deep trap site can be easily generated and the hydrogen permeation can be inhibited.

In this embodiment, the semiconductor layer 30 includes the above-described polycrystalline portion 302, and may further include an amorphous portion 304 having an amorphous structure. By including the polycrystalline portion 302 having a relatively small grain size and including the amorphous portion 304 as described above, it is possible to further enhance the effect due to the small grain size or low crystallinity described above. For example, the polycrystalline portion 302 and the amorphous portion 304 of the semiconductor layer 30 can be determined by a transmission electron microscope, an X-ray rotational analyzer (XRD), a Raman spectroscopy method, or the like.

More specifically, the semiconductor layer 30 may not include the amorphous portion 304 or may include more polycrystalline portion 302 than the amorphous portion 304. This is because the proportion of the amorphous portion 304 in the final structure of the semiconductor layer 30 may be made smaller by the additional heat treatment (for example, laser irradiation during laser doping) of the semiconductor layer 30 during the doping process. In one example, the polycrystalline portion 302 in the semiconductor layer 30 may be 60 to 100 vol% and the amorphous portion 304 may be 0 to 40 vol%. However, the present invention is not limited thereto.

In this embodiment, the semiconductor layer 30 includes a first conductivity type region 32 having a first conductivity type dopant and exhibiting a first conductivity type, a second conductivity type region 32 having a second conductivity type dopant and exhibiting a second conductivity type, Type region 34. [0040] At this time, the regions having the same conductivity type as the first and second conductivity type regions 32 and 34 and the base region 110 (for example, the second conductivity type region 34) Concentration. The first conductive type region 32 and the second conductive type region 34 may be located coplanarly within the semiconductor layer 30 formed continuously over the control passivation film 20. [ And a barrier region 36 may be positioned between the first conductivity type region 32 and the second conductivity type region 34 on the same plane.

One of the first and second conductivity type regions 32 and 34, which has a conductivity type different from that of the base region 110, constitutes at least a part of the emitter region. The emitter region forms a pn junction (or pn tunnel junction) with the base region 110 to generate carriers by photoelectric conversion. The other of the first and second conductivity type regions 34 and 34 having the same conductivity type as the base region 110 constitutes at least a part of a back surface field region. The rear electric field area forms a back electric field which prevents carriers from being lost by recombination at the rear surface of the semiconductor substrate 10. [

The first or second conductivity type dopant included in the semiconductor layer 30 may be included together in the semiconductor layer 30 in the process of forming the semiconductor layer 30 or may be included in the semiconductor layer 30 after forming the semiconductor layer 30, , An ion implantation method, or the like, may be included in the semiconductor layer 30. As the first or second conductivity type dopant, various materials which can be doped to the semiconductor layer 30 to exhibit n-type or p-type conductivity may be used. When the first or second conductivity type dopant is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. When the first or second conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used. In one example, one of the first and second conductivity type dopants may be boron (B) and the other may be phosphorus (P).

A barrier region 36 is positioned between the first conductive type region 32 and the second conductive type region 34 to separate the first conductive type region 32 and the second conductive type region 34 from each other. When the first conductive type region 32 and the second conductive type region 34 are in contact with each other, a shunt may be generated to deteriorate the performance of the solar cell 100. Accordingly, in this embodiment, unnecessary shunt can be prevented by positioning the barrier region 36 between the first conductive type region 32 and the second conductive type region 34.

An undoped (i.e., unshown) insulating material (e.g., oxide, nitride) or the like may be used as the barrier region 36. Alternatively, the barrier region 36 may comprise an intrinsic semiconductor. At this time, the first conductive type region 32, the second conductive type region 34, and the barrier region 36 are formed of the same semiconductor (for example, a semiconductor including a polycrystalline portion 302) Layer 30), the barrier region 36 may be an i-type (intrinsic) semiconductor material substantially free of dopants. For example, after the intrinsic semiconductor layer is formed, a first conductive type dopant is doped in a portion of the intrinsic semiconductor layer to form a first conductive type region 32, and a second conductive type dopant is doped in a portion of the other region When the second conductivity type region 34 is formed, a region where the first conductivity type region 32 and the second conductivity type region 34 are not formed may constitute the barrier region 36. [ This makes it possible to simplify the manufacturing method of the first conductivity type region 32, the second conductivity type region 34, and the barrier region 36.

However, the present invention is not limited thereto. Thus, the barrier region 36 may be formed by various methods to have various thicknesses and may have various shapes. The barrier region 36 may be a trench which is an empty space. Various other variations are possible. In the drawing, the barrier region 36 is entirely separated from the first conductivity type region 32 and the second conductivity type region 34. However, the barrier region 36 may be formed to separate only a part of the boundary portions of the first conductive type region 32 and the second conductive type region 34. Alternatively, since the barrier region 36 is not formed, the boundaries of the first conductive type region 32 and the second conductive type region 34 may be in contact with each other.

In the above description, it is exemplified that the first and second conductivity type regions 32 and 34 or the semiconductor layer 30 constituting the first and second conductivity type regions 32 and 34 may include the polycrystalline portion 302 and further include the amorphous portion 304 . However, the present invention is not limited thereto. Therefore, the first and second conductivity type regions 32 and 34 or the semiconductor layer 30 may have a crystal structure different from that of the semiconductor substrate 10 so that they can be easily formed on the semiconductor substrate 10. For example, the first and second conductivity type regions 32 and 34 may be amorphous semiconductors, microcrystalline semiconductors, or polycrystalline semiconductors (e.g., amorphous silicon, microcrystalline silicon , Or polycrystalline silicon) or the like may be formed by doping with a first or second conductivity type dopant. In particular, if the first and second conductivity type regions 32 and 34 have a polycrystalline semiconductor, they can have a high carrier mobility.

At this time, diffusion regions 320 and 340 may be formed in the semiconductor substrate 10 in this embodiment. The diffusion regions 320 and 340 constitute a part of the semiconductor substrate 10 and have the same crystal structure as that of the base region 110. The conductivity type or the doping concentration may be different from that of the base region 110.

The diffusion regions 320 and 340 may include one of the first diffusion region 320 and the second diffusion region 340 or may include a first diffusion region 320 and a second diffusion region 340, have. Here, the first diffusion region 320 is formed in a region of the semiconductor substrate 10 that is partially adjacent to the control passivation film 20 at a position corresponding to the first conductive type region 32, The doping concentration may be lower than the first conductivity type region 32. And the second diffusion region 340 is formed in a region of the semiconductor substrate 10 that is partially adjacent to the control passivation film 20 at a location corresponding to the second conductive type region 34, The concentration may be lower than the second conductivity type region 32. [ A region of the first and second diffusion regions 320 and 340 having the same conductivity type as the base region 110 (for example, the second diffusion region 340) has a higher doping concentration than the base region 110 Lt; / RTI > Hereinafter, the base region 110 has a second conductivity type for convenience. Since the first and second conductivity type regions 32 and 34 are located on the rear side in the solar cell 100 having the rear electrode structure as described above, the diffusion regions 320 and 340 are formed on the rear surface of the semiconductor substrate 10 as a whole Once formed, the diffusion regions 320 and 340 can prevent the movement of the necessary carriers. For example, if the first diffusion region 320 is formed as a whole, the first diffusion region 320 interferes with the flow of carriers from the portion adjacent to the second conductivity type region 34 toward the second conductivity type region 34 do. Alternatively, if the second diffusion region 340 is formed in its entirety, the second diffusion region 340 interferes with the flow of carriers from the portion adjacent to the first conductivity type region 32 toward the first conductivity type region 32. In particular, the diffusion regions 320 and 340 may be spaced apart from each other to define a base region 110 spaced between the diffusion regions 320 and 340, thereby reducing the doping region in the semiconductor substrate 10 The characteristics of the semiconductor substrate 10 and the like can be minimized.

Since the first and second diffusion regions 32 and 34 have shapes corresponding to the first and second conductivity type regions 32 and 34, the first diffusion region 32 and the second diffusion region 34 They can be located alternately.

In the present embodiment, the diffusion regions 320 and 340 are formed in the first or second conductivity type regions 32 and 34, the control passivation film 20, and the semiconductor substrate 10, And serves to deform the energy band so that the majority carriers of the regions 32 and 34 can easily pass through. As a result, the open-circuit voltage and the filling density can be improved. In particular, the filling density can be greatly improved. This will be described in more detail with reference to FIG.

3 (a) is an energy band diagram of the solar cell 100 according to the present embodiment, and FIG. 3 (b) is an energy band diagram of the solar cell having no diffusion regions 320 and 340. FIG. In FIG. 3, for example, the base region 110 has an n-type, and the first diffusion region 320 and the first conductivity type region 32 have a p-type. The doping concentration of the first diffusion region 320 is less than the doping concentration of the first conductivity type region 32.

3 (a), the first diffusion region 320 is formed in such a manner that the conduction band and the electrical conductivity band are gradually shifted toward the first conductivity type region 32, the control passivation film 22 and the base region 10 And modifies the energy band to decrease continuously. In the case of the energy band diagram, the electrons e located in the conduction band have an energy band gap Ec between the base region 10 and the first conductivity type region 32, The energy band gap? Ev between the base region 10 and the first conductivity type region 32 is present in the holes located in the current conduction band, And is easily moved to the first conductivity type region 32. On the other hand, in the absence of the first diffusion region 320, as shown in FIG. 3 (b), the conduction band and the electrical conductivity band are discontinuously positioned with respect to the control passivation film 22, It is possible to prevent movement in the direction. In other words, a discontinuous conduction band and an electrical conductivity band in the vicinity of the control passivation film 22 serve as an energy barrier preventing the desired carrier from moving to the conductive type regions 32 and 34. As described above, the diffusion regions 320 and 340 in the present embodiment are formed by modifying the energy band that allows a desired carrier to easily move into the first and second conductivity type regions 32 and 34, And filling density can be improved.

The control passivation layer 20 may include a first doped portion 202 and a second doped portion 202 that are located between the first conductive region 32 and the first diffusion region 320 and include a first conductive dopant, And a second doped portion 204 located between the region 34 and the second diffusion region 340 and including a second conductive dopant. That is, in the control passivation film 20, the first and second doped portions 202 and 204 may be partially formed to correspond to the first and second conductivity type regions 32 and 34, respectively. In this embodiment, the control passivation film 20 corresponds to the barrier region 36 and the first and second doped portions 202 and 204 are spaced apart from each other with the undoped undoped portion 206 therebetween And can be positioned alternately with each other. However, the present invention is not limited thereto. At this time, the first and second doped portions 202 and 204 may be partially doped to form heavily doped portions 202a and 204a having higher concentrations than other portions. These heavily doped portions 202a and 204a may be portions where the dopant is formed by remaining in a cohesive state at a portion of the control passivation film 20. [ The highly doped portions 202a and 204a may be irregularly positioned with various random shapes.

The first and second doped portions 202 and 204 of the control passivation film 20 are electrically connected to other undoped insulating films (the antireflection film 26, the front and back passivation films 24 and 40, The doping concentration of the first or second conductivity type dopant is higher than that of the first or second conductivity type dopant).

The diffusion regions 320 and 340 may be formed in such a manner that the control passivation film 20 has an amorphous structure so that the first or second conductivity type dopant of the conductive regions 32 and 34 can easily form the control passivation film 20 Can be formed by passing. Thereby, a specific doping profile is obtained. This will be described in detail with reference to FIG. 4 together with FIG. 1 and FIG.

4 is a graph showing a doped profile of a conductive type region, a control passivation film and a diffusion region in the solar cell shown in Fig. By way of reference, the doping profiles according to FIG. 4 were measured by secondary ion mass spectrometry (SIMS) (SIMS).

4, the first conductive type region 32, the control passivation film 20 and the first diffusion region 320, and / or the second conductive type region 34, the control passivation film 20, The control passivation film 20 and the first or second diffusion region 32 and 34 have a relatively uniform doping concentration in the first or second conductivity type regions 32 and 34 when the second diffusion region 340 is viewed in the thickness direction. The doping concentration is continuously and gradually reduced in the regions 320 and 340 while being directed to the inside of the semiconductor substrate 10. That is, the first conductivity type region 32 is relatively uniform and has a high surface doping concentration Cs, and passes through the control passivation film 20 and the first diffusion region 320 until the doping concentration becomes zero The doping concentration gradually decreases. And the second conductivity type region 34 is relatively uniform and has a high surface doping concentration Cs and the doping concentration is greater than the doping concentration of the base region 110 after passing through the control passivation film 20 and the second diffusion region 340. [ The doping concentration gradually decreases until it becomes equal to the doping concentration. Although the surface doping concentration Cs of the first conductivity type region 32 and the surface doping concentration Cs of the second conductivity type region 34 are shown to be the same for convenience in FIG. 4, The surface doping concentration Cs of the first conductivity type region 32 and the surface doping concentration Cs of the second conductivity type region 34 may be different from each other. The first and / or second conductivity type dopants of the conductive type regions 32 and 34 are diffused through the control passivation film 20 by the doping profile to form the first and second diffusion regions 320 and 340 .

The difference in doping concentration of the first conductive region 32 in the thickness direction (difference in doping concentration between the portion adjacent to the control passivation film 20 and the opposite portion thereof) (The difference in doping concentration between the portion adjacent to the control passivation film 20 and the portion opposite thereto) is large. Similarly, the difference in doping concentration of the second conductive region 34 in the thickness direction (the difference in doping concentration between the portion adjacent to the control passivation film 20 and the opposite portion thereof) The difference between the doping concentration (the difference in doping concentration between the portion adjacent to the control passivation film 20 and the portion opposite thereto) may be large. The absolute value of the doping concentration gradient (or slope) in the doping profile as viewed in the thickness direction is greater in the first diffusion region 320 than in the first conductivity type region 32 and greater than in the second conductivity type region 34 And may be larger in the second diffusion region 340. This is because the first or second conductivity type dopant is implanted in the first and second conductivity type regions 32 and 34 to form the first or second conductivity type dopant uniformly in the first and second conductivity type regions 32 and 34, And the first and second diffusion regions 320 and 340 are formed by diffusing the first or second conductivity type dopant included in the first and second conductivity type regions 32 and 34.

For example, the doping concentrations of the first and second conductivity type regions 32 and 34 may be 1 × ^{10 19} / cm ^{3 or} more, respectively. Within this range, the effects of the first and second conductivity type regions 32 and 34 can be sufficiently realized and the contact resistance with the first and second electrodes 42 and 44 can be minimized. For example, the doping concentration of the first diffusion region 320 may be less than 1 × ^{10 19} / cm ³ and the doping concentration of the first conductivity type region 32 may be less than the doping concentration of the first diffusion region 320, May be less than 1 × ^{10 19} / cm ^{3 and} less than the doping concentration of the second conductivity type region 34, respectively. However, the present invention is not limited thereto. At this time, each of the first and second conductivity type regions 32 and 34 has a relatively uniform doping concentration in the entire region.

The thicknesses T2 and T3 of the diffusion regions 320 and 340 may be equal to or greater than the thickness T1 of the conductive regions 32 and 34 (or the thickness of the semiconductor layer 30). More specifically, the thickness T2 of the first diffusion region 320 is equal to or greater than the thickness T1 of the first conductive region 32 or the semiconductor layer 30, Is equal to or greater than the thickness T1 of the second conductivity type region 34 or the semiconductor layer 30. Accordingly, the process time for forming the semiconductor layer 30 can be shortened and the effect of the first and second diffusion regions 320 and 340 can be sufficiently realized. However, the present invention is not limited thereto, and the thicknesses T2 and T3 of the diffusion regions 320 and 340 may be smaller than the thickness T1 of the conductive regions 32 and 34 (or the thickness of the semiconductor layer 30) It is possible.

For example, the thicknesses T2 and T3 of the first or second diffusion regions 320 and 340 may be the same as the reference doping concentration Co that is determined to be substantially not doped from the surface of the semiconductor substrate 10 As shown in FIG. For example, when the doping concentrations of the first and second conductivity type regions 32 and 34 and the first and second diffusion regions 320 and 340 are measured by secondary ion mass spectrometry as described above, The concentration (Co) may be 1 x ¹⁰ < ¹⁵ > / cm < ³ >. According to the secondary ion mass spectrometry, even when the dopant is not actually doped, it is considered that the doping concentration is indicated by noise or the like. That is, when the doping concentration is less than 1 × ^{10 15} / cm ³ , even if the doping concentration is indicated, the doping is not actually performed. Therefore, this portion is not considered when determining the thickness of the first or second diffusion region 320 or 340 I will not. However, the present invention is not limited thereto. Accordingly, the doping concentration of the first and second diffusion regions 320 and 340 can be measured by various methods, and the thicknesses of the first and second diffusion regions 320 and 340 can be measured or determined can do.

The absolute value of the doping concentration gradient in the first diffusion region 320 may be smaller than the absolute value of the doping concentration gradient in the second diffusion region 340 in the thickness direction. The thickness T3 of the second diffusion region 340 having the same second conductivity type as that of the base region 110 may be greater than the thickness T2 of the first diffusion region 320 having the first conductivity type. The second diffusion region 340 having the same second conductivity type as the base region 110 may be formed to have a relatively large thickness in the base region 110. Since the first diffusion region 320 has to be doped to have the same first conductivity type as that of the base region 110, the passivation characteristics may be degraded if the first diffusion region 320 is relatively thick. For example, according to the thermal diffusion method in which the second conductive type region 34 and the front electric field region 130 can be formed in the same process in order to simplify the process, the second conductive type dopant is infinite, (340) can easily be formed. If the first conductive type region 32 is formed by laser doping or the like for partial doping, the first conductive type dopant is finite, so that the relatively thin first diffusion region 320 can be easily formed. However, the present invention is not limited thereto, and the thickness of the second diffusion region 340 may be smaller than that of the first diffusion region 320.

Alternatively, the thickness of the first diffusion region 320 may be 500 nm or less (for example, 50 nm to 500 nm) and the thickness of the second diffusion region 340 may be 800 nm or less (50 nm to 800 nm). The effect of the first and second diffusion regions 320 and 340 can be sufficiently realized within such a thickness range. However, the present invention is not limited thereto.

In the drawings and the above description, it is exemplified that both the first diffusion region 320 and the second diffusion region 340 are provided. Alternatively, only one of the first diffusion region 320 and the second diffusion region 340 may be provided. For example, a first diffusion (not shown) corresponding to a conductive type region (for example, the first conductive type region 32) having a conductive type opposite to the semiconductor substrate 10 among the first and second diffusion regions 320 and 340 Only the region 320 is provided and the second diffusion region 340 corresponding to the conductive type region (for example, the second conductive type region 34) having the same conductivity type as that of the semiconductor substrate 10 is not provided have. This is because in the conductive type region in which the carrier by the conductive type dopant included in the semiconductor substrate 10 is used as a majority carrier, carriers are easily transferred through the control passivation film 20 by the electric field formed while the carriers of the semiconductor substrate 10 are piled up It is difficult for the carrier to move easily through the control passivation film 20 in the conductive type region where the opposite carrier is used as the majority carrier. In other embodiments, only the second diffusion region 340 may be provided and the first diffusion region 320 may not be provided. In some embodiments, the first and second diffusion regions 320 and 340 may be omitted.

The rear passivation film 40 may be formed on the first and second conductivity type regions 32 and 34 and the barrier region 36 on the rear surface of the semiconductor substrate 10. [ For example, the rear passivation film 40 may be formed in contact with the first and second conductivity type regions 32 and 34 and the barrier region 36 to simplify the structure.

The rear passivation film 40 has contact holes 46 for electrical connection between the conductive regions 32 and 34 and the electrodes 42 and 42. The contact hole 46 includes a first contact hole 461 for connecting the first conductivity type region 32 and the first electrode 42 and a second contact hole 461 for connecting the second conductivity type region 34 and the second electrode 44, And a second contact hole 462 for connection of the second contact hole 462. As a result, the rear passivation film 40 is formed in the same manner as that of the first conductive type region 32 and the second conductive type region 34 in the case of the electrode to which the first conductive type region 32 and the second conductive type region 34 should not be connected 44 in the case of the second conductivity type region 34 and the first electrode 42 in the case of the second conductivity type region 34). In addition, the back passivation film 40 may have the effect of passivating the first and second conductivity type regions 32, 34 and / or the barrier region 36.

The front passivation film 24 and / or the antireflection film 26 can be positioned on the front surface of the semiconductor substrate 10 (more precisely, on the front electric field area 130 formed on the front surface of the semiconductor substrate 10) have. However, the present invention is not limited thereto, and another insulating layer having a stacked structure may be formed on the front electric field area 130.

The front passivation film 24 and the antireflection film 26 may be formed entirely on the entire surface of the semiconductor substrate 10. [ And the rear passivation film 40 may be formed entirely on the rear surface of the semiconductor layer 30 except for the contact hole 46. [

The front passivation film 24 or the rear passivation film 40 may be formed in contact with the semiconductor substrate 10 or the semiconductor layer 30 to prevent defects present in the front surface or bulk of the semiconductor substrate 10 or the semiconductor layer 30 Immobilized. Thus, the recombination site of the minority carriers can be removed to increase the open-circuit voltage of the solar cell 100. The antireflection film 26 may reduce the reflectivity of light incident on the front surface of the semiconductor substrate 10, thereby increasing the amount of light reaching the pn junction. Accordingly, the short circuit current Isc of the solar cell 100 can be increased.

The front passivation film 24, the antireflection film 26, and the rear passivation film 40 may be formed of various materials. In one example, the front passivation film 24, the anti-reflection film 26 or the passivation film 40 is a silicon nitride film, a silicon nitride film containing hydrogen, silicon oxide, silicon nitride oxide, aluminum oxide film, a silicon carbide film, MgF _2, ZnS, TiO _2, and CeO ₂ , or a multilayer structure in which two or more films are combined.

For example, in the present embodiment, the front passivation film 24 and / or the antireflection film 26 and the rear passivation film 40 may not include a dopant or the like so as to have excellent insulating properties, passivation properties, and the like. However, the present invention is not limited thereto.

The front passivation film 24, the antireflection film 26, and the rear passivation film 40 may have a thickness greater than that of the control passivation film 20. [ As a result, the insulating characteristics and the passivation characteristics can be improved. Various other variations are possible.

The first electrode 42 is formed by filling at least a portion of the first contact hole 461 of the rear passivation film 40 and is electrically connected to the first conductive type region 32 The second electrode 44 is formed by filling at least a portion of the second contact hole 462 of the rear passivation film 40 and electrically connected to the second conductive type region 34 (for example, by contact formation).

1 and 2, the first conductive type region 32 and the second conductive type region 34, the barrier region 36, and the planar shape of the first and second electrodes 42 and 44 Will be described in detail.

1 and 2, in the present embodiment, the first conductive type region 32 and the second conductive type region 34 are formed so as to have a stripe shape and are alternately arranged in a direction intersecting the longitudinal direction, Respectively. Barrier regions 36 may be located between the first conductivity type region 32 and the second conductivity type region 34 to isolate them. Although not shown, a plurality of first conductive regions 32 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductive regions 34 separated from each other may be connected to each other at the other edge. However, the present invention is not limited thereto.

At this time, when the base region 110 has the second conductivity type, the area of the first conductivity type region 32 may be larger than the area of the second conductivity type region 34. For example, if the second conductivity type region 34 and the base region 110 have n-type conductivity, a junction that forms a carrier by photoelectric conversion with the base region 110 (e.g., a control passivation film 20, And the first conductivity type region 32 forming the pn junction formed on the first conductive type region 32 may be widely formed to increase the photoelectric conversion area. Further, in this case, the emitter region having a large area can effectively collect holes having a relatively slow moving speed, thereby contributing more to the improvement of photoelectric conversion efficiency. However, the present invention is not limited thereto.

In one example, the areas of the first conductivity type region 32 and the second conductivity type region 34 can be adjusted by varying their widths. That is, the width W1 of the first conductivity type region 32 may be greater than the width W2 of the second conductivity type region 34. [

The first electrode 42 may be formed in a stripe shape corresponding to the first conductivity type region 32 and the second electrode 44 may be formed in a stripe shape corresponding to the second conductivity type region 34 . The contact hole (reference numeral 46 in FIG. 1, hereinafter the same) is formed so that only a part of the first and second electrodes 42 and 44 are connected to the first conductivity type region 32 and the second conductivity type region 34, respectively . For example, the contact hole 46 may be formed of a plurality of contact holes. Alternatively, the contact holes 46 may be formed in the entire length of the first and second electrodes 42 and 44 corresponding to the first and second electrodes 42 and 44, respectively. The contact area between the first and second electrodes 42 and 44 and the first conductivity type region 32 and the second conductivity type region 34 can be maximized to improve the carrier collection efficiency. Various other variations are possible. Although not shown in the figure, the first electrodes 42 may be connected to each other at one edge, and the second electrodes 44 may be connected to each other at the other edge. However, the present invention is not limited thereto.

When light is incident on the solar cell 100 according to the present embodiment, electrons and holes are generated by the photoelectric conversion at the pn junction formed between the base region 110 and the first conductivity type region 32, And electrons pass through the control passivation film 20 to move to the first and second electrodes 42 and 44 after moving to the first conductivity type region 32 and the second conductivity type region 34, respectively. Thereby generating electrical energy.

In the solar cell 100 having the rear electrode structure in which the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10 and electrodes are not formed on the front surface of the semiconductor substrate 10 as in the present embodiment, The shading loss can be minimized at the front side of the screen. Thus, the efficiency of the solar cell 100 can be improved. However, the present invention is not limited thereto. The solar cell 100 of another structure will be described in detail later with reference to Figs. 6 and 7. Fig.

Since the first and second conductivity type regions 32 and 34 are formed on the semiconductor substrate 10 with the control passivation film 20 interposed therebetween, As a result, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the dopant is used as the conductive type region.

At this time, the control passivation film 20 has an amorphous structure, and diffusion regions 320 and 340 can be easily formed in the semiconductor substrate 10 corresponding to the conductive regions 32 and 34. The efficiency of the solar cell 100 can be improved by improving the open voltage and the filling density of the solar cell 100 by the diffusion regions 320 and 340.

Also, the semiconductor layer 30 or the conductive regions 32 and 34 include the polycrystalline portion 302 having a small grain size, so that even when a high-temperature heat treatment process or the like is performed, the crystallinity is not changed and the passivation property can be maintained excellent. As a result, the open circuit voltage of the solar cell 100 can be improved and the efficiency of the solar cell 100 can be greatly improved.

The above-described control passivation film 20 and the semiconductor layer 30 can be formed under specific conditions and have the above-described characteristics. Hereinafter, a method of manufacturing a control passivation film 20 having a desired characteristic and a specific solar cell 100 for forming the semiconductor layer 30 will be described in detail with reference to FIGS. 5A to 5F.

5A to 5F are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

First, as shown in FIG. 5A, the control passivation film 20 is formed on the rear surface of the semiconductor substrate 10 formed of the base region 110. The control passivation film 20 may be formed entirely in contact with the rear surface of the semiconductor substrate 10. [

In this embodiment, as described above, the control passivation film 20 may have an amorphous structure so that diffusion regions (reference numerals 320 and 340 in FIG. 5D) can be easily formed. The control passivation film 20 having such an amorphous structure can be easily formed by performing a thermal oxidation process at a normal pressure and a process temperature of 600 ° C to 800 ° C. More specifically, the thermal oxidation process is performed by heating from a temperature of 500 ° C or lower to a process temperature of 600 ° C to 800 ° C under normal pressure, and then cooled to a temperature of 500 ° C to 550 ° C to form a control passivation film 20 can be formed. Particularly, in the present embodiment, the control passivation film 20 may not be subjected to a separate heat treatment to densify the control passivation film 20 before the semiconductor layer 30 is formed by the thermal oxidation process described above have. The control passivation film 20 having an amorphous structure as described above can be formed by a simple process.

In the thermal oxidation process described above, the gas atmosphere may contain an oxygen gas (O ₂ ) as a raw material gas and further include a halogen gas. The halogen gas can serve to enhance the purity and quality of the control passivation film 20. [ As the halogen gas, a chlorine gas which can be easily obtained and is relatively stable can be used. As another example, in the thermal oxidation process, the gas atmosphere may include an inert gas or a nitrogen gas to form the control passivation film 20. As an example, it may contain only an inert gas or nitrogen gas. As another example, in the thermal oxidation process, the control passivation film 20 can be formed by decomposing gas containing ozone under atmospheric pressure into ultraviolet rays (UV).

5B to 5D, a first conductive type region 32 and a second conductive type region 34 are formed on the control passivation film 20, and an electric field (not shown) is formed on the entire surface of the semiconductor substrate 10, Regions 130 are formed. The first and second diffusion regions 320 and 340 may be formed in or after the process of forming the first and second conductivity type regions 32 and 34 according to the embodiment. An anti-reflection structure (for example, a texturing structure) may be formed on the entire surface of the semiconductor substrate 10. This will be described in more detail as follows.

The semiconductor layer 30 is formed on the control passivation film 20, as shown in Fig. 5B. At this time, the semiconductor layer 30 may be intrinsic.

As described above, in the present embodiment, the semiconductor layer 30 is a polycrystalline portion having a polycrystalline structure having a grain size of less than a nanometer level (for example, 300 nm or less) or a crystal grain size smaller than the thickness of the semiconductor layer 30 1, reference numeral 302, hereinafter the same), and an amorphous portion having an amorphous structure (reference numeral 304 in FIG. 1, the same applies hereinafter). This semiconductor layer 30 is formed by deposition in a gas atmosphere including a semiconductor-containing gas and a process temperature of 700 DEG C or less, a pressure lower than the pressure of the step of forming the control passivation film 20. [

If the deposition pressure of the semiconductor layer 30 is lower than the pressure or the atmospheric pressure of the step of forming the control passivation film 20, the semiconductor layer 30 grows at a high speed, It is possible to prevent the crystallinity from increasing. More specifically, the pressure at the time of depositing the semiconductor layer 30 may be between 10 mtorr and 10 torr. Such a pressure range is limited to a range in which the formation of the semiconductor layer 30 is smoothly performed but the grain size is prevented from becoming large. However, the present invention is not limited thereto.

 Also, the semiconductor layer 30 can be grown at a high temperature at a high temperature by setting the process temperature at the time of depositing the semiconductor layer 30 to 700 ° C or lower, thereby preventing the crystal grain size from increasing or the crystallinity from being increased. As an example, the semiconductor layer 30 may be deposited at a process temperature of 580 to 700 ° C. If the temperature is less than 580 DEG C, the semiconductor layer 30 may have only an amorphous structure, and it may be difficult to realize high electrical characteristics due to the polycrystalline structure.

More specifically, the semiconductor layer 30 may be formed by raising the temperature from a temperature of 500 to 600 ° C to a process temperature of 700 ° C or lower, and then lowering the temperature to 500-600 ° C again. According to this, the semiconductor substrate 10, the control passivation film 20, and the like can be prevented from imposing a large burden due to a sudden change in temperature. However, the present invention is not limited thereto.

As described above, in this embodiment, the pressure and the process temperature in the process of forming or depositing the semiconductor layer 30 are limited to suppress the rapid growth of the semiconductor layer 30 to easily form the semiconductor layer 30 having a small grain size . It is expected that the semiconductor material will grow without scattering. Alternatively, when the semiconductor layer is formed at a high pressure (for example, normal pressure or a higher pressure) and a process temperature exceeding 700 ° C, the polycrystalline portion having a polycrystalline structure having a crystal grain size of nanometer It can be difficult to form. When the grain size of the semiconductor layer is increased, the crystallinity of the semiconductor layer can be easily changed and the passivation characteristic may be lowered in a subsequent high-temperature heat treatment process.

The semiconductor containing gas contained in the gas atmosphere used in the deposition process of the semiconductor layer 30 may include a compound of silicon and hydrogen (for example, silane (SiH ₄ )). And the gaseous atmosphere may comprise nitrogen gas together with the semiconductor containing gas. The nitrogen gas may play a role of controlling the partial pressure in the deposition process of the semiconductor layer 30. However, since the grain size of the semiconductor layer 30 can be increased if the amount of the nitrogen gas is increased, the nitrogen gas may be contained in an amount of 20 vol% or less. The nitrogen gas may be contained in an amount of 10 vol% or less (more specifically, 5 vol% or less) in order to effectively control the crystal grain size of the semiconductor layer 30 and the like. Alternatively, it is also possible that the gas atmosphere does not contain a nitrogen gas so as to effectively prevent the grain size of the semiconductor layer 30 from increasing. In addition, the gas atmosphere may not contain a hydrogen gas (for example, H ₂ ) composed of hydrogen other than the above-described semiconductor-containing gas, which is not in the form of a compound, or may contain 45 vol% or less of hydrogen gas. If the hydrogen gas contains more than 45 vol%, it may be difficult to keep the grain size of the polycrystalline portion 302 of the semiconductor layer 30 in a small range as described above.

As described above, the semiconductor layer 30 including the polycrystalline portion 302 having a desired crystal grain size can be formed by adjusting the temperature, the pressure, and the gas atmosphere in the deposition process of the semiconductor layer 30.

In this embodiment, a separate heat treatment for changing the crystal characteristics of the semiconductor layer 30 may not be performed between the deposition process of the semiconductor layer 30 and the doping process. In this way, the semiconductor layer 30 can have desired crystallization characteristics while simplifying the process. However, the present invention is not limited thereto. After the semiconductor layer 30 is formed, a separate heat treatment for recrystallizing the amorphous portion 304 may be performed to maintain the passivation effect. For example, after the semiconductor layer 30 is formed, the amorphous portion 304 can be recrystallized by irradiating a laser at room temperature.

In the above description, the semiconductor layer 30 has a specific crystal structure. However, the semiconductor layer 30 may have a crystal structure different from that described above. In one example, the semiconductor layer 30 may be composed of a microcrystalline, amorphous, or polycrystalline semiconductor. At this time, the semiconductor layer 30 can be formed, for example, by a thermal growth method, a deposition method (for example, low pressure chemical vapor deposition (LPCVD)), or the like. Various other methods can be applied.

Although the semiconductor layer 30 is formed only on the rear surface of the semiconductor substrate 10, the present invention is not limited thereto. The semiconductor layer 30 may be additionally formed on the front surface and / or the side surface of the semiconductor substrate 10 according to the method of manufacturing the semiconductor layer 30. [ The semiconductor layer 30 formed on the front surface of the semiconductor substrate 10 can be removed at a later stage.

5C, a first conductive type dopant is doped in a part of the semiconductor layer 30 to form a first conductive type region 32, and the entire surface of the semiconductor substrate 10 is textured to form an anti-reflection structure A second conductive type dopant is doped on the entire surface of the semiconductor substrate 10 and another portion of the semiconductor layer 30 to form the electric field region 130 and the second conductive type region 34 as shown in FIG. . At this time, an undoped region, which is not doped with a dopant, may be positioned between the first conductive type region 32 and the second conductive type region 34, and this region may constitute the barrier region 36.

At this time, in this embodiment, the diffusion regions 320 and 340 can be formed in or after the step of forming the conductive type regions 32 and 34. For example, the first conductivity type region 32 and the first diffusion region 320 are formed, and then the second conductivity type region 34 and the second diffusion region 340 are formed.

That is, as shown in FIG. 5C, the first conductivity type region 32 and the second diffusion region 320 may be formed first. For example, a first dopant layer (not shown) including a first conductive dopant may be formed on the semiconductor layer 30 at a position corresponding to a region where the first conductive region 32 is to be formed, For example, laser irradiation) to form the first conductivity type region 32 and the first diffusion region 320. [ When the first conductive type region 32 is formed, the first conductive type dopant is injected to the semiconductor substrate 10 through the first conductive type region 32 (or the semiconductor layer 30) and the control passivation film 20, And the first diffusion region 320 is formed. As another example, after the first conductive type region 32 is formed in the semiconductor layer 30, the first conductive type region 32 is heat-treated to form the first conductive type region 32 in the first conductive type region 32. [ The dopant may be diffused. Then, the first conductive type dopant included in the first conductive type region 32 reaches the semiconductor substrate 10 through the control passivation film 20 to form the first diffusion region 320. At this time, various methods can be applied as a method of performing the heat treatment on the first conductivity type region 32. For example, a laser can be used.

However, the present invention is not limited thereto. The first conductivity type region 32 and the first diffusion region 320 may be formed by ion implantation, thermal diffusion by heat treatment using a gas including a dopant, thermal treatment performed after formation of a doped layer, and the like Can be formed by various methods.

Wet or dry texturing may be used for texturing the surface of the semiconductor substrate 10. [ The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be formed uniformly, but the processing time is long and damage to the semiconductor substrate 10 may occur. Alternatively, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

5D, the second conductive type region 34, the second diffusion region 340, and the electric field region 130 can be formed.

For example, a second dopant layer (not shown) including a second conductive dopant may be formed on the semiconductor layer 30 at a position corresponding to a region where the second conductive region 34 is to be formed, For example, laser irradiation) to form the second conductivity type region 34 and the second diffusion region 340. [ The second conductive type dopant then passes through the second conductive type region 34 (or the semiconductor layer 30) and the control passivation film 20 when the second conductive type region 34 is formed, And the second diffusion region 340 is formed. As another example, a second conductivity type region 34 may be formed in the semiconductor layer 30, followed by a heat treatment to the second conductivity type region 34 to form a second conductivity type region 34 in the second conductivity type region 34. [ The dopant may be diffused. Then, a second conductive dopant included in the second conductive type region 34 reaches the semiconductor substrate 10 through the control passivation film 20 to form the second diffusion region 340. At this time, various methods can be applied as a method of performing heat treatment on the second conductivity type region 34, for example, a laser can be used.

However, the present invention is not limited thereto. The second conductive type region 34 and the second diffusion region 340 may be formed by ion implantation, thermal diffusion by heat treatment using a gas containing a dopant, heat treatment performed after formation of a doped layer, or the like Can be formed by various methods.

The electric field region 130 may be formed by various methods such as ion implantation, heat diffusion by heat treatment using a gas including a dopant, heat treatment performed after forming a doped layer, and laser doping .

In particular, the second conductivity type region 34, the second diffusion region 340, and the electric field region 130 may be simultaneously formed by a thermal diffusion method using a gas including a second conductivity type dopant. This can greatly simplify the process.

The second conductivity type region 34 and the second diffusion region 340 are formed after the first conductivity type region 32 and the first diffusion region 320 are formed. However, the present invention is not limited thereto. The first and second conductive regions 32 and 34 may be formed and then heat-treated to form the first and second diffusion regions 320 and 340 simultaneously or separately. In this embodiment, the first and second diffusion regions 320 and 340 are all provided. However, the first and second diffusion regions 320 and 340 may be provided, Diffusion regions 320 and 340 may not be provided.

The front electric field area 130 is formed by the same doping process as that of the second conductive area 34 and / or the second diffusion area 340. However, the front electric field area 130 may be formed by other processes .

That is, the formation order of the first conductive type region 32, the second conductive type region 34, the front electric field region 130, the first and second diffusion regions 320 and 340, and the texturing structure may vary It is possible.

Next, as shown in FIG. 5E, another insulating film is formed on the front and rear surfaces of the semiconductor substrate 10. That is, a front passivation film 24 and an antireflection film 26 are formed on the entire surface of the semiconductor substrate 10, and a rear passivation film 40 is formed on the rear surface of the semiconductor substrate 10.

More specifically, the front passivation film 24 and the antireflection film 26 are entirely formed on the front surface of the semiconductor substrate 10, and the rear passivation film 40 is formed on the rear surface of the semiconductor substrate 10 as a whole. The front passivation film 24, the antireflection film 26 or the rear passivation film 40 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating. The order of forming the front passivation film 24, the antireflection film 26, and the rear passivation film 40 is not limited.

Next, as shown in FIG. 5F, first and second electrodes 42 and 44 connected to the first and second conductivity type regions 32 and 34, respectively, are formed.

For example, the contact hole 46 is formed in the rear passivation film 40 by the patterning process, and then the first and second electrodes 42 and 44 are formed while filling the contact hole 46 . At this time, the contact hole 46 may be formed by various methods using laser ablation using a laser, etching solution, etch paste or the like. The first and second electrodes 42 and 44 may be formed by various methods such as a sputtering method, a plating method, and a deposition method. In particular, in this embodiment, the first and second electrodes 42 and 44 may be formed by a sputtering method.

However, the present invention is not limited thereto. Alternatively, the first and second electrode forming pastes may be applied on the rear passivation film 40 by screen printing or the like, and then fire through or laser firing contact may be performed to form the above- The first and second electrodes 42 and 44 may be formed. In this case, since the contact hole 46 is formed when the first and second electrodes 42 and 44 are formed, it is unnecessary to add a process of forming the contact hole 46 separately.

According to the present embodiment, it is possible to easily form the control passivation film 20 and the semiconductor layer 30 having desired characteristics by limiting process conditions. The diffusion regions 320 and 340 can be easily formed in the semiconductor substrate 10 corresponding to the conductive type regions 32 and 34 by the control passivation film 20. [ The crystallinity of the semiconductor layer 30 can be reduced even if a high-temperature annealing process or the like is performed by a low crystallinity or a small grain size. Thus, the manufacturing method of the solar cell 100 having excellent efficiency can be simplified.

The structure in which the first and second conductivity type regions 32 and 34 and the first and second electrodes 42 and 44 are all located on the rear surface of the semiconductor substrate 10 has been described as an example. However, the present invention is not limited thereto, and the control passivation film 20, the first and second conductivity type regions 32 and 34, and the diffusion regions 320 and 340 described above may be formed on the solar cell 100 of another structure. Can be applied.

Hereinafter, a solar cell according to another embodiment of the present invention and a method of manufacturing the same will be described in detail. Detailed descriptions will be omitted for the same or extremely similar parts as those described above, and only different parts will be described in detail. It is also within the scope of the present invention to combine the above-described embodiments or variations thereof with the following embodiments or modifications thereof.

FIG. 6 is a cross-sectional view illustrating a solar cell according to another embodiment of the present invention, and FIG. 7 is a plan view of the solar cell shown in FIG.

6 and 7, in this embodiment, the first conductive type region 32 is located on the first control passivation film 20a on one side of the semiconductor substrate 10, and the second conductive type region 34 And is located on the second control passivation film 20b located on the other surface of the semiconductor substrate 10. [ At this time, the first control passivation film 20a and the first conductive type region 32 are entirely formed on one surface of the semiconductor substrate 10, and the second control passivation film 20b is formed over the second conductive type region 34 And may be formed entirely on the other surface of the semiconductor substrate 10. In this embodiment, unlike the embodiment of FIGS. 1 to 5, the front electric field area 130 is not provided.

For example, the first control passivation film 20a may be in contact with the semiconductor substrate 10, and the first conductive type region 32 may be located in contact with the first control passivation film 20a. For example, the second control passivation film 20b may be in contact with the semiconductor substrate 10, and the second conductive type region 34 may be in contact with the second control passivation film 20b.

At this time, the first and second passivation films 20a and 20b may be the same as or very similar to the control passivation film 20 of the above-described embodiment. And the first and second control passivation films 20a and 20b may be formed by the same method as the control passivation film 20 of the above-described embodiment. The first control passivation film 20a formed on the front surface of the semiconductor substrate 10 and the second control passivation film 20b formed on the rear surface of the semiconductor substrate 10 in the process of forming the control passivation film 20 ) Can be formed together at the same time by the same process. In this case, the first passivation film 20a may be composed of a first doped portion (reference numeral 202 in FIG. 1) including a first conductive dopant, and the second passivation film 20b may include a second conductive dopant (Reference numeral 204 in FIG. 1). Although not shown in the drawing, the first and second passivation films 20a and 20b may have highly doped portions (202a and 204a in FIG. 1).

 And the first and second conductivity type regions 32 and 34 may be the same or very similar to the first or second conductivity type regions 32 and 34 of the above described embodiment except for the shape and / or position. The first and second semiconductor layers 30a and 30b constituting the first and second conductivity type regions 32 and 34 are formed in the semiconductor layer 30 in FIG. And the like. The first and second semiconductor layers 30a and 30b may be formed by the same method as the process for forming the semiconductor layer 30 of the above-described embodiment. For example, in the process of forming the semiconductor layer 30, the first semiconductor layer 30a located on the first control passivation film 20a on the front surface of the semiconductor substrate 10 and the first semiconductor layer 30a located on the rear surface of the semiconductor substrate 10 The second semiconductor layer 30b located on the second control passivation film 20b may be simultaneously formed by the same process.

In this embodiment, a first diffusion region 320 is formed as a whole on a portion of the semiconductor substrate 10 adjacent to the first control passivation film 20a in the lower portion of the first conductive type region 32, A second diffusion region 340 may be formed entirely in a portion of the semiconductor substrate 10 adjacent to the second control passivation film 20b under the region 34. [

In this embodiment, the first and second control passivation films 20a and 20b and the first and second conductivity type regions 32 and 34 have the characteristics of the above-described embodiment and the first and second diffusion regions 320 and 340 ) Were all formed. However, the present invention is not limited thereto, and at least one of the first and second control passivation films 20a and 20b and / or at least one of the first and second conductivity type regions 32 and 34 may be formed in the above- Can have the characteristics of. And either one of the first and second control passivation films 20a and 20b may be provided and one of the first and second conductive type regions 32 and 34 may be disposed in contact with the semiconductor substrate 10, 10 of the present invention. It is also possible that only one of the first and second diffusion regions 320 and 340 is formed, or both the first and second diffusion regions 320 and 340 are not formed.

The front passivation film 24 and the antireflection film 26 are formed on the front surface of the semiconductor substrate 10 on the first conductive type region 32 except for the first contact hole 461 corresponding to the first electrode 42. [ As shown in FIG. For example, the front passivation film 24 may contact the first conductivity type region 32 and the antireflection film 26 may contact the front passivation film 24. The rear passivation film 40 may be formed substantially over the rear surface of the semiconductor substrate 10 over the second conductive type region 34 except for the second contact hole 462 corresponding to the second electrode 44 . For example, the rear passivation film 40 may be formed in contact with the second conductive type region 34.

The first electrode 42 may be electrically connected to the first conductivity type region 32 by locating (e.g., contacting) the first conductivity type region 32. The second electrode 44 may be electrically connected to the second conductive type region 34 by locating (e.g., contacting) the second conductive type region 34. The first electrode 42 is electrically connected to the first passivation film 24 and the antireflection film 26 through the first contact hole 461 formed in the front passivation film 24 and the antireflection film 26 1 < / RTI > The second electrode 44 may be electrically connected to the second conductivity type region 34 through a second contact hole 462 formed in the back passivation film 40 (i.e., through the back passivation film 40) have.

In the drawings, the anti-reflection structures are formed on the front and rear surfaces of the semiconductor substrate 10, but an anti-reflection structure may be formed on either the front surface or the rear surface, or an anti-reflection structure may not be formed on the front surface and the rear surface.

The planar shape of the first and second electrodes 42 and 44 will be described in detail with reference to FIG.

Referring to FIG. 7, the first and second electrodes 42 and 44 may include a plurality of finger electrodes 42a and 44a spaced apart from each other with a predetermined pitch. Although the finger electrodes 42a and 44a are parallel to each other and parallel to the edge of the semiconductor substrate 10, the present invention is not limited thereto. The first and second electrodes 42 and 44 may include bus bar electrodes 42b and 44b formed in a direction crossing the finger electrodes 42a and 44a to connect the finger electrodes 42a and 44a. have. Only one bus bar electrode 42b or 44b may be provided, or a plurality of bus bar electrodes 42b and 44b may be provided with a larger pitch than the pitch of the finger electrodes 42a and 44a as shown in FIG. At this time, the width of the bus bar electrodes 42b and 44b may be larger than the width of the finger electrodes 42a and 44a, but the present invention is not limited thereto. Therefore, the width of the bus bar electrodes 42b and 44b may be equal to or smaller than the width of the finger electrodes 42a and 44a.

The finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may all be formed through the front passivation film 24 and the antireflection film 26 as viewed in cross section. That is, the first contact hole 461 may be formed corresponding to the finger electrode 42a and the bus bar electrode 42b of the first electrode 42, respectively. The finger electrode 44a and the bus bar electrode 44b of the second electrode 44 may all be formed through the rear passivation film 40. [ That is, the second contact holes 462 may be formed corresponding to the finger electrodes 44a and the bus bar electrodes 44b of the second electrode 44, respectively. However, the present invention is not limited thereto. As another example, the finger electrode 42a of the first electrode 42 is formed to pass through the front passivation film 24 and the antireflection film 26, and the bus bar electrode 42b is formed through the front passivation film 24 and the anti- (Not shown). In this case, the first contact hole 461 is formed in a shape corresponding to the finger electrode 42a, and may not be formed in a portion where only the bus bar electrode 42b is located. A finger electrode 44a of the second electrode 44 may be formed through the rear passivation film 40 and a bus bar electrode 44b may be formed on the rear passivation film 40. [ In this case, the second contact hole 462 is formed in a shape corresponding to the finger electrode 44a, and may not be formed at a portion where only the bus bar electrode 44b is located.

In the drawing, the first electrode 42 and the second electrode 44 have the same planar shape. The width and the pitch of the finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may be the same as the width and pitch of the finger electrode 44a and the bus bar electrode 42b of the second electrode 44, A width, a pitch, and the like of the first electrode 44b. In addition, the first electrode 42 and the second electrode 44 may have different planar shapes, and various other modifications are possible.

As described above, in this embodiment, the first and second electrodes 42 and 44 of the solar cell 100 have a certain pattern, so that the solar cell 100 can receive light from the front and back surfaces of the semiconductor substrate 10 It has a bi-facial structure. Accordingly, the amount of light used in the solar cell 100 can be increased to contribute to the efficiency improvement of the solar cell 100. However, the present invention is not limited thereto, and it is also possible that the second electrode 44 is formed entirely on the rear side of the semiconductor substrate 10. Various other variations are possible.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
20: Control passivation film
202: first doping portion
204: second doping portion
32: first conductivity type region
34: second conductivity type region
36: Barrier area
320: first diffusion region
340: second diffusion region
42: first electrode
44: Second electrode

Claims (18)

A semiconductor substrate including a base region;
A control passivation film formed on one surface of the semiconductor substrate and composed of an oxide film;
A semiconductor layer formed on the control passivation film and including a first conductive type region having a first conductivity type and a second conductive type region having a second conductive type opposite to the first conductive type, And
A first electrode coupled to the first conductivity type region, and a second electrode coupled to the second conductivity type region,
/ RTI >
Wherein the first and second conductivity type regions each comprise a polycrystalline silicon layer having a polycrystalline structure,
A first diffusion region formed adjacent to the control passivation film at a portion corresponding to the first conductivity type region in the semiconductor substrate and having a doping concentration lower than that of the first conductivity type region, And a second diffusion region that is formed adjacent to the control passivation film in part,
The thickness of the second diffusion region is larger than the thickness of the first diffusion region,
Wherein the first diffusion region and the second diffusion region are spaced apart from each other,
Wherein the control passivation film has a doped portion that is partially located between the first conductive type region and the first diffusion type region or between the second conductive type region and the second diffusion type region. The method according to claim 1,
And a barrier region composed of an intrinsic polycrystalline silicon layer is provided between the first conductive type region and the second conductive type region. The method according to claim 1,
Wherein the control passivation film is an amorphous film composed only of an amorphous structure or an amorphous film including a partially crystallized portion. The method according to claim 1,
Further comprising an insulating film located on the semiconductor substrate or the semiconductor layer,
Wherein the control passivation film has a thickness smaller than that of the insulating film,
Wherein the control passivation film includes a portion having a higher doping concentration than the insulating film. The method according to claim 1,
Wherein the doped portion includes a first doped portion that is partially located between the first conductive type region and the first diffusion type region and a second doped portion that is partially located between the second conductive type region and the second diffusion type region Including solar cells. 6. The method of claim 5,
Wherein the first doped portion or the second doped portion partially contains a heavily doped portion having a higher doping concentration than the other portion. The method according to claim 1,
And a doping concentration at which the doping concentration continuously decreases toward the semiconductor substrate when the first or second conductivity type region, the control passivation film, and the diffusion region are viewed in their thickness direction, Wherein the absolute value of the doping concentration gradient of the diffusion region is larger than the absolute value of the doping concentration gradient of the second conductivity type region. The method according to claim 1,
Wherein a thickness of the diffusion region is larger than a thickness of the first conductivity type region and the second conductivity type region. 6. The method of claim 5,
The first diffusion region and the second diffusion region being spaced from each other such that the base region is located between the first diffusion region and the second diffusion region,
A barrier region composed of an intrinsic polycrystalline silicon layer is provided between the first conductive type region and the second conductive type region,
Wherein an undoped undoped portion is located between the semiconductor substrate and the barrier region in the control passivation film. The method according to claim 1,
The absolute value of the doping concentration gradient of the second diffusion region is smaller than the absolute value of the doping concentration gradient of the first diffusion region when viewing the first and second diffusion regions in their thickness direction. Forming a control passivation film composed of an oxide film on one surface of a semiconductor substrate including a base region;
Forming a semiconductor layer on the control passivation film including a first conductive type region having a first conductivity type and a second conductive type region having a second conductive type opposite to the first conductive type, step; And
Forming an electrode including a first electrode connected to the first conductive type region and a second electrode connected to the second conductive type region;
Lt; / RTI >
Wherein the first and second conductivity type regions each comprise a polycrystalline silicon layer having a polycrystalline structure,
A first diffusion region formed adjacent to the control passivation film in a portion of the semiconductor substrate corresponding to the first conductivity type region and having a doping concentration lower than that of the first conductivity type region, And a diffusion region including a second diffusion region formed adjacent to the control passivation film in a portion corresponding to the second conductivity type region are formed together, and in the control passivation film, between the first conductivity type region and the first diffusion region Or a doped portion that is partially located between the second conductivity type region and the second diffusion region is formed,
The thickness of the second diffusion region is larger than the thickness of the first diffusion region,
Wherein the first diffusion region and the second diffusion region are spaced apart from each other with an interval therebetween. 12. The method of claim 11,
Wherein, in the step of forming the semiconductor layer, the semiconductor layer includes a barrier region composed of an intrinsic polycrystalline silicon layer between the first conductive type region and the second conductive type region. 12. The method of claim 11,
Wherein the control passivation film is an amorphous film composed only of an amorphous structure or an amorphous film including a partially crystallized portion. 12. The method of claim 11,
Further comprising forming an insulating film on the semiconductor substrate or the semiconductor layer,
Wherein the control passivation film has a thickness smaller than that of the insulating film,
Wherein the control passivation film includes a portion having a higher doping concentration than the insulating film. 12. The method of claim 11,
The step of forming the control passivation film may be performed in a gas atmosphere containing oxygen gas and chlorine gas, or in a gas atmosphere containing an inert gas or nitrogen gas, or may be carried out by decomposing gas containing ozone into ultraviolet rays Gt; 12. The method of claim 11,
Wherein the step of forming the control passivation film and the step of forming the semiconductor layer do not separately perform heat treatment on the control passivation film. 12. The method of claim 11,
Wherein forming the control passivation film comprises forming the control passivation film by a thermal oxidation process at a normal pressure and a temperature of 600 캜 to 800 캜. 12. The method of claim 11,
Wherein forming the semiconductor layer comprises:
Forming an intrinsic silicon layer;
And doping the first conductive dopant and the second conductive dopant to the intrinsic silicon layer to form the first conductive type region and the second conductive type region,
Lt; / RTI >
Wherein the first and second conductive dopants pass through the control passivation film to form the first and second diffusion regions in the doping step or after the doping step, And forming the doped portion including the first and second doped portions in a portion of the film.

Images