KR101970544B1

KR101970544B1 - Organic light emitting diode display device and method for driving the same

Info

Publication number: KR101970544B1
Application number: KR1020110101918A
Authority: KR
Inventors: 김지훈; 타로 하스미
Original assignee: 엘지디스플레이 주식회사
Priority date: 2011-10-06
Filing date: 2011-10-06
Publication date: 2019-08-13
Also published as: KR20130037491A

Abstract

The present invention provides an organic light emitting diode display which can realize a higher contrast ratio by alternately driving data lines, thereby simplifying a driver circuit of a display panel and preventing degradation of display image quality due to image signal distortion. And a driving method comprising: a display panel including a plurality of pixel areas to display an image; A gate driver configured to drive gate lines, emission control lines, and initialization lines of the display panel; A data driver configured to generate an image signal such that data lines adjacent to each other among the data lines of the display panel are alternately driven; A power supply unit supplying first and second power signals to power lines of the display panel and supplying a reference voltage to a compensation power line; A data switching unit configured to alternately select each of the data lines so that adjacent ones of the plurality of data lines are alternately driven and electrically connect the image signal output channels of the data driver; And a timing controller for aligning and supplying image data input from the outside to the data driver and controlling the data switching unit and the data and gate driver.

Description

Organic light emitting diode display and its driving method {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display, and by driving data lines alternately, a driver circuit of the display panel is simplified, and a higher contrast ratio is prevented by preventing display image degradation due to image signal distortion. The present invention relates to an organic light emitting diode display and a driving method thereof.

Recently, flat panel displays are emerging as liquid crystal displays, field emission displays, plasma display panels, and organic light emitting diode displays. Emitting Display). Among them, the organic light emitting diode display is a self-luminous device that emits an organic light emitting layer by recombination of electrons and holes.

Each of the plurality of unit pixels of the organic light emitting diode display includes an organic light emitting diode composed of an organic light emitting layer between an anode and a cathode, and a pixel circuit for independently driving each organic light emitting diode. Here, the pixel circuit adjusts the gray level of each pixel by adjusting the amount of current supplied to each organic light emitting diode.

Recently, a method of reducing manufacturing cost by simplifying the number of data driver circuits, for example, data integrated circuits (ICs), and the number of channels thereof among driving circuits for driving the display panel has emerged. This is a method of simplifying the number of data integrated circuits or the number of channels thereof by alternately driving image signal supply lines, that is, adjacent data lines, of the display panel.

However, in the alternative driving method of the adjacent data lines according to the related art, since data lines that do not receive an image signal are floated in the process of being alternately driven with each other, the contrast of the pre-charged image signal and the reference voltage is shortened. The problem of lowering the contrast ratio occurs.

Specifically, in the case of driving the data lines collectively instead of alternately driving them, since the image signals are supplied to each data line continuously in every horizontal line unit, even when the reference voltage and the image signal are shorted, Maintain the voltage level. However, in the case of alternately driving the data lines adjacent to each other, since the data lines not receiving the image signal are floated, the charged image signal voltage level may be distorted when the pre-charged image signal and the reference voltage are shorted. In this case, since the dark gray level signal having a low voltage level is greatly affected by the distortion, the brightness of the dark image is increased, resulting in a decrease in the contrast ratio.

SUMMARY OF THE INVENTION The present invention is to solve the above problems, and by driving the data lines alternately to simplify the driver circuit of the display panel and to prevent the degradation of the display image quality due to image signal distortion to achieve a higher contrast ratio An object of the present invention is to provide an organic light emitting diode display and a driving method thereof.

An organic light emitting diode display according to an embodiment of the present invention for achieving the above object includes a display panel for displaying an image having a plurality of pixel areas; A gate driver configured to drive gate lines, emission control lines, and initialization lines of the display panel; A data driver configured to generate an image signal such that data lines adjacent to each other among the data lines of the display panel are alternately driven; A power supply unit supplying first and second power signals to power lines of the display panel and supplying a reference voltage to a compensation power line; A data switching unit configured to alternately select each of the data lines so that adjacent ones of the plurality of data lines are alternately driven and electrically connect the image signal output channels of the data driver; And a timing controller for aligning and supplying image data input from the outside to the data driver and controlling the data switching unit and the data and gate driver.

The timing controller arranges and supplies the image data from the outside to the data driver so that the adjacent data lines are alternately driven within at least one horizontal period to display an image, and the data switching unit is provided in at least one horizontal line unit. The data switching unit is controlled by generating at least one selection signal so as to alternately select adjacent data lines to be electrically connected to the image signal output channel of the data driver.

The gate driver sequentially drives the gate control signal, the emission control signal, and the initialization signals in every horizontal line unit according to a gate control signal from the timing controller to drive the gate lines, the emission control lines, and the initialization lines. It generates, but characterized in that the initialization signals are generated and output before the gate control signals.

Sub pixels are arranged in a matrix in each pixel area, and each sub pixel of the display panel includes a light emitting cell for displaying an image by emitting light, and a cell driver for driving the light emitting cells independently. The driving unit includes first to fifth switching elements, a driving switching element, and a storage capacitor, wherein the first switching element is configured to receive an image signal from the data line in response to a gate voltage of a low logic from the gate line. The storage capacitor is charged by supplying a node, and the second switching element connects the driving switching element by connecting the gate electrode and the drain electrode of the driving switching element with each other in response to an initialization voltage of a low logic from the initialization line. The third switch is connected in the form of a diode An element connects the drain electrode of the drive switching element to the anode electrode of the light emitting cell in response to the light emission control voltage of the low logic from the light emission control line, and the fourth switching element is connected to the low logic of the low logic from the light emission control line. And in response to a light emission control voltage, supply a reference voltage supplied through the compensation power line to the first node, and the fifth switching element supplies the compensation power line in response to a gate voltage of a low logic from the initialization line. The reference voltage is supplied to the third node to which the light emitting cell is connected.

In addition, a method of driving an organic light emitting diode display according to an exemplary embodiment of the present invention for achieving the above object includes a plurality of pixel areas using a gate driver to emit light and gate lines of a display panel displaying an image. Driving control lines and initialization lines; Generating an image signal by using a data driver to alternately drive adjacent data lines among the data lines of the display panel; Supplying first and second power signals to power lines of the display panel and supplying a reference voltage to a compensation power line; Alternately selecting each of the data lines so that adjacent ones of the plurality of data lines are alternately driven by using a data switching unit and electrically connecting the data lines to an image signal output channel of the data driver; And aligning and supplying image data input from the outside to the data driver and controlling the data switching unit, the data and the gate driver.

The controlling of the data switching unit and the data and gate driver may be performed by arranging image data from the outside so that the adjacent data lines are alternately driven within at least one horizontal period to display an image. And generating at least one selection signal such that the data switching unit alternately selects adjacent data lines in units of at least one horizontal line and electrically connects to the image signal output channel of the data driver. It characterized in that it comprises a step of supplying to the wealth.

The driving of the gate lines and the initialization lines may include sequentially setting the gate control signal and the initialization signals in every horizontal line unit according to a gate control signal from the timing controller to drive the gate lines and the initialization lines. Generate, but generate and output the initialization signals before the gate control signals.

An organic light emitting diode display and a method of driving the same according to an exemplary embodiment of the present invention having various technical features as described above simplify the driver circuit of the display panel by alternately driving the data lines of the display panel. Can reduce the manufacturing cost. In addition, in the process of alternately driving the data lines, a high contrast ratio may be realized and the reliability of the product may be improved by preventing the display quality from being lowered due to image signal distortion.

1 is a block diagram illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram illustrating one sub-pixel of the display panel shown in FIG. 1. FIG.
3 is a waveform diagram illustrating a method of driving an organic light emitting diode display according to the present invention;

Hereinafter, an organic light emitting diode display and a driving method thereof according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention. 2 is an equivalent circuit diagram illustrating one sub-pixel of the display panel illustrated in FIG. 1.

An organic light emitting diode display shown in FIG. 1 includes a display panel 1 having a plurality of pixel areas to display an image; A gate driver 2 driving the gate lines GL1 to GLn, the emission control lines EL1 to ELn, and the initialization lines INI of the display panel 1; A data driver 3 generating an image signal such that data lines adjacent to each other among the data lines DL1 to DLm of the display panel 1 are alternately driven; The power supply unit 4 which supplies the first and second power signals VDD and GND to the power lines PL1 to PLm of the display panel 1 and supplies the reference voltage Vref to the compensation power line CPL. ); Each data line is alternately selected to alternately drive adjacent data lines among the plurality of data lines DL1 to DLm and electrically connected to the image signal output channels CH1 to CHn of the data driver 3. A data switching unit 10 to make; And a timing controller 5 for aligning and supplying the image data RGB input from the outside to the data driver 3 and controlling the data switch 10 and the data and gate drivers 3 and 2.

In the display panel 1, a plurality of sub-pixels P are arranged in a matrix form in each pixel area to display an image, and each sub-pixel P independently of the light emitting cell OLD and the light emitting cell OLD. And a cell drive unit (DVD) for driving. Specifically, each sub-pixel P as shown in FIG. 2 has a gate line GL, a data line DL, a compensation power line CPL, an emission control line EL, and an initialization line INI. ) And a light emitting cell OLD, which is equivalently represented by a diode connected between the cell driver DVD and the cell power source DVD and the second power signal GND, respectively. Equipped.

The cell driver DVD includes first to fifth switching elements T1 to T5, a driving switching element DT, and a storage capacitor Cst. Here, the first to fifth switching elements T1 to T5 and the driving switching element DT may be constituted by an NMOS transistor or a PMOS transistor. Hereinafter, the first to fifth switching elements T1 to T5 and the driving switching element DT may be formed. An example in which the driving switching device DT is made of a PMOS transistor will be described.

The first switching element T1 supplies the data signal Vdata from the data line DL to the first node N1 in response to the gate voltage of the low logic from the gate line GL, thereby providing a storage capacitor ( Cst) is charged.

The second switching elements T2a and T2b connect the gate electrode and the drain electrode of the driving switching element DT to each other in response to the initialization voltage of the low logic from the initialization line INI to form a diode. Connect to

The third switching element T3 connects the drain electrode of the driving switching element DT to the anode electrode of the light emitting cell OLD in response to the low logic light emission control voltage from the light emission control line EL. That is, the third switching element T3 supplies the data current output from the driving switching element DT to the light emitting cell OLD according to the light emission control voltage of the low logic.

The fourth switching element T4 supplies the reference voltage Vref supplied through the compensation power line CPL to the first node N1 in response to the light emission control voltage of the low logic from the light emission control line EL. do.

In response to the gate voltage of the low logic from the initialization line INI, the fifth switching element T5 supplies a reference voltage Vref supplied through the compensation power line CPL to the third light emitting cell OLD. Supply to node N2. Here, the fifth switching element T5 does not affect the driving process even if the fifth switching element T5 is not provided as a stabilization element of the cell driver DVD.

The driving switching element DT controls the amount of current flowing in the light emitting cell OLD in response to the voltage on the second node N2.

The storage capacitor Cst is formed between the first and second nodes N1 and N2 to store the difference voltage between the first and second nodes N1 and N2, and the first switching element T1 is turned off. The on-state state of the driving switching device DT is maintained for a predetermined period, for example, one frame period, by using the stored voltage.

The cell driving unit DVD configured as described above allows the second switching elements T2a and T2b to connect the driving switching element DT in the form of a diode in response to a logic initialization signal supplied from the initialization line INI. Before the data signal Vdata is supplied to the first node N1 by the first switching element T1, the second and third nodes N2 and N3 are initialized to provide the data signal Vdata and the reference voltage ( Vref) can be prevented from shorting.

The light emitting cell OLD includes an anode electrode connected to the cell driver DVD, an organic layer formed between the cathode electrode, the anode electrode, and the cathode electrode connected to the second power signal GND having the low potential voltage. The light emitting cell OLD emits light by a current from the driving switching element DT through the third switching element T3 of the cell driving unit DVD.

The gate driver 2 receives the gate control signal GVS from the timing controller 5, for example, a gate on signal in response to a gate start pulse GSP and a gate shift clock GSC. (Eg, the gate voltage of the low logic) is sequentially generated, and the pulse width of the gate-on signal is controlled according to a gate output enable (GOE) signal. The gate-on signals are sequentially supplied to the gate lines GL1 to GLn. Here, a gate-off voltage (eg, a high logic gate voltage) is supplied to a period when the gate-on voltage is not supplied to the gate lines GL1 to GLn. Accordingly, the gate driver 2 causes the first switching element T1 connected to the gate lines GL1 to GLn to be driven in units of the gate line GL. Here, the gate driver 2 may supply a high logic gate voltage during a data input period in one horizontal period and a low gate logic gate voltage during a scan period in one horizontal period. In this case, the data voltage is not supplied to each light emitting cell OLD in the data input period, but the data voltage is supplied to each light emitting cell OLD during the scan period in one horizontal period.

In addition, the gate driver 2 sequentially generates emission control voltages of high or low logic and supplies the emission control voltages to the emission control lines EL1 to ELn. Here, the emission control voltage sequentially output adjusts a period during which the reference voltage Vref is supplied to the first node N1 and a period during which a current flows in the light emitting cell OLD, that is, a period during which an image is displayed. In other words, the gate driver 2 adjusts the display period of the image and the blanking period during which the black image is displayed under the control of the timing controller 5.

In addition, the gate driver 2 sequentially generates initialization signals in units of horizontal lines using the gate control signal GVS from the timing controller 5, and sequentially initializes the initialization signals to the initialization lines INI. Supply. In this case, the initialization signals are first supplied to the initialization lines INI in the initialization period before the gate-on signals are supplied to initialize the second node N2 and the third node N2. That is, before the data signal Vdata is supplied to the first node N1 of the cell driver DVD, the initialization signal is supplied to the second switching elements T2a and T2b so that the driving switching element DT is diode-shaped. The second and third nodes N2 and N3 are initialized before the data signal Vdata is supplied to the first node N1 by the first switching element T1.

The data driver 3 includes a data control signal DVS from the timing controller 5, for example, a source start signal (SSP), a source shift clock (SSC), and a source output enable (SSC). Generates and outputs an image signal by 1/2 horizontal line every 1/2 horizontal period so that adjacent data lines DL1 through DLm are alternately driven within at least one horizontal period using a source output enable (SOE) signal. . In other words, the data driver 3 latches the digital image data inputted by one horizontal line in accordance with the SSC, and then alternates the latched image data Data within at least one horizontal period between adjacent data lines DL1 to DLm. Convert into an analog video signal to drive as a target. In response to the SOE signal, an image signal corresponding to 1/2 horizontal line is supplied to each output channel CH1 through CHn every 1/2 horizontal period in which a scan pulse is supplied to each gate line GL1 through GLn. At this time, the data driver 3 selects a gamma voltage having a predetermined level according to the gray value of the digital image data Data, and supplies the selected gamma voltage to each output channel CH1 to CHn as an image signal.

The timing controller 5 aligns and supplies the image data RGB from the outside to the data driver 3 such that adjacent data lines DL1 to DLm are alternately driven within at least one horizontal period to display an image. The gate control signal GCS and the data control signal DCS are generated using the synchronization signals DCLK, DE, Hsync, and Vsync from the outside, and the data driver 34 and the gate driver 2 are respectively controlled. .

In addition, the timing controller 5 alternately selects data lines DL1 to DLn adjacent to each other by at least one horizontal line unit so that the data switching unit 10 outputs the image signal output channels CH1 to CH1 of the data driver 3. At least one selection signal CS is generated to be electrically connected to the CHn, and the data switching unit 10 is controlled. Here, the timing controller 8 generates the at least one selection signal CS alternately in units of at least one horizontal period or every frame period so that the phase is changed and supplies the changed data to the data switching unit 10. For example, the selection signal CS may be generated and supplied to the data switching unit 10 to be changed to different logic levels within at least one horizontal period.

3 is a waveform diagram illustrating a method of driving an organic light emitting diode display according to the present invention.

One frame period, that is, the frame period for each pixel, is divided into an initialization period t0, a data charger period t1, and a light emission period t2.

First, in the initialization period t0, before the low logic gate voltage is sequentially supplied to the corresponding gate line GL, low logic level initialization signals are supplied to the initialization lines INI to provide the second node N2. And the third node N2 are initialized. In this case, the second switching elements T2a and T2b connect the driving switching element DT in the form of a diode in response to a logic initialization signal supplied from the initialization line INI, thereby providing the first switching element T1. By initializing the second and third nodes N2 and N3 before the data signal Vdata is supplied to the first node N1, the short circuit of the data signal Vdata and the reference voltage Vref is prevented. can do.

A low logic gate voltage is sequentially supplied to the gate line GL between the data chargers t2, and then a light emission control voltage of high logic is supplied to the light emission control line EL. Accordingly, the first, second and fifth switching elements T1, T2, and T5 of each sub pixel P are turned on, and the third and fourth switching elements T3 and T4 are turned off. do. The data voltage Vdata from the data line DL is supplied to the first node N1 through the turned-on first switching element T1, and is driven through the turned-on second switching element T2. The gate electrode and the drain electrode of the switching element DT are connected to each other. Accordingly, since the driving switching element DT becomes a forward diode, the threshold voltage Vth of the driving switching element DT is supplied to the gate electrode of the driving switching element DT, that is, the second node N2. The threshold voltage Vth of the driving switching element DT is sampled at the two nodes N2. At this time, the first power signal VDD, which is a high potential voltage, is supplied to the source electrode of the driving switching element DT, so that the threshold voltage of the first power signal VDD and the driving switching element DT is supplied to the second node N2. The difference voltage VDD-Vth is supplied.

Subsequently, during the light emission period t2, a high logic gate voltage is supplied to the gate line GL, and a light emission control signal of low logic is supplied to the light emission control line EL. Accordingly, each of the first, second and fifth switching elements T1, T2, and T5 is turned off while the third and fourth switching elements T3 and T4 are turned on. In this case, the reference voltage Vref is supplied to the first node N1 through the turned-on fourth switching element T4.

At this time, the voltage across the storage capacitor Cst is kept constant because no current path is formed in the cell driver DVD. Therefore, the voltage on the second node N2, which is the other end of the storage capacitor Cst, is changed by the voltage change amount Vref-Vdata on the first node N1, which is one end of the storage capacitor Cst. That is, VDD-Vth + Vref-Vdata is supplied to the second node N2.

Subsequently, the driving switching element DT is turned on by the voltage between the gate and source electrodes. Accordingly, the current supplied from the driving switching element DT to the light emitting cell OLD through the third switching element T3, that is, the current N3I of the third node N3 is expressed by Equation 1 below. In Equation 1, β represents a constant value, and Vth_R represents an actual threshold voltage of the driving switching device DT.

In Equation 1, if the threshold voltage Vth of the sampled driving switching element DT and the threshold voltage Vth_R of the actual driving switching element are the same, the current output to the driving switching element DT is a high potential voltage ( VDD) is determined by the reference voltage Vref and the data voltage Vdata without being affected by the drop and the threshold voltage of the driving switching element DT. Therefore, deterioration in image quality due to hysteresis of the driving switching element DT may be minimized.

As described above, the organic light emitting diode display and the driving method thereof according to the exemplary embodiment of the present invention simplify the driver circuit of the display panel by alternately driving the data lines of the display panel 1 of the organic light emitting diode display. The manufacturing cost can be reduced. In addition, in the process of alternately driving the data lines, a high contrast ratio may be realized and the reliability of the product may be improved by preventing the display quality from being lowered due to image signal distortion.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims

A display panel including a plurality of pixel areas to display an image;
A gate driver configured to drive gate lines, emission control lines, and initialization lines of the display panel, and supply driving signals to the initialization lines before the gate lines and emission control lines;
A data driver configured to generate an image signal such that data lines adjacent to each other among the data lines of the display panel are alternately driven;
A power supply unit supplying first and second power signals to power lines of the display panel and supplying a reference voltage to a compensation power line;
A data switching unit configured to alternately select each of the data lines so that adjacent ones of the plurality of data lines are alternately driven and electrically connect the image signal output channels of the data driver; And
An organic light emitting diode display comprising: a timing controller for aligning and supplying image data input from an external device to the data driver and controlling the data switch and the data and gate drivers;
In each pixel area
The sub pixels are arranged in a matrix form, each sub pixel of the display panel includes a light emitting cell for displaying an image by emitting light, and a cell driver for driving the light emitting cells independently.
The cell driver includes first to fifth switching elements, a driving switching element, and a storage capacitor,
The first switching element supplies the image signal from the data line to the first node in response to a low logic gate voltage from the gate line while the potential of the gate electrode of the driving switching element is initialized. To charge,
The second switching element connects the gate electrode and the drain electrode of the driving switching element to each other in response to the initialization voltage of the low logic from the initialization line in the initialization period before the gate on signal is supplied to the gate electrode of the driving switching element. Thereby connecting the drive switching element in the form of a diode,
A third switching element connects the drain electrode of the driving switching element to the anode electrode of the light emitting cell in response to a low logic light emission control voltage from the light emission control line,
A fourth switching element supplies a reference voltage supplied through a compensation power line to the first node in response to a light emission control voltage of a low logic from the light emission control line,
The fifth switching device simultaneously supplies a reference voltage supplied through the compensation power line to the third node to which the light emitting cell is connected in response to the gate voltage of the low logic provided to the second switching device through the initialization line. An organic light emitting diode display, characterized in that.

The method of claim 1,
The timing controller
The image data from the outside are aligned and supplied to the data driver so that the adjacent data lines are alternately driven within at least one horizontal period to display an image.
Controlling the data switching unit by generating at least one selection signal such that the data switching unit alternately selects adjacent data lines in at least one horizontal line unit and electrically connects the image signal output channels of the data driver unit. An organic LED display characterized in that.

The method of claim 2,
The gate driver
In order to drive the gate lines, the light emission control lines, and the initialization lines, the gate control signal, the light emission control signal, and the initialization signals are sequentially supplied in every horizontal line unit according to a gate control signal from the timing controller. An organic LED display characterized in that.

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The gate driver drives the gate lines, the light emission control lines, and the initialization lines of the display panel including a plurality of pixel areas to display an image, but is the first to the initialization lines rather than the gate lines and the light emission control lines. Supplying a driving signal;
Generating an image signal by using a data driver to alternately drive adjacent data lines among the data lines of the display panel;
Supplying first and second power signals to power lines of the display panel and supplying a reference voltage to a compensation power line;
Alternately selecting each of the data lines so that adjacent ones of the plurality of data lines are alternately driven by using a data switching unit and electrically connecting the data lines to an image signal output channel of the data driver; And
The method of driving an organic light emitting diode display device comprising the step of aligning image data input from an external device and supplying the data data to the data driver and controlling the data switch and the data and gate drivers.
In each pixel area
The sub pixels are arranged in a matrix form, each sub pixel of the display panel includes a light emitting cell for displaying an image by emitting light, and a cell driver for driving the light emitting cells independently.
The cell driver includes first to fifth switching elements, a driving switching element, and a storage capacitor,
The first switching element supplies the image signal from the data line to the first node in response to a low logic gate voltage from the gate line while the potential of the gate electrode of the driving switching element is initialized. To charge,
The second switching element connects the gate electrode and the drain electrode of the driving switching element to each other in response to the initialization voltage of the low logic from the initialization line in the initialization period before the gate on signal is supplied to the gate electrode of the driving switching element. Thereby connecting the drive switching element in the form of a diode,
A third switching element connects the drain electrode of the driving switching element to the anode electrode of the light emitting cell in response to a low logic light emission control voltage from the light emission control line,
A fourth switching element supplies a reference voltage supplied through a compensation power line to the first node in response to a light emission control voltage of a low logic from the light emission control line,
The fifth switching device simultaneously supplies a reference voltage supplied through the compensation power line to the third node to which the light emitting cell is connected in response to the gate voltage of the low logic provided to the second switching device through the initialization line. A method of driving an organic light emitting diode display, characterized in that.

The method of claim 5,
Controlling the data switching unit and the data and gate driver
Arranging and supplying image data from the outside so that the adjacent data lines are alternately driven within at least one horizontal period to display an image, and
At least one selection signal is generated and supplied to the data switching unit so that the data switching unit alternately selects adjacent data lines in units of at least one horizontal line and electrically connects the image signal output channels of the data driving unit. And driving the organic light emitting diode display.

The method of claim 6,
Driving the gate lines and the initialization lines
In order to drive the gate lines and the initialization lines, the gate control signal and the initialization signals are sequentially supplied in every horizontal line according to the gate control signal from the timing controller. Way.

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