KR101968178B1 - Timing control unit and liquid crystal display device comprising the same - Google Patents

Abstract

There is provided a timing control unit and a liquid crystal display device including the same that can reduce the number of layers and manufacturing cost of a printed circuit board. The timing control unit and the liquid crystal display including the same include a control signal generating unit for receiving a plurality of control signals from the outside to output a plurality of first gate control signals for driving a plurality of gate lines, And a level shifter for converting the plurality of first gate control signals to a constant voltage level and outputting a plurality of second gate control signals, wherein the plurality of second gate control signals includes a gate start signal (VST) 4 clock signals CLK1 to CLK4, and first and second gate driving voltages VDD_O and VDD_E.

Description

TECHNICAL FIELD [0001] The present invention relates to a timing control unit and a liquid crystal display including the timing control unit,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing controller and a liquid crystal display including the same, and more particularly, to a timing controller and a liquid crystal display including the same, which can reduce the number of layers and manufacturing cost of a printed circuit board.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used today because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

2. Description of the Related Art In general, a liquid crystal display (LCD) displays an image by controlling the light transmittance of a liquid crystal having dielectric anisotropy using an electric field.

Such a liquid crystal display device receives a control signal from a timing controller (not shown) to generate a gate signal, sequentially supplies the generated gate signal to a gate line (not shown), and turns on the thin film transistor connected to the gate line A data driver (not shown) receiving a control signal and image data from the timing controller and applying a data voltage corresponding to the image data to a data line (not shown), a gate driver (not shown) A voltage generating unit (not shown) for supplying the operating power of each of the driving units and generating and supplying a common voltage to the liquid crystal panel, and a plurality of gate control signals outputted from the timing control unit, And outputs a level shifter (not shown).

Here, the timing controller receives a plurality of control signals provided from outside, for example, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, a main clock DCLK, and a data enable signal DE, And generates and outputs a plurality of gate control signals input to the driving unit. The plurality of gate control signals output from the timing controller are converted into a constant voltage level through the level shifter, and then input to the gate driver. The plurality of gate control signals generated in the timing control section may include, for example, a start signal VST, first to fourth clock signals CLK1 to CLK4, first and second driving voltages VDD_O and VDD_E, And may be the same signal as the second gate modulated signals GPM1 and GPM2.

Also, a plurality of pin assignments are required to transmit a plurality of gate control signals to the level shifter in the timing controller, and a plurality of pins are required to receive a plurality of gate control signals transmitted from the timing controller in the level shifter, A plurality of pin assignments are required for converting a plurality of gate control signals to a constant voltage level and then outputting them to the gate driver.

Accordingly, a plurality of pins are required to be allocated to the timing control section and the level shifter, and a plurality of wirings for transferring data between the timing control section and the level shifter are required. Therefore, the size of the timing control unit and the level shifter are increased due to the multiple pin assignments, the size of the printed circuit board is increased due to a plurality of wires for data transmission, and the number of layers and manufacturing cost of the printed circuit board are increased There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a level shifter in a timing control section so that a plurality of pins are not required for a timing control section and a level shifter, Thereby reducing the number of layers of the printed circuit board and a liquid crystal display device including the same.

In addition, the present invention provides a timing control unit having a level shifter in a timing control unit to reduce the number of layers of a printed circuit board, thereby reducing the manufacturing cost of a printed circuit board, and a liquid crystal display device including the same.

Other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above objects, a timing control unit according to an embodiment of the present invention includes a control signal generating unit for receiving a plurality of control signals from the outside and outputting a plurality of first gate control signals for driving a plurality of gate lines, And a level shifter for converting the plurality of first gate control signals output from the control signal generator to a constant voltage level and outputting a plurality of second gate control signals.

The timing control unit may further include a data processing unit for receiving image data from outside and sorting and outputting the image data to be suitable for driving the liquid crystal panel.

The plurality of second gate control signals includes a gate start signal VST, first to fourth clock signals CLK1 to CLK4, and first and second gate driving voltages VDD_O and VDD_E.

The plurality of second gate control signals further include a gate discharge signal.

The plurality of second gate control signals are provided to the gate driver through the data transfer wiring.

According to another aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel for displaying an image; first and second gate drivers for driving gate lines formed on both sides of the liquid crystal panel, A data driver for driving a data line formed on the liquid crystal panel, and a plurality of first gate control signals for driving a plurality of gate lines and a plurality of data lines by receiving a plurality of control signals from an external source, And a level shifter for converting the plurality of first gate control signals output from the control signal generator to a predetermined voltage level and outputting a plurality of second gate control signals, .

The timing control unit may further include a data processing unit for receiving image data from outside and sorting and outputting the image data to be suitable for driving the liquid crystal panel.

The plurality of second gate control signals includes a gate start signal VST, first to fourth clock signals CLK1 to CLK4, and first and second gate driving voltages VDD_O and VDD_E.

The plurality of second gate control signals further include a gate discharge signal.

The plurality of second gate control signals are provided to the gate driver through the data transfer wiring.

As described above, the timing control unit and the liquid crystal display including the same according to the present invention include a level shifter in the timing control unit, so that it is not necessary to assign a plurality of pins to the timing control unit and the level shifter, There is no need for a separate wiring for transmission, and the number of layers of the printed circuit board can be reduced.

In addition, the timing control unit and the liquid crystal display device including the same according to the present invention provide a level shifter in the timing control unit to reduce the number of printed circuit boards, thereby reducing the manufacturing cost of the printed circuit board.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.
2 is a block diagram illustrating a timing controller according to an embodiment of the present invention;
3 shows a level shifter according to an embodiment of the present invention.
4 is a timing diagram of gate control signals output from a level shifter according to one embodiment of the present invention;
5 is a timing chart of a data signal output from a timing control unit according to one embodiment of the present invention;
6 illustrates a printed circuit board according to one embodiment of the present invention.
7 is a view showing a connection relationship between a liquid crystal panel and a gate discharge circuit according to an embodiment of the present invention;

Hereinafter, preferred embodiments of a timing controller and a liquid crystal display including the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 1, the liquid crystal panel 110 includes a plurality of display signal lines and a plurality of unit pixels arranged in a matrix.

Here, the display signal line is formed in a display region (not shown) and includes a plurality of gate lines GL for transferring gate signals and a plurality of data lines DL for transferring data signals. At this time, the gate lines GL extend in the row direction, are substantially parallel to each other, the data lines DL extend in the column direction, and are substantially parallel to each other.

Each unit pixel includes a switching element connected to a display signal line and a liquid crystal capacitor Clc and a storage capacitor Cst connected to the switching element.

The control terminal and the providing terminal of the three-terminal device are connected to the gate line GL and the data line DL, respectively, and the output terminals thereof are connected to the liquid crystal capacitors Clc and Clc. And is connected to the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, that is, the pixel electrode of the array substrate and the common electrode of the color filter substrate, and the liquid crystal layer between the two electrodes functions as a dielectric. The pixel electrode is connected to the switching element (TFT), and the common electrode is formed on the front surface of the color filter substrate and receives the common voltage Vcom. Here, a common electrode may be provided on the array substrate, and both electrodes may be linear or bar-shaped.

The storage capacitor Cst is formed by superimposing a separate signal line (not shown) and a pixel electrode provided on the array substrate, and a predetermined voltage such as the common voltage Vcom is applied to the separate signal lines. However, the storage capacitor Cst may be formed by superimposing the pixel electrode on the immediately preceding gate line via the insulator.

On the other hand, in order to realize color display, each unit pixel must be able to display a color, which can be achieved by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. Here, the color filter may be formed in the corresponding region of the color filter substrate, or may be formed on or below the pixel electrode of the array substrate.

A polarizer (not shown) for polarizing light is attached to the outer surface of at least one of the array substrate and the color filter substrate of the liquid crystal panel 110.

The first and second gate drivers 120 and 122 are disposed on both sides of the liquid crystal panel 110, respectively. The first and second gate drivers 120 and 122 are connected to the respective gate lines GL to generate a gate signal composed of a combination of the gate-on voltage Von and the gate-off voltage Voff, To the line GL.

Here, the first and second gate drivers 120 and 122 are formed together with a thin film transistor (thin film transistor) process on a non-display area (not shown) of the liquid crystal panel 110 to reduce manufacturing cost and minimize power consumption A gate in panel (GIP) method is used.

The data driver 130 is connected to a data line DL of the liquid crystal panel 110. The data driver 130 generates a plurality of gradation voltages based on a plurality of gamma voltages provided from the outside, And is usually composed of a plurality of integrated circuits. Here, the data driver 130 may be formed on the liquid crystal panel 110 or not.

The timing controller 140 generates a gate control signal CONT1 for controlling the operation of the first and second gate drivers 120 and 122 and a plurality of data control signals CONT2 for controlling the operation of the data driver 130 And provides a gate control signal CONT1 to the first and second gate drivers 120 and 122 and a plurality of data control signals CONT2 to the data driver 130, respectively.

The voltage generating unit 150 generates a plurality of driving voltages for operating the driving units 120, 122, 130, and 140. For example, the voltage generator 150 may generate first and second gate voltages VGH and VGL and a driving voltage VDD, which are used as an input voltage of a level shifter (not shown).

Hereinafter, the display operation of the liquid crystal display will be described in more detail.

The timing controller 140 receives control signals, for example, a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync, for controlling the display of RGB image data R, G, and B from an external graphic controller (not shown) A main clock MCLK, a data enable signal DE, and the like. The timing controller 140 generates a plurality of first gate control signals CONT1 and a plurality of data control signals CONT2 based on the control signals and supplies the image data R, The first and second gate drivers 120 and 122 and the plurality of data control signals CONT2 after the second gate control signal CONT1 ' And the processed image data DAT to the data driver 130.

The data driver 130 sequentially receives image data DAT corresponding to a unit pixel of one row in accordance with a plurality of data control signals CONT2 provided from the timing controller 140, ), Thereby converting the video data DAT into the corresponding data voltages.

The first and second gate drivers 120 and 122 apply a gate-on voltage Von to the gate line GL according to a plurality of second gate control signals CONT1 'provided from the timing controller 140, And turns on a switching element (TFT) connected to the gate line GL.

The data driver 130 supplies each data voltage to the corresponding data line DL while a gate-on voltage is applied to one gate line GL so that one row of the switching elements TFT connected thereto is turned on. The data voltage supplied to the data line DL is applied to the corresponding unit pixel through the turned-on switching element (thin film transistor).

The liquid crystal molecules change their arrangement according to the change of the electric field generated by the pixel electrode and the common electrode, and the polarization of the light passing through the liquid crystal layer changes accordingly. Such a change in polarization is caused by a change in light transmittance by a polarizer (not shown) attached to the array substrate and the color filter substrate.

In this manner, the gate-on voltage Von is sequentially applied to all the gate lines GL during one frame to apply a data voltage to all the unit pixels. When one frame ends, the next frame starts and the state of the inverted signal applied to the data driver 130 is controlled so that the polarity of the data voltage applied to each unit pixel is opposite to the polarity of the previous frame (frame inversion). In this case, the polarity of the data voltage flowing through one data line may be changed (line inversion) or the polarity of the data voltage applied to one pixel line may be different (dot inversion) depending on the characteristics of the inversion signal even in one frame.

2 is a block diagram illustrating a timing controller according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a level shifter according to an embodiment of the present invention. FIG. FIG. 5 is a timing diagram of a data signal output from the timing controller according to one embodiment of the present invention. Referring to FIG.

2 to 5, a timing controller 140 according to an exemplary embodiment of the present invention includes a control signal generator 142, a level shifter 144, and a data processor 146.

Here, the control signal generator 142 generates a plurality of first (first) and second (second) clock signals using a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, a main clock DCLK, and a data enable signal DE, And generates a gate control signal CONT1 and a plurality of data control signals CONT2.

At this time, the plurality of data control signals CONT2 are not shown in the drawing, but the source output enable signal SOE, the source shift clock signal SSC, the source start pulse light SSPR, the source start pulse signal SSPL, The polarity control signal POL may be included. In addition, the control signal generating unit 110 may generate the power management signal DPM and the inverter left / right signal UDO although not shown in the figure.

2 and 3, the level shifter 144 includes a first gate voltage VGH, a second gate voltage VGL and a driving voltage VDD provided from the outside and an output And outputs a plurality of second gate control signals CONT1 'by converting the first gate control signal CONT1 into a constant voltage level.

The level shifter 144 increases the swing width of the plurality of first gate control signals CONT1 output from the timing controller 140 and outputs the increased swing voltage to a predetermined voltage level or more, . This is because a signal having a swing voltage of 10 V or more must be supplied to drive the thin film transistor formed on the liquid crystal panel 110.

 Referring to FIG. 4, a plurality of second gate control signals CONT1 'output through the level shifter 144 are supplied to the gate drivers 140 and 142, which direct the operations of the shift registers in the first and second gate drivers 120 and 122, The first to fourth gate clock signals CLK1 to CLK4 having different phases and inputted to the shift register in the first and second gate drivers 120 and 122 and the first and second gate clock signals CLK1 to CLK4, And first and second gate driving voltages VDD_O and VDD_E for operating a shift register in the memory cells 120 and 122, respectively.

At this time, the low level of the gate start signal VST may be, for example, -5V, and the high level may be 20V. The first to fourth gate clock signals CLK1 to CLK4 sequentially have different phases.

2 and 5, the data processor 146 receives R, G, and B data and a reset signal (not shown) provided from an external system and receives R, G, and B data And B data, and supplies R ', G', and B 'data to the data driver 130. At this time, the data processing unit 144 can generate the data polarity reversal signal REV which inverts the polarity of the video data.

The interface between the timing controller 140 and the data driver 130 may be a mini-LVDS method in which the voltage swing size is further reduced to improve current consumption and electrostatic discharge (EMI) characteristics, for example. . The image data output through the data processing unit 146 of the timing controller 140 may be a logic signal and the high level of the logic signal may be, for example, 1.8 to 2.5 V, Voltage (GND).

6 is a view illustrating a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 6, a printed circuit board 200 according to an exemplary embodiment of the present invention includes a plurality of components for operating the liquid crystal panel 110. The timing controller 140, the voltage generator 150 and the first to fourth connectors 210 to 216 are mounted on the printed circuit board 200. The first and second gate signal transmission lines 220 and 222 ), First to third data transfer wirings 230 to 234, and fourth and fifth data transfer wirings 240 and 250 are formed.

The timing controller 140 outputs a plurality of first gate control signals CONT1 from an internal control signal generator 142. The level shifter 144 includes a plurality of first gate control signals CONT1, And receives a first to a second voltages VGH and VGL and a driving voltage VDD from the driving transistor 150 and outputs a plurality of second gate control signals CONT1 '

The plurality of second gate control signals CONT1 'output from the level shifter 144 in the timing controller 140 are connected to the first and third gate signal transmission lines 220 and 222 through the first and second gate signal transmission lines 220 and 222, (210, 214), respectively. The first and third connectors 210 and 214 are connected to the first and second gate drivers 120 and 122 formed in the aspect ratio display region (not shown) on both sides of the liquid crystal panel 110, respectively.

Accordingly, the plurality of second gate control signals CONT1 'provided from the level shifter 146 of the timing controller 140 through the first and third connectors 210 and 214 are supplied to the first and second gate drivers 120 And 122, respectively. At this time, the first and second gate drivers 120 and 122 are operated by a plurality of second gate control signals CONT1 '.

Then, the first and second gate drivers 120 and 122 generate a plurality of gate-on voltages Von by the plurality of second gate control signals CONT1 'and sequentially apply the gate-on voltages Von to the plurality of gate lines GL do.

In the prior art, a plurality of gate control signals generated by the timing control unit are transmitted to a level shifter located outside the timing control unit, a plurality of gate control signals are converted into a constant voltage level at the level shifter, To the gate driver. Accordingly, the timing controller and the level shifter require a plurality of input pins for receiving a plurality of gate control signals, and a plurality of output pin assignments for outputting a plurality of gate control signals having voltage levels converted. A plurality of data lines for transmitting a plurality of gate control signals between the shifters was required.

In an embodiment of the present invention, the level shifter 144 is provided in the timing controller 140 to generate a plurality of first gate control signals CONT1 generated by the control signal generator 142, Is directly transferred to the level shifter 144. Thus, as in the prior art, a plurality of pin assignments and a plurality of wirings are not required for data transmission to a level shifter disposed outside the timing control section.

In the embodiment of the present invention, since the plurality of second gate control signals CONT1 'outputted from the level shifter 144 are directly transmitted to the first and second gate drivers 120 and 122, Similarly, in order to transfer a plurality of gate control signals from the level shifter disposed outside the timing control section to the gate driver, it is not necessary to assign a plurality of pins to the level shifter.

Therefore, in the embodiment of the present invention, the level shifter 144 is provided in the timing controller 140, so that a plurality of pins for data transmission and a plurality of wires and a level shifter Since multiple pin assignments are not required, for example, 25 pins can be reduced.

In addition, in an embodiment of the present invention, a separate data line for transmitting a plurality of gate control signals between the timing controller and the level shifter is not required, so that the number and the size of the printed circuit board can be reduced, It is possible to reduce the manufacturing cost of the apparatus.

7 is a diagram illustrating a connection relationship between a liquid crystal panel and a gate discharge circuit according to an embodiment of the present invention.

Referring to FIG. 7, a control signal generator 142 (FIG. 2) according to an embodiment of the present invention may output a gate discharge signal DIS. At this time, the gate discharge signal DIS includes a plurality of first And may be included in the gate control signal CONT1. Accordingly, the gate discharge signal DIS is also converted to a constant voltage level through a level shifter 144 (FIG. 3), and then transmitted to the first and second gate drivers 120 and 122. The gate discharge signal DIS transmitted to the first and second gate drivers 120 and 122 is applied to the gate discharge circuit 160, respectively.

The gate discharge circuit 160 is disposed between the first gate driver 120 and the plurality of gate lines GL to correspond to the plurality of gate lines GL and the first and second gate drivers 120, And the gate discharge signal DIS provided from the gate driver 122.

Here, the gate discharge signal DIS is a signal for increasing the current between the drain and the source by making the gate electrode of the thin film transistor formed on the liquid crystal panel 110 at the ground voltage (GND) The magnitude of the current between the drain and the source is smaller than when the gate-on signal Von for fully turning on is applied.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Accordingly, the invention is not to be determined by the embodiments described, but should be determined by equivalents to the claims and the appended claims.

110: liquid crystal panel 120, 122: first and second gate driver
130: Data driver 140: Timing controller
142: control signal generator 144: level shifter
146; Data processing unit 150:
160: Gate discharge circuit

Claims (10)

delete delete delete delete delete A liquid crystal panel for displaying an image;
First and second gate drivers formed on both side edge regions of the liquid crystal panel to drive gate lines formed on the liquid crystal panel;
A data driver driving a data line formed in the liquid crystal panel; And
A control signal generator for receiving a plurality of control signals from the outside to output a plurality of first gate control signals and a plurality of first data control signals for driving a plurality of gate lines and a plurality of data lines, And a level shifter for converting the plurality of first gate control signals output from the plurality of gate control signals to a constant voltage level and outputting a plurality of second gate control signals,
And a voltage generator for outputting the first to second gate voltages VGH and VGL and the driving voltage VDD to the level shifter,
The plurality of second gate control signals may include a gate start signal VST, first to fourth clock signals CLK1 to CLK4, first and second gate driving voltages VDD_O and VDD_E,
Wherein the timing control unit and the voltage generating unit are mounted on one printed circuit board. The method according to claim 6,
Wherein the timing control unit further comprises a data processing unit for receiving image data from outside and sorting and outputting the image data to be suitable for driving the liquid crystal panel. delete The method according to claim 6,
Wherein the plurality of second gate control signals further comprise a gate discharge signal. The method according to claim 6,
Wherein the plurality of second gate control signals are provided to a gate driver through a data transmission line.

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