KR101928253B1 - Method of Manufacturing Power Semiconductor Device - Google Patents

Abstract

The present invention relates to a method of manufacturing a power semiconductor device of a trench MOSFET type. By changing the ion implantation sequence and performing an RTP process, a high doping N-type source region and a P- The present invention relates to a method of manufacturing a power semiconductor device capable of securing a depth of a region and thus ensuring a stable operation region (Reverse Bias Safety Operation Area, RBSOA).

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a power semiconductor device,

[0001] The present invention relates to a power semiconductor device and a manufacturing method thereof, which improves the structure of an IEGT (Injection Enhanced Gate Transistor) to reduce the strength of an electric field (E-field) To a method of manufacturing a power semiconductor device capable of reducing energy consumption and improving switching performance.

In the field of power electronics (power electronics), there is a strong demand for miniaturization and high performance of power supply devices. In response to this demand, the power semiconductor device has been improved in performance for low loss and low noise as well as for high breakdown voltage and large current. Under such circumstances, an IEGT (Injection Enhanced Gate Transistor) having an improved IGBT (Insulated Gate Bipolar Transistor) has attracted attention as an element having a low ON voltage characteristic and capable of reducing a turn-off loss at the same time have.

Particularly, in order to secure the breakdown voltage colloctor-emitter (BV _CES) of the IEGT, the conventional techniques disclosed in recent years minimize the floating interval of the IEGT or reduce the resistivity of the Epi layer ) Value to increase the BV _CES , which is the breakdown voltage between the collector and the emitter.

However, such conventional techniques have a problem in that the floating effect is reduced to increase V _ce (sat) (Collector-Emitting Saturation voltage) or increase the thickness of the Epi layer to reduce the switching performance.

U. S. Patent No. 6,809, U.S. Patent No. 7,038,273 U.S. Patent No. 7,078,740

The present invention provides a method of manufacturing a power semiconductor device that solves the problems of the related art as described above and can maintain the BV _CES , reduce the gate capacitance, thereby reducing power consumption and providing improved switching performance do.

A method of manufacturing a power semiconductor device according to an aspect of the present invention includes: forming a plurality of trenches in a substrate; Forming a gate insulating film and a gate electrode on the trench; Implanting a P-type dopant into the substrate to form a P-type base region; Implanting a high-concentration P-type dopant into the P-type base region; Rapid annealing after the first ion implantation; Implanting a high-concentration N-type dopant on the substrate to form a high-concentration N-type source region; Depositing an interlayer insulating film on the substrate and patterning the interlayer insulating film to form an interlayer insulating film pattern; Implanting a high-concentration P-type dopant between the insulating film patterns; Forming a high concentration P-type doped region in the P-type base region; Forming an emitter electrode on the substrate in contact with the high-concentration N-type source region and the high-concentration P-type doped region; Forming a passivation insulating film on the emitter electrode; Implanting a high concentration P-type dopant on the bottom surface of the substrate to form a collector region; And forming a drain electrode on a bottom surface of the collector region.

Forming a floating region and an N-type well region in the substrate prior to forming the trench in the method of manufacturing a power semiconductor device according to an aspect of the present invention.

In the method of manufacturing a power semiconductor device according to an aspect of the present invention, the substrate includes a first epitaxial layer having a high concentration and a second epitaxial layer having a low concentration.

In the method of manufacturing a power semiconductor device according to an aspect of the present invention, the depth of the P-type doped region is formed deeper than the heavily doped N-type source region.

In the method of manufacturing a power semiconductor device according to an aspect of the present invention, the high-concentration N-type source region and the P-type doped region are formed in contact with sidewalls of the emitter electrode.

The method of manufacturing a power semiconductor device according to an aspect of the present invention further includes grinding the back surface of the substrate before forming the collector region.

In the method of manufacturing a power semiconductor device according to an aspect of the present invention, the ion implantation energy of the secondary ion implantation step is smaller than the ion implantation energy of the primary ion implantation step.

In the method of manufacturing a power semiconductor device according to an aspect of the present invention, the dose of ion implantation in the secondary ion implantation step is smaller than the dose of ion implantation in the primary ion implantation step.

A method of manufacturing a power semiconductor device according to an aspect of the present invention includes: forming a plurality of trenches in a substrate; Forming a gate insulating film and a gate electrode on the trench; Forming a P-type base region in the substrate; Forming a first high concentration P-type doped region in the P-type base region; Forming an N-type source region in the P-type base region that is smaller than the depth of the first high concentration P-type doped region; Forming an interlayer insulating film on the gate electrode; Etching the first high concentration P-type doped region; Forming an emitter electrode in contact with the high-concentration N-type source region and the high-concentration P-type doped region; Forming a passivation insulating film on the emitter electrode; Forming a collector region on the bottom surface of the substrate; And forming a drain electrode on a bottom surface of the collector region.

In the method of manufacturing a power semiconductor device according to an aspect of the present invention, rapid annealing is further performed after forming the first high concentration P-type doped region.

In the method of manufacturing a power semiconductor device according to an aspect of the present invention, the step of etching the first high concentration P-type doped region proceeds simultaneously with the step of etching the interlayer insulating film.

Etching the first high concentration P-type doped region in the method of manufacturing a power semiconductor device according to an aspect of the present invention; Thereafter, forming a second high concentration P-type doped region in the first high concentration P-type doping region.

In the method of manufacturing a power semiconductor device according to an aspect of the present invention, the ion implantation energy and the dose amount in the step of forming the second high concentration P-type doped region are determined by the ion implantation energy of the step of forming the first high concentration P- And smaller than the dose amount.

Method of manufacturing a power semiconductor device according to the present invention reduces the electric field that is concentrated in the lower region of the trench structure by forming deeper conventional contrast the floating region to surround the lower region of said trench structure without reducing the BV _CES low V _ce (sat ) And an improved switching performance.

1 is a plan view of a power semiconductor device according to an embodiment of the present invention.
2 is a view illustrating a manufacturing process of a power semiconductor device according to an embodiment of the present invention.
3 to 10 are views showing a method of manufacturing a power semiconductor device according to an embodiment of the present invention.
11 is a device simulation result of a power semiconductor device according to the general technology.
12 is a device simulation result of a power semiconductor device according to an embodiment of the present invention.
13 is a SEM photograph of a power semiconductor device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It should be understood, however, that it is not intended to be limited to the specific embodiments of the invention but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Spatially relative terms such as below, beneath, lower, above, upper, and the like facilitate the correlation between one element or elements and other elements or elements as shown in the figure Can be used for describing. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figure, an element described below (beneath) another element may be placed above or above another element. Thus, an exemplary term, lower, may include both lower and upper directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

Also, the terms "first conductivity type" and "second conductivity type" refer to opposite conductivity types such as N or P type and each embodiment described and illustrated herein includes its complementary embodiment . Hereinafter, a case in which the first conductivity type is N-type and the second conductivity type is P-type will be exemplified in the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, a method of manufacturing a power semiconductor device and a power semiconductor device manufactured in accordance with an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 12. FIG.

1 is a plan view of a power semiconductor device according to an embodiment of the present invention.

The power semiconductor device includes tens to hundreds of active cell regions 205. Concentration source region 230 and a high-concentration P-type doped region 235 in the unit active cell region 205. The high- Here, the high concentration source region 230 surrounds the high concentration P-type doped region 235. And a plurality of trench gate structures 210 surrounding the heavily doped source region 230 and the heavily doped P-type doped region 235. The trench gate structure 210 formed to surround the high-concentration P-type doped region 235 may be configured to be located in one region of the quadrant. A P-type floating region DF 220 is formed between the trench gate structure 210 and the structure. The floating region 220 is not electrically connected to the emitter electrode (electrode) or the gate electrode, and is entirely in a floating state.

The procedure of the embodiment of the present invention is shown in Fig. In step S10, a substrate including a low-concentration first epitaxial layer 250 and a high-concentration second epitaxial layer 252 is prepared. The second epilayer is used as a field stop layer. The first epi layer may be used as a drift region. In step S20, a floating region and an N-type well region are formed in the first epi-layer. In step S30, a trench structure is formed and a gate insulating film and a gate electrode are formed in the trench structure. In step S40, a P-type base region is formed on the substrate and the first high temperature annealing is performed for dopant diffusion. In step S50, the P + doped region is formed by the primary P + ion implantation and the RTP fast annealing method. In step S60, an N + type ion implantation is performed to form an N type source region. In step S70, an interlayer insulating film pattern is formed, an interlayer insulating film is deposited, and contact holes are etched to form an interlayer insulating film pattern. In step S80, the P + doping region is finally completed by performing the secondary P + ion implantation. Then, a second high temperature annealing process is further performed after the second P + ion implantation. In step S80, an emitter electrode and a passivation insulating layer are formed. In step S90, a back side grinding operation is performed on the rear surface of the substrate to remove a portion of the substrate until the N + field stop layer is exposed. And a P + collector layer 257 is formed. Then, the drain electrode 259 is deposited to complete the power semiconductor device.

In other words, in the method of manufacturing a power semiconductor device, S30 is a step of forming a plurality of trenches in a substrate, and a gate insulating film and a gate electrode are formed in the trenches. Step S40 is a step of forming a P-type base region on the substrate. Step S50 is a step of forming a first high concentration P-type doped region in the P-type base region. And further comprising rapid annealing after forming the first high concentration P-type doped region. S60 is a step of forming an N-type source region in the P-type base region which is smaller than the depth of the first high concentration P-type doping region. Step S70 is a step of etching the first high concentration P-type doped region while forming an interlayer insulating film pattern on the gate electrode. The etching of the first heavily doped P-type doped region takes place near some of the surfaces and occurs simultaneously while patterning the interlayer insulating film.

S80 is a step of forming a second high concentration P-type doped region in the first high concentration P-type doping region. Here, the ion implantation energy and the dose amount in the step of forming the second high concentration P-type doped region are smaller than the ion implantation energy and the dose amount in the step of forming the first high concentration P-type doped region.

S90 is a step of forming an emitter electrode in contact with the high-concentration N-type source region and the high-concentration P-type doped region, and forming a passivation insulating film on the emitter electrode. S100 is a step of forming a collector region on the bottom surface of the substrate after backside grinding and forming a drain electrode on the bottom side of the collector region.

3, the substrate 100 includes a first epitaxial layer 252 doped with a high concentration N-type and a second epitaxial layer 250 doped with a low concentration N-type dopant on a base substrate 254 do. And two epilayers 252 and 250 having different concentrations. In this case, the first epitaxial layer 252 having a high impurity concentration operates as a field stop layer (or a buffer layer, see FIGS. 9 and 255). The second epilayer 250 operates as a drift region 250 to be described later.

The thickness of the second epi-layer 250 may be 90 to 100 [mu] m. The reason for forming the second epi layer 250 to be thick is to separate the floating region 220 and the first epi layer 252 from each other by a predetermined distance, thereby forming the first epi layer 252 ) And the base region 240 or the floating region 210 to some extent to increase the breakdown voltage.

4, a P-type floating region DF 220, a LOCOS isolation film 260, and an N-type well region 245 are formed on the substrate.

Specifically, a floating mask pattern is formed on the substrate so as to be spaced apart at regular intervals. Then, the floating region 220 is formed by ion implantation into the substrate using a P-type dopant. As the P-type dopant, boron (B) or BF2 may be used. In an embodiment applicable to the present invention, the floating region 220 may be formed to have a depth of about 8-9 um. In terms of ensuring the breakdown voltage, the depth of the floating region 220 may be about 8 to 10% of the thickness of the N-type drift region 250. The floating region 220 may be formed to a depth greater than the well region 245.

Then, a LOCOS region 260 is formed on the substrate 100. So as to separate a plurality of active cell regions. An N-type well region 245 may be formed between the floating regions 220. The well region 245 may be formed to have a thickness of about 6-7 um from the top surface of the substrate.

The N-type well region 245 serves to suppress the movement of the hole carrier from the drain metal layer (electrode 259) to the high concentration source region 230. For this, the N-type well region 245 may be formed to have an impurity concentration higher than that of the N-type drift region 240. Accordingly, when the hole carriers are accumulated in the drift region 240, the injection of electrons is increased to cause more conductivity modulation, resulting in a lower resistance. Therefore, the electron carrier can easily move to the drain region even at a small voltage, so that a low Vce (sat) characteristic can be obtained.

Next, as shown in FIG. 5, a plurality of trenches 211, 212, 213, and 214 are formed at a predetermined depth from the upper surface of the substrate. The plurality of trenches 211, 212, 213, and 214 are formed in contact with the side surfaces of the floating region 220 and the well region 245, respectively. For convenience of explanation, the first trench 211, the second trench 212, the third trench 213, and the fourth trench 214 are respectively referred to as left to right in the drawing. The first to fourth trench gates 211, 212, 213 and 214 may be formed through an etching process on the semiconductor substrate, and they may be formed to have the same depth through the same process.

A gate insulating film 216 and a gate electrode 215 are formed in the respective trenches 211, 212, 213, and 214, respectively. The gate electrode 216 is formed by depositing and patterning poly-silicon, which is a conductive material, to form the gate electrode 216.

5, a photomask pattern (not shown) is formed on the substrate, and a P-type dopant is selectively implanted into the N-type well region 245 using the mask pattern to form a P- (240). The area of the N-type well region 245 is reduced. The annealing process can be performed at 700-900 ^° C at high temperature to diffuse the P-type base region downward into the substrate.

As shown in FIG. 6, a P + mask pattern 120 is formed on the substrate to form a P + doped region 235. A P + mask pattern 120 is formed on the gate electrode 215 to expose the substrate. Then, the first P + doped region 235 is formed by selectively ion-implanting (285) a P-type dopant selectively on the substrate using the mask pattern 120. After forming the first P + doped region 235, a rapid thermal process (RTP) is performed to activate the P + doped region. Boron can be used as a dopant. RTP can proceed from 850 to 1200 C in 10 to 120 seconds. Boron as a dopant 100 - can be implanted at a dose of between 200 KeV ion implantation energy, 1E14-1E16 / cm ^2.

As shown in FIG. 7, an N + source region 230 is formed. An N + photomask pattern (not shown) is formed to form an N + source region 230, and an N type dopant is selectively implanted into the substrate to form an N + doped region 230. The N-type source region is smaller than the depth of the first high concentration P-type doped region 235.

After the N + photo (NSD), N + ion implantation and P + photo (PSD) implantation are performed, P + ion implantation is performed and an annealing process is performed to form a heavily doped source region and a P type doped region. Simultaneous activation is achieved by the annealing process, in which the N type dopant diffuses to the P type doping region a lot and the P + doping region can be reduced. In this case, a sufficient operation area (SOA) is not secured. However, as in the embodiment of the present invention, rapid thermal annealing (RTP) is performed immediately after P + ion implantation and N + ion implantation is performed to suppress the diffusion of the N-type dopant into the P + -doped region. By doing so, the P-type doped region is secured to some extent. A sufficient operation area can be ensured.

As shown in FIG. 8, a thick interlayer insulating layer 270 is deposited on the upper surface of the substrate by a CVD method. An insulating film 270 of silicon oxide series is used as an interlayer insulating film. The interlayer insulating layer 270 may be formed of two layers. The first layer may be used as a gate electrode protective layer such as an HLD oxide layer, and the second layer may be formed of a PSG or BPSG material. The PSG or BPSG material has good flow characteristics, and the interlayer insulating film can be planarized. This is because, in order to form the contact mask pattern well, the interlayer insulating film must be formed flat. Then, a contact mask pattern 140 is formed on the interlayer insulating film. The contact etching process for etching the interlayer insulating film is performed using the contact mask pattern 140 as a mask.

As shown in FIG. 9, after the contact etching process, an interlayer insulating film pattern 270 is formed. Then, the contact mask pattern 140 is removed. The interlayer insulating film is etched by an interlayer insulating film etching process, and the substrate is exposed. The exposed substrate has a P + doped region 235 at the top, and some regions of the P doped region are also lost by the etching process. That is, the first high concentration P-type doped region 235 is etched. The entire thickness of the first high concentration P + doped region 235 becomes thin, and the area occupied by the first high concentration P + doped region 235 decreases. This reduces the P-type dopant concentration in the P + doped region 235.

In order to restore this to its original state, secondary P + ion implantation 295 is performed, as shown in FIG. Supplementing the reduced amount of P-type dopant through the second P + ion implant 295. As BF dopant to less than 100 KeV it can be implanted at a dose between 1E14-1E16 / cm ^2. The dose of the secondary P + ion implantation (295) and the ion implantation energy are smaller than those of the first ion implantation (285). Therefore, it can be seen that the second high concentration P + doping region is formed in the first high concentration P + doping region by performing the secondary P + ion implantation (295).

After the second P + ion implantation, annealing is performed at a temperature lower than 900 ^° C. This annealing serves to mitigate etch damage caused by the contact etch process. Diffusion of N + dopants is negligible at temperatures below 900 ^° C.

As shown in FIG. 10, an emitter electrode 280 is formed by depositing an emitter metal on a dielectric film pattern and a substrate using a metal material such as aluminum or copper. The emitter electrode 280 and the gate electrode 215 are electrically separated from each other by the insulating film pattern 270. The N + source region 230 and the P + doped region 235 are electrically connected to the emitter electrode 280.

Then, a passivation insulating film 290 is formed to prevent water or the like from penetrating after forming the emitter electrode. Then, a back side grinding process is performed on the back side of the substrate. Thereby removing the base substrate 254. And proceeds until the first epi layer 252 is exposed when removing the base substrate. The remaining first epitaxial layer 252 becomes the N + field stop layer 255. Thus, there is an advantage that a separate ion implantation process for forming the N + field stop layer 255 is not necessary.

The field stop layer 255 prevents the electric field formed from the emitter electrode from further extending to the P + collector layer 257. In the absence of the field stop layer 255, the thickness of the drift region 250 must be made very thick, in which case the resistance is increased by the drift region 250 doped with a low concentration. In addition, if the field stop layer 255 is not present, the electric field can be formed deeper downward and the PN diode can not be formed, so that the IGBT function used for a high current can not be exhibited properly.

And a P + collector layer 257 is formed. Then, the drain electrode 259 is deposited to complete the power semiconductor device.

11 and 12 are device simulation results shown to explain the difference between the general technology and the present invention. Fig. 11 shows a case of being manufactured in a general technology manner, and Fig. 12 corresponds to an embodiment of the present invention. As shown in FIG. 11, the arrows shown in FIG. 11 are formed to be deeper than the P + doped region 235 than the N + source region 230. That is, the P + doped region 235 is formed to be shallower. Also, it can be seen that most of the emitter electrode side 280a contacts the N + source region 230 only. Due to the N / P doze difference, the boron is pushed out due to lateral diffusion of phosphorus (P) which is an N-type dopant to the bottom of the emitter contact. Therefore, it is difficult to obtain a stable operation area (Reverse Bias Safety Operation Area, hereinafter referred to as RBSOA) in the reverse bias state because of being vulnerable to dynamic latch-up. The RBSOA parameter is to test stable operating conditions in the turn-off state in the IGBT device.

However, in the present invention, as shown in FIG. 12, the N + source region 230 is formed shallower than the P + doped region 235. The desired P + doped region 235 is secured. The N + source region 230 and the P + doped region 235 contact the emitter electrode side surface 285a at the same time. After the activation of boron (B), which is a P-type dopant, phosphorus (P), which is an N-type dopant, has a stable P + form. Thus, the dynamic latch-up is improved. 5 times the RBSOA level can be secured. SOA test results showed good results under all evaluation conditions and no significant difference for various RTP conditions.

13 is a cross-sectional SEM photograph of the power semiconductor device manufactured by the embodiment of the present invention. As shown in the figure, the N + source region and P + doping region are clearly shown. It can be seen that the SEM photographs are also closely matched with the device simulation results.

The method of manufacturing a power semiconductor device according to the present invention can provide a method of manufacturing a power semiconductor device capable of securing a P + doped region with a desired design and providing a wide RBSOA window through the above technical arrangement have.

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

100: substrate 211, 212, 213, 214: trench structure
215: trench gate electrode, 216: gate insulating film
220: floating region 230: high concentration source region
235: heavily doped P-doped region 240: base layer
245: N-type well region 250: first epitaxial layer (or drift region)
252: second epilayer, 255: field stop layer
259: drain electrode 257: collector layer
260: LOCOS oxide film 270: Interlayer insulating film
280: Emitter electrode 285: Primary P + ion implantation
290: passivation insulating film 295: secondary P + ion implantation

Claims (13)

Forming a plurality of trenches in the substrate;
Forming a gate insulating film and a trench gate electrode in the trench;
Forming a P-type base region in the substrate;
Forming a first P + doped region between the trench gate electrodes;
After the forming the first P + doped region, rapid annealing;
Forming an N + source region between the trench gate electrode and the first P + doped region;
Depositing and patterning an interlayer insulating layer on the substrate to expose the first P + doped region;
Forming a second P + doped region in the exposed first P + doped region; And
And forming an emitter electrode on the substrate in contact with the N + source region and the second P + doped region
Wherein forming the N + source region is followed by forming the trench gate electrode and the first P + doped region.
2. The method of claim 1, wherein, prior to forming the trench,
And forming a floating region and an N-type well region in the substrate.
The method according to claim 1,
Wherein the substrate comprises a first epitaxial layer of high concentration and a second epitaxial layer of low concentration.
The method according to claim 1,
Wherein the depth of the first P + doped region is deeper than the N + source region.
The method according to claim 1,
Wherein the emitter electrode has a side surface and a bottom surface in contact with the substrate, and the N + source region and the second P + doped region are in contact with a side surface of the emitter electrode.
The method according to claim 1,
Forming a passivation insulating film on the emitter electrode; And
Implanting a high-concentration P-type dopant on the bottom surface of the substrate to form a collector region,
And grinding the backside of the substrate prior to forming the collector region.
The method according to claim 1,
Wherein the ion implantation energy of the step of forming the second P + doped region is smaller than the ion implantation energy of the step of forming the first P + doped region.
The method according to claim 1,
And the amount of ion implantation in the step of forming the second P + doping region is smaller than the amount of ion implantation in the step of forming the first P + doping region.
Forming a plurality of trenches in the substrate;
Forming a gate insulating film and a trench gate electrode in the trench;
Forming a P-type base region in the substrate;
Forming a first P + doped region between the trench gate electrodes;
Rapid annealing after forming the first P + doped region;
Forming an N + source region between the trench gate electrode and the first P + doped region;
Forming an interlayer insulating film pattern on the trench gate electrode;
Etching a portion of the first P + doped region;
Forming a second P + doped region in the etched first P + doped region;
Forming an emitter electrode in contact with the N + source region and the second P + doped region; And
And forming a passivation insulating film on the emitter electrode,
Wherein forming the N + source region is performed after forming the trench gate electrode and the first P + doped region.
10. The method of claim 9,
Further comprising: after the forming the second P + doped region, high temperature annealing.
10. The method of claim 9,
Etching the first P + doped region;
Wherein the step of forming the interlayer insulating film pattern is performed simultaneously with the step of forming the interlayer insulating film pattern.
10. The method of claim 9,
Wherein a side surface and a bottom surface of the emitter electrode are formed in contact with the substrate, and the second P + doping region and the N + source region are in contact with a side surface of the emitter electrode.
13. The method of claim 12,
Wherein the ion implantation energy and the dose amount of the step of forming the second P + doped region are smaller than the ion implantation energy and the dose amount of the step of forming the first P + doped region.

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