KR101900206B1 - An apparatus and method for adaptively controlling the brightness and color of led electronic board for the compensation of the brightness imbalance - Google Patents

Abstract

The present invention relates to a technique capable of correcting a luminance imbalance between pixels by increasing luminance in proportion to a deteriorated luminance value when an intrinsic luminance value is lowered by a deterioration phenomenon due to the electro-optical characteristic of an LED device in an LED display board and thus the luminance value or image quality is lowered due to the luminance imbalance. That is, the present invention relates to a luminance and color control technique to which an adaptive luminance implementation bit and a pulse are applied for correcting a luminance unbalance caused by a deterioration phenomenon in the display board and a method thereof, in which an image data composed of each 8-bit of red, green, and blue is converted into 12-bit to 20-bit luminance data, the luminance implementation bit and pulse number are adaptively changed in the LED display board by using the relationship that for the luminance implementation bit, when the number of bits is increased, the luminance value is increased and when the number of bits is decreased, the luminance value is decreased, and the characteristic of the quality of the image that by the number of basic pulses of the luminance implementation, when the number of pulses is increased, the quality of the image is increased and the luminance is decreased, and when the number of pulses is decreased, the quality of the image is decreased, but the luminance is increased, whereby the lighting ratio is increased according to the degree of the deterioration phenomenon and unevenness of the luminance is reduced, thereby prolonging the life of the LED display board.

Description

FIELD OF THE INVENTION [0001] The present invention relates to an adaptive brightness and color control apparatus and a control method for a luminance unbalance correction of an LED electric sign board,

[0001] The present invention relates to a brightness and color control apparatus and a control method for correcting a luminance unbalance according to progress of a deterioration phenomenon of an LED electric sign board, and more particularly, And more particularly, to an apparatus and method for controlling brightness and color of an LED which can reduce luminance unevenness.

An LED electric signboard for generating image signals and control signals for driving the LED pixel matrix (LED Pixel Matrix, LPM module) of the LED electric signboard by receiving image data from the outside is mainly used as an outdoor billboard. The LED display board is manufactured at a price of several million won to several billions of won. If it is used for 2 ~ 3 years, deterioration phenomenon occurs in each pixel constituting the screen due to a rise in junction temperature, The intrinsic luminance value of the LED display panel is reduced by about 20 to 30%, and when more than 5 to 7 years have elapsed, the luminance is decreased by 50% or more and it is judged that the normal life is over.

Also, the deterioration phenomenon causes a luminance unbalance (difference) in each pixel. The LED electric signboard can be recognized when the luminance imbalance between pixels is about 6% or more at the normal brightness, but even when the brightness is low, the luminance difference of about 1% can be easily recognized. Therefore, when the LED electronic signboard is used for a long time, a difference in luminance imbalance due to the decrease in brightness becomes more conspicuous, resulting in inconvenience to the viewer. Considering that hundreds of thousands of LED elements are installed on one electric sign board, shortening the use time of the electric signboard due to the luminance unevenness causes a great economic loss.

On the other hand, the luminance characteristic of the LED display board depends on the number of luminance implementation bits applied to the LED pixel module (LPM) and the luminance implementation basic pulse. When the number of luminance implementation bits increases, the luminance value increases. When the number of bits decreases, the luminance value decreases. In addition, the quality of the displayed image is determined by the basic number of pulses for implementing the brightness. If the number of basic pulses for implementing the brightness is increased, the characteristic of the monitoring curve that the human can feel is improved, and the quality of the image is improved. The brightness of the image data having the high brightness implementation value is increased and the brightness of the image data having the low brightness implementation value is decreased.

As the deterioration of the LED progresses, the image quality of the LED display board becomes seriously uneven in image data of low bit. However, in order to solve this problem, it is impossible to increase the brightness implementation bit indefinitely because a flicker phenomenon occurs as the luminance implementation bit is increased. In addition, if the number of basic pulses for realizing the luminance is increased, the pulse width is shortened. Therefore, there is a problem in the output current response time due to the electrical characteristics of the driving IC, and the basic pulse number can not be arbitrarily increased. For this reason, a display control device that controls an LED display board has been designed and manufactured with a luminance implementation bit of 13 bits and a basic luminance implementation number of 256 or less.

Display device and luminance correction method of display device (Korean Patent Laid-Open Publication No. 10-2010-0021094)

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an LED display panel which is fabricated and installed in a conventional manner or an LED display panel which is newly designed and manufactured, A technique capable of correcting the luminance unbalance between pixels by adaptively increasing the luminance to the decreased luminance value, that is, the adaptive luminance using the luminance implementation bit and the pulse for correcting the luminance unbalance caused by the deterioration phenomenon in the LED electric sign board, A color control device and a method thereof are provided.

To this end, according to a preferred embodiment of the present invention, there is provided an LED display panel for receiving video data from outside and generating an image signal and a control signal for driving an LED pixel matrix ('LPM') module of the LED display panel An adaptive luminance and color control apparatus for luminance unbalance correction,

A memory for storing 8-bit image data and control signals of red (R), green (G), and blue (B); A memory control signal and a luminance correction operation control signal for controlling the arithmetic operation unit to read the 8-bit image data stored in the memory and perform a luminance correction operation on the image data, A control device for generating a control signal and generating an LPM module timing and signal generation control signal; A variable pulse generator for generating a variable pulse in accordance with the variable pulse generation control signal received from the control device; And a control circuit for receiving the variable pulse generated from the variable pulse generator and outputting the luminance implementation bit and the luminance of the 8-bit image data based on the memory address signal, the memory control signal, The arithmetic device performing a luminance correction operation with respect to an implementation basic pulse number and generating a luminance implementation bit value converted according to the luminance correction operation; And an LPM module control device for controlling the timing and signal generation of the LPM module, the LPM module control device receiving the variable pulse generated from the variable pulse generator, receiving the converted circuit implementation bit value from the calculation device, An OE (Out Enable) signal, a ST (Strobe) signal, and a scan line select signal according to the timing of the LPM module and the signal generation control signal, Module, and sending the control signal to the LPM module in synchronization with the converted luminance implementation bit value, wherein the computing device is operable to control the luminance of the LPM module, By adjusting the number of luminance implementation bits and the number of luminance implementation pulses for the LPM module by performing a luminance correction operation according to the degree of damage, Provided is an adaptive luminance and color control apparatus for reducing the luminance unbalance on the M module and correcting the luminance unbalance of the LED electric billboard.

Here, the luminance and color control apparatus reconfigures the sequence of bit values having a low luminance implementation pulse number in a time period during which a residual image occurs, thereby increasing the luminance.

Also, the arithmetic unit maps the luminance implementation basic pulse number, the shift-latch number, and the corresponding bit value of the LPM module, obtains the maximum luminance implementation value Bs obtained by adding all the bit values mapped, The luminance implementation bit for each luminance implementation value is mapped within a range where the luminance implementation value of the module is between 0 and Bs. If 0 is present in the bits expressing the bit value mapped to the Bs, Generating a modified bitmap table according to the logical expression, generating a luminance implementation bit value converted in accordance with the modified bitmap table, And applying the corrected number of luminance implementation bits and the number of luminance implementation pulses according to the converted luminance implementation bit value to the LPM module to reduce the luminance unbalance due to deterioration of the LPM module.

According to another aspect of the present invention, there is provided a method of variably generating and controlling a luminance implementation bit and a luminance implementation pulse of an image signal for driving an LED pixel matrix (LPM) module in a display controller of an LED electric sign board,

Setting a luminance implementation bit value according to a luminance implementation basic pulse number and a shift-latch number; Mapping the luminance implementation basic pulse number, the shift-latch number and the corresponding bit value; Adding all bit values to obtain a maximum luminance implementation value Bs; Mapping luminance implementation bits for each luminance implementation value within a range of luminance implementation values from 0 to Bs;

Mapping a modified bit value to each luminance implementation value if 0 is present in the bit value mapped to the maximum luminance implementation value; Generating a modified logical expression for outputting the modified bit value; Generating a modified bit mapping table according to the logical expression; And generating a luminance implementation bit value converted in accordance with the modified bit mapping table.

After the step of generating the modified bit mapping table, the order of the shift-latch count of the bit value having the low luminance implementation pulse number in the bit mapping table is rearranged to the time when the afterimage occurs, And changing the order of the number of times.

Meanwhile, an LED display controller for controlling an LED display having a plurality of LPM modules constituted by LED pixel matrix according to a preferred embodiment of the present invention,

A receiving unit for receiving an external video signal and converting each 8-bit video data of red (R), green (G) and blue (B) into a clock signal, a vertical synchronizing signal, a horizontal synchronizing signal and a DE signal;

A memory for storing 8-bit image data and control signals of red (R), green (G), and blue (B);

A memory control signal and a luminance correction operation control signal for controlling the arithmetic unit to read the image data stored in the memory and perform a luminance correction operation on the image data, And generates an LPM module timing and signal generation control signal;

A variable pulse generator for generating a variable pulse in accordance with the variable pulse generation control signal received from the control device;

And a control circuit for receiving the variable pulse generated from the variable pulse generator and outputting a luminance implementation bit and a luminance control signal to the 8-bit image data based on the memory address signal, the memory control signal, An arithmetic and logic unit for performing a luminance correction operation with respect to an implementation basic pulse number and generating a luminance implementation bit value according to a luminance correction operation; And

An LPM module control apparatus for controlling a timing and a signal generation of an LPM module, the LPM module control apparatus comprising: a variable pulse generator for receiving a variable pulse generated from the variable pulse generator and receiving the converted circuit implementation bit value from the processor; OE (Out Enable) signal, a ST (Strobe) signal, and a scan line select signal according to the LPM module standard on the basis of the LPM module timing and signal generation control signal and outputs the control signal to the LPM module And transmits the control signals to the LPM module by synchronizing the converted luminance implementation bit value with the control signals,

The arithmetic unit performs a luminance correction operation in accordance with the luminance impairment caused by deterioration of the LPM module to adjust the number of luminance implementation bits and the number of luminance implementation pulses for the LPM module so that the luminance on the LPM module The present invention provides an LED display control apparatus that reduces an imbalance.

Here, the arithmetic unit can increase the brightness by reconstructing the shift-latch sequence of the bit value having the low luminance implementation pulse number to the time zone in which the afterimage phenomenon occurs.

The arithmetic unit maps the luminance implementation basic pulse number, the shift-latch number, and the corresponding bit value of the LPM module, obtains the maximum luminance implementation value Bs obtained by adding all the bit values mapped, The luminance implementation bit for each luminance implementation value is mapped within a range where the luminance implementation value is between 0 and Bs, and if 0 exists in the bits representing the bit value mapped to the Bs, Generating a modified bitmap table according to the logical expression expression, generating a luminance implementation bit value converted in accordance with the modified bitmapping table, The number of luminance implementation bits and the number of luminance implementation pulses according to the luminance implementation bit value may be applied to the LPM module to reduce the luminance unbalance due to deterioration of the LPM module.

As described above, according to the present invention, the luminance implementation bit value, the total shift-latch frequency, and the luminance implementation basic pulse number of the image data to be transmitted to the LPM module can be variably generated. That is, the luminance implementation bit of the image data is changed from 12 bits to 20 bits, and the basic number of luminance implementation pulses is variably changed within a range of 2 ⁿ (5? ^N ? 12) to increase or decrease the luminance value of the LED display . In such a configuration, when a luminance unbalance occurs in the LED display panel due to deterioration or damage of some of the LED dot lamps of the LED display panel, the luminance implementation bit and the luminance implementation pulse are variably changed to increase the brightness of the entire LED display panel, Thereby compensating for the luminance of the dot lamp, thereby solving the problem of the total luminance unbalance.

As the luminance implementation bit value increases, the lighting ratio of the LED display board increases. Also, when the basic number of luminance implementation pulses increases, the image quality improves but the lighting ratio decreases. When the basic number of luminance implementation pulses decreases, the image quality decreases, The number of luminance implementation bits and the number of basic pulses are adjusted according to the degree of the deterioration phenomenon and the number of the basic number of pulses is adjusted according to the degree of the deterioration phenomenon, It is possible to reduce the luminance unbalance problem. As a result, it is possible to extend the service life of the LED electronic sign board.

In addition, the brightness and color control method of the LED display panel according to the present invention can be applied not only to a newly manufactured LED display panel but also to a display control device of a LED display panel manufactured by the existing method, without adding new hardware or changing it.

1 is a block diagram schematically showing a configuration of an LED display control device.
2 is a flow chart illustrating a process for generating luminance and color in the luminance and color control apparatus.

In order to achieve the above object, the display control apparatus of the present invention includes a receiving unit 100 and a luminance and color control processing apparatus 200, and will be described with reference to FIG.

The LED display control device includes a receiver 100 for receiving a DVI / HDMI signal from the outside, and a luminance and color control processor 200 for generating various video signals and control signals capable of driving the LPM module 300 do. One LED display control device can be installed for each screen module.

 The receiver 100 converts a video signal transmitted through a TMDS (Transition Minimized Differential Signaling) signal into a digital video signal in accordance with the DVI standard communication standard and inputs the converted signal to the luminance and color control processor 200 .

The LPM module 300 includes a plurality of LPM modules arranged horizontally and vertically, each of which is composed of red, green, and blue LEDs (or OLEDs) screen modules are arranged to constitute an LED display screen.

The luminance and color control processing apparatus 200 receives the DVI / HDMI signals received by the receiving unit 100 as video signals of red, green and blue as digital video signals, a clock signal, a horizontal synchronizing signal, a vertical synchronizing signal, a data enable ) Signal, and performs various processing processes using the converted video signal, that is, operations such as luminance implementation bit, pulse generation, and gamma processing The control unit 210 includes an RGB storage unit 220, an arithmetic unit 230, a variable pulse generator 240, and an LPM module control unit 250 for generating timing and signals of the LPM module. The luminance and color control processing device 200 may be implemented in the form of a single FPGA (Field Programmable Gate Array).

The control device 210 transmits 8-bit video data of red, green, and blue, which are digital video signals, to the RGB storage device (or the like) by using the shift clock signal, the vertical synchronization signal, the horizontal synchronization signal, and the DE signal input from the receiver 100 220 or a memory address signal and a memory control signal capable of reading the image data stored in the RGB memory device 220 and transferring the image data to the arithmetic unit 230 to generate a variable luminance implementation bit, Generates an operation control signal capable of controlling the arithmetic unit 230 to perform operations such as correction, brightness adjustment, and the like, generates a variable pulse generation control signal for controlling the variable pulse generator 240, 250) for generating the LPM module timing and signal generation control signal.

The RGB storage device 220 is a memory capable of temporarily storing 8-bit image data of red, green, and blue inputted from the receiver 100, and is configured to store image data of even-numbered frames and image data of odd- . When storing image data of an even-numbered frame outputted from a PC or a DVD player, such a storage method transmits image data of odd-numbered frames to the LPM module through the arithmetic unit 230 (gamma correction and brightness adjustment) The image data of the even-numbered frame is transmitted to the LPM module via the arithmetic unit 230, thereby reducing the flicker phenomenon and improving the luminance characteristic.

The arithmetic unit 230 receives the control signal generated by the control unit 210 and the variable pulse generated from the variable pulse generator 240 and generates a bit value for each 8 bit image data value of red, An adjustment constant is multiplied and a gamma value is adjusted to convert an 8-bit input bit into a 12-bit to 20-bit image data value. Operations performed by the arithmetic unit 230 will be described later in detail with reference to FIG.

The variable pulse generator 240 receives the variable pulse generation control signal from the controller 210 and generates 32, 64, 128, 256, 512, ..., , 4096, etc., to the arithmetic operation unit 230 and the LPM module control unit 250, respectively.

The LPM module control device 250 receives the LPM module timing and signal generation control signal generated from the control device 210 and the variable pulse generated from the variable pulse generator 240 and increases the luminance in the calculation device 230 An OE (Out Enable) signal, an ST (Strobe) signal, a scan line selection signal, and a scan line selection signal in accordance with the specifications of the LPM module so as to transmit image data of 12 to 20 bits, Generates control signals such as signals L0, L1, L2 and L3 and transmits them to the LPM module 300 to generate and transmit respective red, green and blue image data to be displayed in synchronization with the control signals.

The control signal includes a shift clock signal, an OE signal, an ST signal, and a scan line selection signal that conform to the specifications of the LPM module 300. The shift clock signal shifts image data represented by the luminance implementation bit values of red, green, and blue to the LPM module 300 by a shift clock, and the shifted serial image data is shifted by the ST signal Is latched in a register (latch register), and the latched data turns on or blinks the corresponding LED pixel. In this case, the OE signal refers to a luminance implementation pulse generated by the entire shift-latch sequence described above. The OE signal is output to drive the latched data to the corresponding LED pixel. The brightness of the corresponding LED pixel can be controlled by performing ON / OFF. The LPM module control unit 250 synchronizes the luminance implementation bit values converted from 12 bits to 20 bits to the LPM module 300 in synchronization with the luminance implementation pulse OE generated by the shift- do.

Hereinafter, the operation of the arithmetic operation unit 230 for generating the converted luminance implementation bit value will be described in more detail.

Implementation of Brightness for Determining Brightness of LED Signboard and Implementation of Brightness for Determining Image Quality First, regarding generation of basic pulse number, 13 bits of luminance implementation bit used in the conventional LED display board and 256 bits of luminance implementation basic pulse Table 1 shows the relationship between the value and the shift-latch count.

The relationship between the number of basic implementation pulses of luminance of 256, the corresponding bit value, and the number of shift-latches Bit order 0 One 2 3 4 5 6 7 8 9 10 11 12 Bit value One 2 4 8 16 32 64 128 256 512 1024 2048 4096 Shift - Number of Latches 0 One 2 3 4 5 6 7 7 9 10 11 ... 14 15 ... 22 23 ... 38 Implement brightness
Number of pulses One 2 4 8 16 32 64 128 256 256 256 256 ... 256 256 ... 256 256 ... 256

The luminance implementation bits of each red, blue, and green image data on the LED display board are implemented with 13 bits, which means that the luminance implementation value capable of representing the image has a value of 0 to 8191. [ For example, the luminance implementation value 8191 means that the input image data value 255 of 8 bits is transformed into the value 8191 which is the sum of the 13-bit values through the transformation of equation (1). Equation (1) is as follows.

f (x) = gain x (scale x X) ^gamma 占offset Equation (1)

f (x) = luminance implementation value

X = 8-bit image data value of red, green, and blue respectively

       gain = contrast,

       offset = luminance,

scale = Bit value adjustment constant

this In order to transmit the 13-bit luminance implementation value to the LPM module 300 and display it as an image, it is necessary to serially input 1 bit by one bit. However, for each corresponding bit, that is, the 0th bit is 0 or 1, the 1st bit is 0 or 2, the 3rd bit is 0 or 4, ... , The seventh bit is 0 or 128, ... , And the 12th bit has a value of 0 or 4096. Thus, since the corresponding bits have different values, the shift-latch can not be performed the same number of times. Therefore, the basic pulse is applied to each corresponding bit value in order to implement luminance by such a problem. When the number of basic pulses for luminance implementation is 256, it is referred to as a unit. The 0th bit is 1/256 of the pulse period of 1 unit, the first bit is 2/256, 3 Th bit is 4/256 of the pulse period of one unit, ... , The eighth bit uses 256/256, that is, 1 unit of 256 pulse periods, the 9th bit is 2 units, the 10th bit is 4 units, ... , And the twelfth bit performs a shift-latch operation using a period of 32 units.

According to Table 1, in order to calculate the lighting time of the LED for the luminance implementation bit 13 bits, the luminance basic pulse number 256, and the shift-latch frequency 39 times, the duty cycle of the LED screen module is 1/4, Table 2 shows the method of calculating the lighting time of the LED on the assumption that the frequency of the vertical synchronization signal Vsync input from the player is 60 Hz, that is, the refresh rate is 60 Hz.

Calculation of LED lighting rate using Table 1 (1/4 duty cycle) division Calculation contents One scanning line driving time (Lt) Vertical synchronization time (Vt): 1/60 (sec) = 16.67mS
Vt Number of repetitions per hour (O): 3 times
Number of times of repetition (O) of one repetition - Number of times of latch (S)
: 13 times
Duty cycle (Ds): 4 (at 1/4)

=

= 106.84uSLt =

=

= 106.84 uS One pulse width (W) for luminance implementation Basic implementation number of luminance (Pn): 256
Shift per scan line - Number of latches (Sn): 12 times W =

=

= 34.78 [ns] Vt 1 line total drive time [Ns] One scanning line driving time (Lt) x
Vt Number of repetitions per hour (O) x
Number of times of repetition (O) of one repetition - Number of times of latch (S) Ns = Lt x O x S
= 106.84 [uS] x 3 x 13
= 4.1667 [mS] Vt 1 line total lighting time per hour [Ls] Total number of pulses to implement brightness (Ps) x
One pulse width (W) for luminance implementation x
Number of times of repetition (O) of one repetition - Number of times of latch (S) Ls = Ps x W x S
= 8192 x 34.78 [nS] x 13
= 3.70393088 [mS] 1 line total forced OFF time (Kt) Scan-line switching time to eliminate afterimage LED OFF time (Kt): S × O × X [uS]
- X = LED forced OFF time (uS) Kt = S x O x X [uS]
= 13 x 3 x 15.432us
= 601.848 [uS] Vt Actual lighting time for one line per hour [Ks] Vt 1 line total lighting time per hour [Ls] -
Forced OFF Time (Kt) Ks = 3703.93088-601.848
= 3102.08288 [uS] 1 line lighting ratio for color expression [Lon]  Vt 1 line actual lighting time per hour [Ks] / Vt 1 line total driving time [Ns] × 100 [%] Lon =

= 74.45 [%]

 Assuming that the luminance implementation bit is 13 bits and the luminance implementation basic pulse number is 256, in order to realize this, it is found that the number of shift-latches per bit for the corresponding bit value is 39 as shown in Table 2 below.

As shown in Table 2, when the ratio of the one-line duty ratio of a conventional LED electronic circuit board divided by the total driving time of one line for the actual one line lighting time within the vertical synchronization time (Vt) as a percentage is 74.45 [%]. If the display ratio of the display is increased to 96 [%], the brightness value is 7,736 [cd / m < 2 >] to 21.55 [cd / [%] Is increased. From this result, it can be seen that in the display control device of the LED electric sign board in which the deterioration phenomenon is progressing The effect of improving the luminance unbalance between the pixels is generated and the lifetime extension effect is obtained. Also, it can be seen that the current can be reduced by 21.55% if the initial LED signboard can be maintained at 6,000 [cd / ㎡]. In addition, the LED deterioration phenomenon can be delayed and the lifetime extension effect can be obtained. In addition, considering the lowering of image quality, If the luminance implementation basic pulse number is lowered, the luminance unbalance is reduced, and the overall image quality can be improved.

개, (n값은 5 ≤ n ≤ 12)일 때, 휘도구현 기본펄스는 32, 64, 128, 256, 512, …, 4096개이며, 휘도구현 비트를 12비트에서 20비트 범위 내에서 가변적으로 변화시켜 휘도 값을 증가하거나 감소하게 할 수 있다. 이하, 수학식 (1)을 이용하여 본 발명의 고안자가 창안한 가변 휘도구현 비트 및 휘도구현 펄스를 생성하는 과정을 설명한다.In this way, the luminance implementation bit can be varied in a range of 12 bits to 20 bits in a range where the flicker phenomenon can not be detected, and a method capable of increasing or decreasing the luminance value. The basic pulse number is changed from 32 to 4096 The performance of the display control device is improved by correcting the luminance unevenness of the LED display panel by increasing or decreasing the brightness by applying the basic pulse number adapted to the luminance according to the progress of the degradation phenomenon from the initial production of the LED display board The following embodiments can be implemented. According to a preferred embodiment of the present invention,

(N value is 5 ≤ n ≤ 12), the luminance implementation basic pulse is 32, 64, 128, 256, 512, ... , 4096, and the luminance value can be increased or decreased by variably changing the luminance implementation bit within the range of 12 bits to 20 bits. Hereinafter, a process of generating the variable luminance implementation bit and the luminance implementation pulse invented by the inventor of the present invention using Equation (1) will be described.

(I) Set the basic number of pulses for implementation of brightness, the number of shift-latches and the value of brightness implementation bit

When the luminance implementation bit is within the range of 12 bits to 20 bits, the luminance implementation value has a value from 0 to 1,048,576. Since the luminance increases when the number of shift-latches is increased, the range within which the flicker phenomenon can not be detected In order to perform the shift-latch repeatedly. For this, the luminance implementation basic pulse number Pn and the total shift-latch number Sm must be determined first. The Sm / Sl value is calculated by determining the number of shift-latches (Sl) per scan line. This value means that the total number of shift-latches (Sm) is repeated in the Sm / Sl cycle by grouping the number of shift-latches (Sl) per scan line. The refresh rate is determined according to how many times this value is repeated within the vertical synchronization time (Vt). If the number of times the shift-latch is repeated within the vertical synchronization time (Vt) is defined as the number of repetitions (O) per Vt time, the refresh rate becomes the frequency of the vertical synchronization signal x O x (Sm / Sl). As an example, Sm / Sl = 8 is obtained by grouping 24 of the shift-latch times Sl per scan line 192 of the vertical sync signal frequency of 60 [Hz] and the total shift-latch number of times Sm (Sm) If the number of times O is four times, the refresh rate is 60 × 8 × 4 = 1,920 [Hz].

If the Sm / Sl value is increased, that is, Sm / Sl = 9, Sl value is 24, and O value is 4, the total number of shift-latches (Sm) becomes 24 × 9 = 216 and the refresh rate is 60 × 9 × 4 = 2,160 [Hz].

Table 3 shows the relationship between the bit number and the shift-latch count for 192 total shift-latch counts and 128 basic implementation pulse counts according to the first preferred embodiment of the present invention.

128 basic pulse number implementation, 192 shift-latch times, relationship with corresponding bit value Bit order 0 One 2 3 4 5 6 7 8 9 10 Bit value One 2 4 8 16 32 32 128 256 512 1024 Shift-latch
Number of times 0 One 2 3 4 5 6 7 8 9 10 ... 13 14 ... 21 Implement brightness
Number of pulses One 2 4 8 16 32 32 128 128 128 128 ... 128 128 ... 128 Bit order 11 12 13 14 6 Bit value 2048 4096 8192 7296 32 Shift-latch
Number of times 22 ... 37 38 ... 69 70 ... 133 134 ... 190 191 Implement brightness
Number of pulses 128 ... 128 128 ... 128 128 ... 128 128 ... 128 32

In addition, the total shift-latch count Sm must be determined in consideration of the relationship between the luminance implementation basic pulse number, the shift-latch count, and the corresponding bit value as in the shift-latch procedure 191 of Table 3 according to the Sm / do. In Table 3, the 19th bit in the shift-latch order shows the sixth order of the bit order and the number of the basic implementation pulses of the luminance is 32. This indicates that the sixth bit of the original bit order is 64, The number of basic pulses was 64, but the 6th bit order bit value and the luminance implementation pulse were divided into two, one for the sixth shift and the other for the 191st. The reason for such a configuration is to rearrange the shift-latch sequence of the bit value having the low-luminance implementation basic pulse number as shown in Tables 13 and 14 to be described later, at a time when the afterimage occurs, thereby increasing the luminance. That is, to increase the refresh rate, the total number of shift-latches 192 is grouped 24 times and repeated 8 times, so that the number of bits having low luminance implementation basic pulse number is 7 in the 0th to 6th bits. 1 ", it is determined that the bit order is low in the 191st shift-latch sequence.

Next, when a table indicating the relationship between the luminance implementation basic pulse number, the shift-latch count, and the corresponding bit values is completed as shown in Table 3, all the bit values are added using this table to calculate the luminance implementation value Bs. As shown in Table 3, the luminance implementation value is a sum of all the bit values, which is 0 to 23,679.

Meanwhile, Table 4 shows the relationship between the number of total shift-latches according to the second preferred embodiment of the present invention and the relationship between the bit value and the number of shift-latches, .

256 luminance basic pulse numbers, 192 shift-latch times, relationship with corresponding bit values Bit order 0 One 2 3 4 5 6 7 8 9
10
Bit value One 2 4 8 16 32 32 128 256 512 1024 Shift - Number of Latches 0 One 2 3 4 5 6 7 8 9 10 11 ... 14
Implement brightness
Number of pulses One 2 4 8 16 32 32 128 256 256 256 256 ... 256
Bit order 11 12 13 14 15 Bit value 2048 4096 8192 16384 14592 Shift - Number of Latches 15 ... 22 23 ... 38 39 ... 70 71 ... 134 135 ... 191 Implement brightness
Number of pulses 256 ... 256 256 ... 256 256 ... 256 256 ... 256 256 ... 256

Table 4 shows that the bit order sixth bit value and the luminance implementation pulse are divided into two parts, one as shown in Table 3, and the other as the sixth and the 191st shift-latch sequence. In order to increase the refresh rate, the total number of shift-latches 192 is repeated 24 times, and the number of times of repetition is 8 times. Therefore, in Table 4, This is because it is necessary to allocate them one by one in the process of repeating 8 times.

Next, when a table showing the relationship between the luminance implementation basic pulse number, shift-latch count and corresponding bit values is completed as shown in Table 4, all the bit values are added by using this table to calculate the luminance implementation value Bs. As shown in Table 4, the luminance implementation value is a sum of all the bit values, which is 0 to 47,359.

(Ii) bit-by-bit mapping of luminance implementation values (0 to Bs)

In order to implement the luminance and color control device with the FPGA, the gain, offset and scale are adjusted so that the luminance implementation value f (x) of Equation (1) becomes 0 to Bs, Create a table that maps by.

As an example, the tables mapped for each bit using Table 3 and Table 4 are shown in Table 5 and Table 6, respectively.

Bit-by-bit mapping table for luminance implementation values 0 to 23,679 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit value sum 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 One One 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 2 One 3































16384 0 4096 2048 1024 0 0 0 64 32 16 8 4 2 0 23,678 16384 0 4096 2048 1024 0 0 0 64 32 16 8 4 2 One 23,679

Bit-by-bit mapping table for luminance implementation values 0 to 47,359 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit value sum 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 One One 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 One 3

































32768 0 8192 4096 2048 0 0 0 0 0 0 0 0 0 0 0 47,104 32768 0 8192 4096 2048 0 0 0 128 64 32 16 8 4 2 One 47,359

(Iii) Mapping of the modified luminance value 0 to Bs by the modified bit

Using the bit-by-bit mapping table created in the previous section, it is checked whether 0 is present in the number of bits representing the bit value mapped to the maximum luminance implementation value Bs. If there is no 0 value, this bit-by-bit mapping table is used as is, and if there is a 0 value, the modified bit value mapping is performed as shown in Tables 7 and 8. The modified bit value mapping is performed in order to maximize the luminance value.

Referring to Table 5, the luminance implementation value 23,679 is 14 bits constituted of 192 shift-latch times, but D7, D8, D9, D13 Since the bit value is 0, the luminance value is lowered by this influence. For the reason, when the highest luminance implementation value 23,679 is mapped on a bit-by-bit basis, the brightness of the LED is highest when all the bit values are 1. In this case, the values of the bits D7, D8, D9 and D13 are 0, This is because the LED does not light up and the luminance is lowered accordingly.

Therefore, as shown in Table 7, it is necessary to map the luminance value 23,679 to a value of 1 in all bits by modifying the X region into the X 'region and performing bit-by-bit mapping on the bit values.

Modified bit mapping table for Table 5 division D C B A D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit value sum 7296 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 128 1024 2048 4096 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 One One 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 2 One 3































X 16384 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16,384 16384 0 4096 0 1024 512 256 128 64 32 16 8 4 2 One 22,527 16384 0 4096 2048 0 0 0 0 0 0 0 0 0 0 0 22,528 16384 0 4096 2048 0 512 256 128 64 32 16 8 4 2 One 23,551 16384 0 4096 2048 1024 0 0 0 0 0 0 0 0 0 0 23,552 16384 0 4096 2048 1024 0 0 0 64 32 16 8 4 2 One 23,679 X ' 2048 4096 × 8192 0 2048 0 0 0 0 0 0 0 0 0 0 0 16,384 2048 4096 × 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 22,527 1024 2048 4096 × 8192 4096 2048 1024 0 0 0 0 0 0 0 0 0 0 22,528 1024 2048 4096 × 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 23,551 128 1024 2048 4096 × 8192 4096 2048 1024 512 256 128 0 0 0 0 0 0 0 23,552 128 1024 2048 4096 × 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 23,679

In accordance with the second embodiment of the present invention, the luminance implementation values 0 to 47,359 are 15 bits consisting of 192 shift-latch times, but actually D8, D9, D10, Since the D14 bit value is 0, the luminance value is lowered by this influence. Therefore, as shown in Table 8, it is necessary to map the luminance value 47,359 to 1 in all bits by modifying the Y region into the Y 'region and performing bit-by-bit mapping on the bit values.

Modified bit value mapping for Table 6 division D C B A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit value sum 14592 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 256 2048 4096 8192 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 One One 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 One 3

































Y 32768 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32,768 32768 0 0 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 40,959 32768 0 8192 0 0 0 0 0 0 0 0 0 0 0 0 0 40,960 32768 0 8192 0 2048 1024 512 256 128 64 32 16 8 4 2 One 45,055 32768 0 8192 4096 0 0 0 0 0 0 0 0 0 0 0 0 45,056 32768 0 8192 4096 0 1024 512 256 128 64 32 16 8 4 2 One 47,103 32768 0 8192 4096 2048 0 0 0 0 0 0 0 0 0 0 0 47,104 32768 0 8192 4096 2048 0 0 0 128 64 32 16 8 4 2 One 47,359 Y ' 8192 × 16384 8192 0 0 0 0 0 0 0 0 0 0 0 0 0 32,768 8192 × 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 40,959 4096 8192 × 16384 8192 4096 0 0 0 0 0 0 0 0 0 0 0 0 40,960 4096 8192 × 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 45,055 2048 4096 8192 × 16384 8192 4096 2048 0 0 0 0 0 0 0 0 0 0 0 45,056 2048 4096 8192 × 16384 8192 4096 2 048 1024 512 256 128 64 32 16 8 4 2 One 47,103 256 2048 4096 8192 × 16384 8192 4096 2048 1024 512 256 0 0 0 0 0 0 0 0 47,104 256 2048 4096 8192 × 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 One 47,359

(Iv) Create logical equations for modified bitmaps

A logic operation truth table is created so that the modified bit values of the luminance implementation values 0 to Bs can be applied as bit values, and a logic operation expression is created. This logic operation expression reflects this logical operation expression when designing the hardware using Equation (1), and outputs the modified bit mapping value.

As a first example, in order to map the values in the X region of Table 7 to the values of the X 'region, bit operations must be performed for each bit. Table 9 shows logical operation truth tables for bit value mapping in Table 7. When the D14 bit is 1, the D13 bit is 0, the D12 bit is 1, and the D11 bit is 0 simultaneously, the A bit is 1, the B bit is 1, and D13 and D11 are 1 When the D14 bit is 1, the D13 bit is 0, the D12 bit is 1, the D11 bit is 1, and the D10 bit is 0, the A bit is 1, the B bit is 1, and the C bit is 1 And logical operations are performed so that D13 and D10 have one value. When the D14 bit is 1, the D13 bit is 0, the D12 bit is 1, the D11 bit is 1, and the D10 bit is 1, the A bit is 1, the B bit is 1, the C bit is 1, and the D bit is 1 D13, D9, D8, and D7 have a value of one.

Logical operation truth table for bit value mapping in Table 7 D14 D13 D12 D11 D10 D9 D8 D7 Operation contents 16384 8192 4096 2048 1024 512 256 128 One 0 One 0 × × × × A = 1, B = 1, D13 = 1, D11 = 1 One 0 One One 0 × × × A = 1, B = 1, C = 1, D13 = 1, D10 = 1 One 0 One One One 0 0 0 A = 1, B = 1, C = 1, D = 1, D13 = 1, D11 = 1 One 0 One One One 0 0 0 A = 1, B = 1, C = 1, D = 1, D13 = 1, D9 = 1, D8 = 1, D7 = 1

(Actually A has 8192, B has 4096, C has 1024, and D has a value of 128)

As a second example, in order to map the value in the Y area of Table 8 to the value of the Y 'area, a bit operation must be performed for each bit. Table 10 shows a logical operation truth table for bit value mapping in Table 8. [ When the D15 bit is 1, the D14 bit is 0, and the D13 bit is 0 simultaneously, the logic operation is performed so that the A bit has 1, the D13 and D11 have 1, and the D15 bit is set to 1 1, the D14 bit is 0, the D13 bit is 1, and the D12 bit is 0, the logical operation is performed so that the A bit is 1, the B bit is 1, D14 and D12 have a value of 1, When bit A is 1, bit D14 is 0, bit D13 is 1, bit D12 is 1, and bit D11 is 0 simultaneously, A bit is 1, B bit is 1, C bit is 1 and D14 and D11 are 1 To perform the logical operation. When the D15 bit is 1, the D14 bit is 0, the D13 bit is 1, the D12 bit is 1, the D11 bit is 0, the D10 bit is 0, the D9 bit is 0, The logical operation is performed so that the B bit is 1, the C bit is 1, the D bit is 1, and D14, D10, D9, and D8 have a value of 1.

Table 8 Logical operation truth table for bit value implementation D15 D14 D13 D12 D11 D10 D9 D8 Operation contents 32768 16384 8192 4096 2048 1024 512 256 One 0 0 × × × × × A = 1, D14 = 1, D13 = 1 One 0 One 0 × × × × A = 1, B = 1, D14 = 1, D12 = 1 One 0 One One 0 × × × A = 1, B = 1, C = 1, D14 = 1, D11 = 1 One 0 One One One 0 0 0 A = 1, B = 1, C = 1, D = 1, D14 = 1, D10 = 1, D9 = 1, D8 = 1

(V) resetting the luminance implementation basic pulse number, shift-latch number and luminance implementation bit value

Using the logical operation truth table, rewrite the relationship between the number of basic luminance pulses, the number of shift-latches, and the corresponding bit values as a table.

With respect to the first embodiment of the present invention, the relationship between the luminance implementation basic pulse number, the corresponding bit value, and the number of shift-latch times in Table 8 is shown in Table 11 for the luminance implementation bits 0 to 23,679.

Implementation of luminance reconstruction in Table 7 The number of existing pulses 128, the number of shift-latches 192, the relationship between the bit values Bit order 0 One 2 3 4 5 6 7 8
9
10
11
Bit value One 2 4 8 16 32 32 128 256
512
1024
2048
shift
Number of Latches 0 One 2 3 4 5 6 7 8 9 10 ... 13 14 ... 21 22 ... ... 37 Number of pulses of luminance implementation One 2 4 8 16 32 32 128 128 128 128 ... 128 128 ... 128 128 ... 128 Bit order 12 13 A B C
D 6 Bit value 4096 8192 4096 2048 1024
128 32 shift
Number of Latches 38 ... 69 70 ... 133 134 ... 165 166 ... 181 182 ... 189 190 191 Number of pulses of luminance implementation 128 ... 128 128 ... 128 128 ... 128 128 ... 128 128 ... 128 128 32

Table 12 shows the relationship between the luminance implementation basic pulse number, the corresponding bit value, and the number of shift-latch times for the value of the luminance implementation 0 to 23,679 in Table 8 according to the second embodiment of the present invention.

Table 8 shows the relationship between the number of luminance implementation basic pulses 256 reconstructed, the number of shift-latches 192, and the corresponding bit values Bit order 0 One 2 3 4 5 6 7 8 9 10 11 12 Bit value One 2 4 8 16 32 32 128 256 512 1024 2048 4096 shift
Number of Latches 0 One 2 3 4 5 6 7 8 9 10 11 ...
14 15 ... 22 23 ... 38 Number of pulses of luminance implementation One 2 4 8 16 32 32 128 256 256 256 256 ...
256 256 ... 256 256 ... 256 Bit order 13 14 A B C D Bit value 8192 16384 8192 4096 2048 256 shift
Number of Latches 39 ... 70 71 ... 134 135 ...
166 167 ...
182 183 ...
190 191
Number of pulses of luminance implementation 256 ... 256 256 ... 256 256 ...
256 256 ...
256 256 ...
256 256

(Vi) Shift-Latch Order Reconstruction for Increasing Luminance and Refresh Rate

The shift-latch sequence is reconstructed to eliminate the LED forced OFF time of the scan line switching time to eliminate the afterimage, and the shift-latch sequence is reconfigured to increase the refresh rate.

In the first embodiment of the present invention, a shift-latch sequence of a bit value having a basic pulse number of low luminance implementation is reconstructed in a time zone in which a residual image is generated using Table 11, The order of the latches is shown in Table 8.

 Here, X = number of scans, Y = corresponding bit, Z = number of shift-latches, and W = number of luminance implementation pulses.

A shift-latch method reconstructing Table 11 for increasing the luminance and refresh rate X One Y 0 7 10 11 11 12 12 12 12 13 13 13 13 13 13 13 13 A A A A B B C Z 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 W One 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 X 2 Y One 9 10 11 11 12 12 12 12 13 13 13 13 13 13 13 13 A A A A B B C Z 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 W 2 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 X 3 Y 2 10 10 11 11 12 12 12 12 13 13 13 13 13 13 13 13 13 A A A B B C Z 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 W 4 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 X 4 Y 3 9 10 11 11 12 12 12 12 13 13 13 13 13 13 13 13 13 A A A B B C Z 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 W 8 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 X 5 Y 4 8 10 11 11 12 12 12 12 13 13 13 13 13 13 13 13 13 A A A B B C Z 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 W 16 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 X 6 Y 5 9 10 11 11 12 12 12 12 13 13 13 13 13 13 13 13 13 A A A B B C Z 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 W 32 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 X 7 Y 6 8 11 11 12 12 12 12 12 13 13 13 13 13 13 13 13 13 A A A B B C Z 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 W 32 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 X 8 Y 6 9 10 11 11 12 12 12 13 13 13 13 13 13 13 13 13 A A A B B C D Z 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 W 32 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128

In accordance with the second embodiment of the present invention, a shift-latch sequence of a bit value having a basic pulse number with a low luminance implementation is reconstructed in a time zone in which a residual image is generated using Table 12, Table 14 shows the latching order.

Here, X = number of scans, Y = corresponding bit, Z = number of shift-latches, and W = number of luminance implementation pulses.

The increase in luminance and reflectance is calculated by subtracting the shift-latch method One 0 8 11 12 12 13 13 13 13 14 14 14 14 14 14 14 14 C B B A A A 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 One 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 2 One 10 11 12 12 13 13 13 13 14 14 14 14 14 14 14 14 C B B A A A 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 2 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 3 2 9 11 12 12 13 13 13 13 14 14 14 14 14 14 14 14 C B B A A A 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 4 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 4 3 10 11 12 12 13 13 13 13 14 14 14 14 14 14 14 14 C B B A A A 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 8 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 5 4 11 D 12 12 13 13 13 13 14 14 14 14 14 14 14 14 C B B A A A 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 16 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 6 5 10 11 12 12 13 13 13 13 14 14 14 14 14 14 14 14 C B B A A A 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 32 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 7 6 9 11 12 12 13 13 13 13 14 14 14 14 14 14 14 14 C B B A A A 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 64 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 8 7 10 11 12 12 13 13 13 13 14 14 14 14 14 14 14 14 C B B A A A 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 128 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256

The luminance and color control device transmits the luminance implementation bit values of the respective red, green, and blue image data to the LPM module's image signal and control signal generator in order to reconstruct the order of the shift-latch number, to the LPM module The image signal and the control signal generator input the respective red, green, and blue luminance implementation bit values into the LPM module in series by 1 bit.

According to the variable luminance implementation bit generation method, the luminance value can be increased or decreased by using the luminance implementation bit and the basic implementation pulse number of luminance implementation. Using this feature, the LED lighting ratio for the luminance implementation value can be calculated, and the luminance value can be increased by the rate at which the luminance value is lowered in the LED electronic board where the deterioration has progressed.

 Table 2 shows a method of calculating the lighting time of the LED when the duty cycle of the LED screen module is 1/4, and the frequency of the vertical synchronizing signal input from the computer or the DVD player is 60 Hz, that is, the refresh rate is 60 Hz. Is defined as a value obtained by dividing one line lighting ratio for full color representation of a 1/4 duty cycle LED display panel by one line total driving time for an actual one line lighting time within a vertical synchronization time Vt, Assuming that the number of times of repetition per one vertical scanning time (Vt) is four, the number of times of shift-latching (S) per one repetition time (O) is eight The basic implementation pulse width, lighting time, and lighting rate were calculated by increasing the number of total shift-latches by 40 and starting with 40 times according to the luminance implementation basic pulse number, and are shown in Table 15.

1 line lighting ratio for full color representation (Vt total driving time per line [Ns] = 4.1667 [mS]) Basic number of pulse implementation Shift - Number of Latches 40 48 56 64 Pulse width
[nS] light on Pulse width
[nS] light on Pulse width
[nS] light on Pulse width
[nS] light on time
[mS] rate
[%] time
[mS] rate
[%] time
[mS] rate
[%] time
[mS] rate
[%] 1024 25.4313 3.229 77.5 21.193 3.386 81.25 18.165 3.497 83.9 512 50.8625 3.333 79.99 42.385 3.472 83.33 36.33 3.571 85.7 31.789 3.646 87.49 256 101.725 3.437 82.49 84.771 3.559 85.41 72.66 3.646 87.49 63.578 3.710 89.05 128 203.405 3.437 82.49 169.542 3.558 85.4 145.321 3.645 87.48 127.156 3.710 89.05 64 406.901 3.54 84.96 339.084 3.64 87.46 290.644 3.719 89.25 254.313 3.775 90.60 32 813.8 3.538 84.92 678.17 3.643 87.43 581.285 3.718 89.23 508.625 3.774 90.57 Basic number of pulse implementation Shift - Number of Latches 72 80 88 96 Pulse width
[nS] light on Pulse width
[nS] light on Pulse width
[nS] light on Pulse width
[nS] light on time
[mS] rate
[%] time
[mS] rate
[%] time
[mS] rate
[%] time
[mS] rate
[%] 512 28.257 3.704 88.88 25.431 3.75 89 23.119 3.788 90.9 21.1927 3.819 91.66 256 56.514 3.761 90.27 50.863 3.802 91.24 46.239 3.835 92.04 42.386 3.863 92.7 128 113.027 3.710 90.26 101.725 3.802 91.24 92.4775 3.835 92.04 84.7708 3.863 92.7 64 226.055 3.819 91.64 203.45 3.853 92.48 184.9545 3.882 93.16 169.542 3.906 93.73 32 452.111 3.1877 91.62 406.9 3.853 92.46 369.909 3.857 93.14 339.083 3.905 93.71 Basic number of pulse implementation Shift - Number of Latches 128 136 192 200 Pulse width
[nS] light on Pulse width
[nS] light on Pulse width
[nS] light on Pulse width
[nS] light on time
[mS] rate
[%] time
[mS] rate
[%] time
[mS] rate
[%] time
[mS] rate
[%] 512 15.896 3.907 93.76 14.959 3.922 94.11 256 31.789 3.939 94.53 29.919 3.952 94.85 21.193 4.015 96.4 20.345 4.0 95.6 128 63.578 3.939 94.53 59.838 3.952 94.85 42.3854 4.015 96.4 40.69 4.021 96.5 64 127.156 3.971 95.3 119.676 3.982 95.56 84.771 4.036 96.86 81.38 4.041 96.98 32 254.3125 3.970 95.25 239.353 3.982 95.56 169.541 4.036 96.86 162.76 4.041 96.98

As shown in Table 15, as the total number of shift-latches increases, the lighting ratio increases. Also, when the number of basic pulses for implementing luminance increases, the quality of the image becomes better but the lighting ratio decreases. And the lighting ratio is increased.

By using such luminance characteristics, it is possible to manufacture the LED electronic signboard by setting the lighting ratio to 80% and then considering the quality and luminance of the image according to the progress of the deterioration phenomenon. The lifetime of the LED electric signboard due to the luminance unbalance can be extended by adaptively controlling the basic pulse number for realizing the luminance and the total shift-latch count. In addition, when the LED display panel having the conventional lighting ratio of 80% or less is brought to a state where it can not be watched due to the deterioration phenomenon, the lighting ratio is increased to thereby reduce the brightness unevenness and prolong the life of the LED display panel.

The above-described embodiments are merely illustrative, and various modifications and equivalents may be made by those skilled in the art. Accordingly, the true scope of protection of the present invention should be determined by the technical idea of the invention described in the following claims.

100:
200: luminance and color control processing device
210: Control device
220: RGB storage device
230:
240: Variable Pulse Generator
250: Timing and signal generator of LPM module
300: LPM module

Claims (8)

An adaptive luminance and color control device for luminance unbalance correction of an LED electric billboard which receives image data from outside and generates an image signal and a control signal for driving an LED pixel matrix (LED Pixel Matrix, 'LPM' as,
A memory for storing 8-bit image data and control signals of red (R), green (G), and blue (B);
A memory control signal and a luminance correction operation control signal for controlling the arithmetic operation unit to read the 8-bit image data stored in the memory and perform a luminance correction operation on the image data, A control device for generating a control signal and generating an LPM module timing and signal generation control signal;
A variable pulse generator for generating a variable pulse in accordance with the variable pulse generation control signal received from the control device; And a control circuit for receiving the variable pulse generated from the variable pulse generator and outputting the luminance implementation bit and the luminance of the 8-bit image data based on the memory address signal, the memory control signal, The arithmetic device performing a luminance correction operation with respect to an implementation basic pulse number and generating a luminance implementation bit value converted according to the luminance correction operation; And
CLAIMS 1. An LPM module control apparatus for controlling timing and signal generation of an LPM module, the LPM module control apparatus comprising: a variable pulse generator for receiving a variable pulse generated from the variable pulse generator, receiving the converted circuit implementation bit value from the processor, An OE (Out Enable) signal, a ST (Strobe) signal, and a scan line selection signal according to the LPM module's specifications based on the timing and signal generation control signal of the LPM module, And transmits the control signals to the LPM module by synchronizing the converted luminance implementation bit value with the control signals,
The arithmetic unit performs a luminance correction operation in accordance with the luminance impairment caused by the deterioration of the LPM module to adjust the number of luminance implementation bits and the number of luminance implementation pulses for the LPM module so that the luminance imbalance Wherein the brightness of the LED display panel is reduced by a predetermined amount. The method according to claim 1,
The brightness and color control device adjusts the seat flap order of the bit value having a low luminance implementation pulse number to a time when the afterimage occurs, thereby increasing the luminance. The adaptive luminance and color control for the luminance unbalance correction of the LED electronic billboard Device. The method according to claim 1,
The arithmetic unit maps the luminance implementation basic pulse number, the shift-latch number, and the corresponding bit value of the LPM module, obtains the maximum luminance implementation value Bs obtained by adding all the bit values mapped, The luminance implementation bit for each luminance implementation value is mapped within a range where the luminance implementation value is between 0 and Bs, and if 0 exists in the bits representing the bit value mapped to the Bs, Generating a modified bit-mapping table according to the logical expression, generating a converted luminance implementation bit value according to the modified bit-mapping table, And applying the corrected number of luminance implementation bits and the number of luminance implementation pulses according to the luminance implementation bit value to the LPM module to reduce the luminance unbalance due to deterioration of the LPM module. Adaptive brightness and color control device for the unbalance correction. A method of variably generating and controlling a luminance implementation bit and a luminance implementation pulse of an image signal for driving an LED pixel matrix (LPM) module in a display controller of an LED electric sign board,
Setting a luminance implementation bit value according to a luminance implementation basic pulse number and a shift-latch number; Mapping the luminance implementation basic pulse number, the shift-latch number and the corresponding bit value; Adding all bit values to obtain a maximum luminance implementation value Bs; Mapping luminance implementation bits for each luminance implementation value within a range of luminance implementation values from 0 to Bs;
Mapping a modified bit value to each luminance implementation value if 0 is present in the bit value mapped to the maximum luminance implementation value; Generating a modified logical expression for outputting the modified bit value; Generating a modified bit mapping table according to the logical expression; And generating a converted luminance implementation bit value according to the modified bit mapping table. ≪ Desc / Clms Page number 19 > 5. The method of claim 4,
After the step of generating the modified bit mapping table, the order of the shift-latch count of the bit value having the low luminance implementation pulse number in the bit mapping table is rearranged to the time when the afterimage occurs, And changing the order of the number of times of the brightness adjustment of the LED display panel. An LED display control device for controlling an LED display in which a plurality of LPM modules composed of LED pixel matrix are arranged,
A receiving unit for receiving an external video signal and converting each 8-bit video data of red (R), green (G) and blue (B) into a clock signal, a vertical synchronizing signal, a horizontal synchronizing signal and a DE signal;
A memory for storing 8-bit image data and control signals of red (R), green (G), and blue (B);
A memory control signal and a luminance correction operation control signal for controlling the arithmetic unit to read the image data stored in the memory and perform a luminance correction operation on the image data, And generates an LPM module timing and signal generation control signal;
A variable pulse generator for generating a variable pulse in accordance with the variable pulse generation control signal received from the control device;
And a control circuit for receiving the variable pulse generated from the variable pulse generator and outputting the luminance implementation bit and the luminance for each of the 8-bit image data based on the memory address signal, the memory control signal, An arithmetic and logic unit for performing a luminance correction operation with respect to an implementation basic pulse number and generating a luminance implementation bit value according to a luminance correction operation; And
An LPM module control apparatus for controlling a timing and a signal generation of an LPM module, the LPM module control apparatus comprising: a variable pulse generator for receiving a variable pulse generated from the variable pulse generator and receiving the converted circuit implementation bit value from the processor; OE (Out Enable) signal, a ST (Strobe) signal, and a scan line select signal according to the LPM module standard on the basis of the LPM module timing and signal generation control signal and outputs the control signal to the LPM module And transmits the control signals to the LPM module by synchronizing the converted luminance implementation bit value with the control signals,
The arithmetic unit performs a luminance correction operation in accordance with the luminance impairment caused by deterioration of the LPM module to adjust the number of luminance implementation bits and the number of luminance implementation pulses for the LPM module so that the luminance on the LPM module LED display control device for reducing imbalance. The method according to claim 6,
Wherein the arithmetic unit reconfigures the shift-latch sequence of bit values having a low luminance implementation pulse number to a time zone in which a residual image occurs, thereby increasing the luminance. The method according to claim 6,
The arithmetic unit maps the luminance implementation basic pulse number, the shift-latch number, and the corresponding bit value of the LPM module, obtains the maximum luminance implementation value Bs obtained by adding all the bit values mapped, The luminance implementation bit for each luminance implementation value is mapped within a range where the luminance implementation value is between 0 and Bs, and if 0 exists in the bits representing the bit value mapped to the Bs, Generating a modified bit-mapping table according to the logical expression, generating a converted luminance implementation bit value according to the modified bit-mapping table, Further comprising applying the corrected number of luminance implementation bits and the number of implemented luminance pulses to the LPM module in accordance with the luminance implementation bit value to reduce the luminance unbalance due to degradation of the LPM module. Control devices.

Images