KR101873060B1 - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device according to an embodiment includes: a substrate; A liquid crystal display panel on the substrate; A driver IC for transmitting a signal supplied to the liquid crystal display panel; And a link line for supplying a signal to the liquid crystal display panel, wherein the link line includes: a first link line formed on the substrate; And a second link line formed between the first link line and the insulating film, and compensates the process errors of the first and second link lines with gamma voltages of different sizes.

Description

[0001] Liquid crystal display device [0002]

The embodiment relates to a liquid crystal display device.

Various display devices capable of displaying information are being developed. The display device may be, for example, a liquid crystal display device, a plasma display panel device, an electrophoretic display device, an organic electro-luminescence display device, And a semiconductor light-emitting display device.

Of these, the liquid crystal display device has excellent image quality, light weight, thinness, and low power consumption, and has been popular as a representative display device. For example, liquid crystal displays are widely employed in mobile phones, navigation systems, notebooks, and televisions.

1 is a view showing a conventional liquid crystal display device.

Referring to FIG. 1, a conventional liquid crystal display device includes a driver IC 104 and a liquid crystal display panel 103 on a substrate 101.

On the liquid crystal display panel 103, a plurality of gate lines (not shown) and a plurality of data lines DL1 to DLm are formed.

A link line 107 for electrically connecting the plurality of data lines DL1 to DLm to the driver IC 104 is formed. A pad portion 105 for applying a video signal to the driver IC 104 from the outside is formed on one side of the substrate 101. A plurality of link lines 107 are required as the resolution of a recent liquid crystal display device increases and the number of the link lines 107 is increased so that the driver IC 104 is transferred from the liquid crystal display panel 103 by the process margin, The second distance L2 from the liquid crystal display panel 103 to the end of the substrate adjacent to the pad unit 105 is increased. The second distance L2 is a non-display area that does not display an image, and the area of the non-display area is increased, thereby hindering reduction in thickness and weight of the liquid crystal display device.

The embodiment provides a liquid crystal display device in which the width of the dual link compensates for image quality by the other link lines.

A liquid crystal display device according to an embodiment includes: a substrate; A liquid crystal display panel on the substrate; A driver IC for transmitting a signal supplied to the liquid crystal display panel; And a link line for supplying a signal to the liquid crystal display panel, wherein the link line includes: a first link line formed on the substrate; And a second link line formed between the first link line and the insulating film, and compensates the process errors of the first and second link lines with gamma voltages of different sizes.

Embodiments provide a liquid crystal display device that compensates image quality due to RC delay by generating and applying gamma voltages of different sizes to link lines of different widths.

1 is a view showing a conventional liquid crystal display device.
2 is a view showing a liquid crystal display device according to an embodiment.
3 is a cross-sectional view of the liquid crystal display according to the embodiment taken along line A-A '.
4 is a block diagram showing a liquid crystal display device according to an embodiment.
5 is a diagram illustrating a gamma generating unit, a power source unit, and a data driver of the liquid crystal display according to the embodiment.

2 is a view showing a liquid crystal display device according to an embodiment.

Referring to FIG. 2, the liquid crystal display device according to the embodiment may include a driver IC 4 and a liquid crystal display panel 3 on a substrate 1.

On the liquid crystal display panel 3, a plurality of gate lines (not shown) and a plurality of data lines DL1 to DLm are formed.

A plurality of first link lines 7 and second link lines 9 for electrically connecting a plurality of gate lines (not shown) to the driver IC 4 may be formed on the substrate 1. A plurality of first link lines 7 and second link lines 9 for electrically connecting the plurality of data lines DL1 to DLm to the driver IC 4 may be formed on the substrate 1 . The first link line (7) may be formed on a layer different from the second link line (9).

The first link line 7 may be an odd-numbered link line. The second link line 9 may be an even link line.

The driver IC 4 may include a gate driver and a data driver.

A plurality of pad portions 5 may be formed on one side of the substrate 1. The pad unit 5 may transmit a video signal from the outside to the driver IC 4. The pad unit 5 may be electrically connected to a printed circuit board for applying a video signal.

The driver IC 4 may include a gate driver for transmitting a gate signal to the liquid crystal display panel 3 and a data driver for transmitting a data signal to the liquid crystal display panel 3.

The distance between the boundary between the driver IC 4 side of the liquid crystal display panel 3 and one end of the driver IC 4 on the liquid crystal display panel 3 side can be defined as a first distance L1. The first distance L1 may be a shortest distance between the driver IC 4 and the liquid crystal display panel 3. [

A distance from the liquid crystal display panel 3 to an end of the substrate 1 adjacent to the pad unit 5 may be defined as a second distance L2.

By forming the first link line 7 in a layer different from the second link line 9, it is possible to reduce the first distance L1 even if the gap is maintained to maintain the process margin. As a result, by reducing the first distance L1, the second distance L2 is reduced and the area of the non-display area of the image is reduced, thereby making the liquid crystal display thin and light.

3 is a cross-sectional view of the liquid crystal display according to the embodiment taken along line A-A '.

Referring to FIG. 3, a plurality of first link lines 7 may be formed on a substrate 1 in a liquid crystal display device according to an embodiment.

The plurality of first link lines 7 may be formed at regular intervals. The plurality of first link lines 7 may be formed on the same layer as the gate lines of the liquid crystal display panel. The first link line 7 may be formed of a gate metal. The gate metal may be at least one selected from the group consisting of Ti, Cr, Ni, Al, Pt, Au, W, Cu, Group. ≪ / RTI >

A gate insulating film 13 may be formed on the substrate 1 including the plurality of first link lines 7. The gate insulating layer 13 is a layer for electrically isolating the first link line 7 from a layer to be formed later and an insulating material is required and an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) Or organic insulating materials such as benzocyclobutene (BCB).

A plurality of second link lines 9 may be formed on the gate insulating layer 13. The plurality of second link lines 9 may be formed at regular intervals. The plurality of second link lines 9 may be formed between each first link line 7. In other words, the plurality of second link lines 9 may be formed so as not to overlap with the plurality of first link lines 7 in the vertical direction.

The second link line 9 may be formed on the same layer as the data line of the liquid crystal display panel. The second link line 9 may be formed of data metal. The data metal may be at least one selected from the group consisting of Ti, Cr, Ni, Al, Pt, Au, W, Cu, Group. ≪ / RTI >

A protective layer 15 may be formed on the gate insulating layer 13 including the second link line 9. [ The protection layer 15 may insulate the second link line 9 from the second link line 9 and protect the second link line 9 from the outside. The protective layer 15 may include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or an organic insulating material such as BCB (benzocyclobutene).

Although the first link line 7 and the second link line 9 are designed to have the same width, the width W1 of the first link line 7 and the width of the second link line 9, The width W2 of the light emitting diode may be varied. Since the width W1 of the first link line 7 and the width W2 of the second link line 9 are different from each other, the line resistance is changed, and the RC delay is varied, so that the image quality may be deteriorated. The width W1 of the first link line 7 may be greater than the width W2 of the second link line 9. [ The width W1 of the first link line 7 may be smaller than the width W2 of the second link line 9. [ The width W1 of the first link line 7 may be equal to the width W2 of the second link line 9. [

In other words, since the odd-numbered link line and the even-numbered link line have different widths, the line resistance may vary and the image quality may be degraded due to the changed RC delay.

4 is a block diagram showing a liquid crystal display device according to an embodiment.

4, the liquid crystal display according to the embodiment includes a liquid crystal display panel 3, a timing controller 10, a gate driver 20, a data driver 30, a gamma generator 40, and a power source 50 .

On the liquid crystal display panel 3, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm may be formed. The thin film transistor 11 may be electrically connected to the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm.

The timing controller 10 can receive a data clock signal Dclk, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync together with a data signal from an external graphics card.

The timing controller 10 controls the gate driver 20 and the data driver 30 based on a data clock signal Dclk, a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync. Lt; / RTI > The timing control signal may include a gate control signal and a data control signal. The gate control signal may include, for example, a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). The gate start pulse GSP is a signal for controlling the driving start timing of the first gate line of the liquid crystal display panel 3 in one frame and the gate shift clock GSC is a signal for starting the gate driving start time of the liquid crystal panel And the gate output enable (GOE) is a signal for controlling the timing of sending a gate signal to each gate line.

The data control signal may include a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE) signal, a polarity signal (POL) . The source start pulse SSP is a signal for controlling the supply time point of the data voltage of the first line in one frame and the source shift clock SSC is a signal for controlling the supply time point of the data voltage for each line, The source output enable (SOE) is a signal for controlling a time point of sending a data voltage to the data lines of the liquid crystal display panel, and the polarity signal POL is a signal for selecting a data voltage or a negative data voltage.

The timing controller 10 may rearrange the data signals provided from the graphics card to provide the data drivers 30 with data signals.

The timing controller 10 may provide the gate control signal to the gate driver 20 and provide the data control signal and the data signal to the data driver 30.

The gate driver 20 sequentially generates a gate signal based on the gate control signal provided from the timing controller 10 and provides the generated gate signal to the plurality of gate lines GL1 to GLn.

The data driver 30 may provide a data voltage corresponding to the data signal provided from the timing controller 10 to the plurality of data lines DL1 to DLm.

The gamma generator 40 may generate a gamma voltage at a power supply voltage supplied from the power supply 50. The power supply unit 50 may be included in the timing controller 10. The gamma generator 40 may generate a plurality of gamma voltages corresponding to the grayscales at a power supply voltage, and may transmit the gamma voltages to the data driver 30.

The power supply unit 50 may generate and supply a driving voltage for driving the timing controller 10, the gate driver 20, the data driver 30, and the gamma generator 40. The power supply unit 50 may provide a power supply voltage to generate the gamma voltage in the gamma generator 40.

The thin film transistor 11 is on / off controlled by the gate signal, receives the data voltage, transfers the data voltage to the pixel electrode, and controls the displacement of the liquid crystal molecules to display an image. In other words, the gate electrode of the thin film transistor 11 is electrically connected to the gate lines GL1 to GLn to which the gate signal is applied, and the source electrode is electrically connected to the data lines DL1 to DLm through which the data voltage is transmitted , And the drain electrode may be electrically connected to the pixel electrode capable of controlling the displacement of the liquid crystal molecules.

5 is a diagram illustrating a gamma generating unit, a power source unit, and a data driver of the liquid crystal display according to the embodiment.

Referring to FIG. 5, the gamma generator 40 of the liquid crystal display according to the embodiment may include a gamma reference voltage generator 41 and a gamma voltage generator 43.

The gamma generation unit 40 may generate a gamma voltage using a power source voltage applied from the power source unit 50 and may supply a gamma voltage corresponding to a data signal applied to the timing control unit to the data driver 30 . The gamma generator 40 may be included in the data driver 30 and may be included in the timing controller. A part of the configuration of the gamma generator 40 may be included in the data driver 30 and included in the timing controller.

The power supply unit 50 generates a voltage having a plurality of levels for driving the configuration of the liquid crystal display device by receiving a voltage from the outside and applies the voltage to a plurality of configurations of the liquid crystal display device. The gamma generation unit 40 may also receive a power supply voltage from the power supply unit 50 to generate a gamma voltage.

The gamma reference voltage generating unit 41 may generate a plurality of gamma reference voltages using the power source voltage applied by the power source unit 50. The plurality of gamma reference voltages may be, for example, first to eighth gamma reference voltages Vref0 to Vref7. The gamma reference voltage generator 41 may include a gamma resistor string 47 and a gamma reference voltage selector 45 connected in series with the gamma resistor string 47.

The gamma resistance column 47 may be a circuit in which a plurality of resistors R are connected in series. A plurality of resistive elements may be connected to the resistor R and a node connected to each of the resistive elements may be connected to the resistor R. A plurality of gamma reference voltages Can be selected. The gamma reference voltage may be selected by the gamma reference voltage selector 45.

The gamma reference voltage selector 45 may include a plurality of resistive elements. The gamma reference voltage selector 45 may select the highest gamma reference voltage. The gamma reference voltage selector 45 may select one of the low-level gamma reference voltage Vref_L and the high-level gamma reference voltage Vref_H as the highest gamma reference voltage. By selecting the level of the highest gamma reference voltage, a plurality of levels of the gamma reference voltages generated in the gamma resistance column 47 can be selected. For example, when the high level gamma reference voltage Vref_H is selected, the first to eighth gamma reference voltages Vref0 to Vref7 can be selected to be relatively high level, and the low level gamma reference voltage Vref_L When selected, the first to eighth gamma reference voltages Vref0 to Vref7 may be selected to be relatively low level.

When the first to eighth gamma reference voltages Vref0 to Vref7 are selected as the high level, the gamma reference voltages are generated at the nodes adjacent to the gamma reference voltage selector 45 in the plurality of resistors R And the gamma reference voltage (Vref0 to Vref7) at the nodes relatively spaced from the gamma reference voltage selector 45 in the plurality of resistors R when the first to eighth gamma reference voltages Vref0 to Vref7 are selected as the low level, Can be generated.

The gamma voltage generator 43 may generate a gamma voltage with a plurality of gamma reference voltages supplied from the gamma reference voltage generator 41. [ The gamma voltage generator 43 may include a plurality of resistors, and the gamma voltage generator 43 may include a plurality of resistors connected in series. The gamma voltage generator 43 may generate gamma voltages by dividing a plurality of gamma reference voltages by a plurality of resistor elements connected in series. The gamma voltage generator 43 may generate a gamma voltage and supply the gamma voltage to the data driver 30.

As shown in FIG. 3, the difference in the RC delay due to the widths of the first link line and the second link line can be compensated by the gamma reference voltage. In other words, the difference in the RC delay due to the different widths of the odd-numbered link line and the even-numbered link line can be compensated by varying the magnitude of the gamma reference voltage.

For example, when the width of the first link line is greater than the width of the second link line, that is, when the width of the odd-numbered link line is larger than the width of the even-numbered link line, Is larger than the first link line, the RC delay value of the second link line is increased and a gamma voltage of a level higher than that of the first link line may be applied to the second link line. Therefore, the gamma reference voltage selector 45 applies a low level gamma reference voltage lower than the voltage applied to the second link line to the first link line, and the gamma resistance line 47 also has a relatively low level gamma reference You can choose to generate a voltage. The gamma reference voltage selector 45 applies a high-level gamma reference voltage higher than the voltage applied to the first link line to the second link line. In the gamma resistance column 47, Can occur.

For example, when the width of the first link line is smaller than the width of the second link line, that is, when the width of the odd-numbered link line is smaller than the width of the even-numbered link line, Is larger than the second link line, the RC delay value of the first link line is increased, and the gamma voltage of the level higher than that of the second link line is applied to the first link line to compensate. Therefore, the gamma reference voltage selector 45 applies a high-level gamma reference voltage Vref_H higher than the voltage applied to the second link line to the first link line, A high level gamma reference voltage can be selected to occur. The gamma reference voltage selector 45 applies a low level gamma reference voltage lower than the voltage applied to the first link line to the second link line, You can choose to generate a voltage.

When the liquid crystal display panel is driven by a column driven version driving method, all the first link lines in one frame are driven with the same polarity, and all the second link lines are driven with polarities different from those of the first link lines, The polarity can be reversed. Accordingly, the gamma positive voltage generating unit and the gamma negative voltage generating unit generate a high voltage for each frame, thereby compensating the process error. For example, if the positive gamma reference voltage is selected as the high level in the first frame, the negative gamma reference voltage may be selected as the high level in the second frame to compensate for the process error due to the line width variation.

The line width variation due to the process errors of the first link line and the second link line can be compensated for by changing the size of the gamma reference voltage, thereby improving the image quality.

1.101: substrate 3,103: liquid crystal display panel
4,104: driver IC 5,105: pad portion
7: first link line 9: second link line
10: timing controller 11: thin film transistor
13: gate insulating film 15: protective layer
20: gate driver 30: data driver
40: gamma generator 41: gamma reference voltage generator
43: gamma voltage generator 45: gamma reference voltage selector
47: gamma resistance column 50:

Claims (10)

Board;
A liquid crystal display panel on the substrate;
A driver IC for transmitting a signal supplied to the liquid crystal display panel;
A link line for supplying a signal to the liquid crystal display panel; And
A gamma generator for generating a gamma voltage;
Lt; / RTI >
The link line includes:
A first link line formed on the substrate; And
And a second link line formed between the first link line and the insulating film,
Wherein the widths of the first and second link lines are different from each other through a process error of the first link line and the second link line, When the RC delay occurs, the difference of the RC delay is compensated for every frame with different gamma voltages,
The gamma-
A gamma reference voltage generator for receiving a power supply voltage to generate a plurality of gamma reference voltages; And
And a gamma voltage generator for generating a gamma voltage with a gamma reference voltage generated by the gamma reference voltage generator,
Wherein the gamma reference voltage generator comprises:
A resistor for dividing the power supply voltage to generate a plurality of gamma reference voltages; And
And a gamma reference voltage selector connected in series with the resistor to generate a gamma reference voltage,
Wherein the gamma reference voltage selector selects a level of the gamma reference voltage and selects a gamma reference voltage having a low level of gamma reference voltage on a wide link line of the first and second link lines, And applies a high-level gamma voltage to the link line having a small width.
delete delete delete The method according to claim 1,
The gamma reference voltage selector selects a low level and a high level from the highest gamma reference voltage,
And selects a low level and a high level of the gamma reference voltage for each frame in accordance with the selected uppermost gamma reference voltage. 6. The method of claim 5,
The gamma reference voltage selector may include:
And selects the level of the gamma reference voltage according to the widths of the first link line and the second link line. delete The method according to claim 1,
Wherein the resistor unit comprises a plurality of resistors connected in series. The method according to claim 1,
Wherein the gamma reference voltage selector comprises a plurality of resistors connected in series. The method according to claim 1,
Wherein the gamma voltage comprises a positive gamma voltage and a negative gamma voltage,
A voltage having a different polarity is applied to the first link line and the second link line,
Wherein the gamma voltage selectively compensates the positive gamma voltage and the negative gamma voltage for each frame.

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