KR101831684B1 - Clock and data recovery circuit - Google Patents

Abstract

A clock and data recovery circuit of the present invention includes a voltage control oscillator including a capacitor bank; a digital circuit for generating a bank code as a control signal for the capacitor bank and generating an oscillator control code according to the bank code; and a comparator which compares whether an oscillator control voltage generated according to the oscillator control code is within an allowable range. The clock and data recovery circuit operates according to the bank code and the oscillator control code and outputs a recovery clock signal and recovery data signal, when the oscillator control voltage is within the allowable range. It is possible to perform temperature compensation and dead zone compensation.

Description

CLOCK AND DATA RECOVERY CIRCUIT [0002]

The present invention relates to a clock and data recovery circuit.

The clock and data recovery circuit (CDR) is a circuit that restores the clock signal and data from the data received at the receiving end. The clock and data recovery circuit can be divided into a type using an external clock and a type not using an external clock (reference-less CDR).

Conventional interface chips for mobile interface applications require an external crystal oscillator used as a clock source, resulting in a large chip area and high design cost.

To reduce chip area and design costs, we use two loops consisting of a frequency-locked loop (FLL) and a phase-locked loop (PLL), and a reference-less CDR that does not use an external clock However, since it includes two loop filters, the area is still large, and interference between the two loops occurs, so that jitter characteristics are poor.

Conventional reference-less CDRs typically include a voltage-controlled oscillator (VCO), which is sensitive to temperature variations, so that when there is no control voltage margin when phase locked, continuous data recovery is achieved There is no problem.

In addition, the existing frequency detector (FD) generates a deadzone, which is an interval in which the frequency discrimination can not be accurately performed when the input jitter is large. The dead zone becomes wider as the jitter becomes larger. Therefore, existing frequency detectors are not suitable for mobile applications requiring high jitter tolerance (JTOL).

(Non-Patent Document 1) D. Dalton, et. "A 12.5-Mb / s to 2.7-Gb / s Continuous-Rate CDR with Automatic Frequency Acquisition and Data-Rate Readback," ISSCC Dig. Tech. Papers, pp. 230-231, Feb., 2005.

A technical object of the present invention is to provide a clock and data recovery circuit including a voltage-controlled oscillator capable of temperature compensation and a frequency detector capable of dead zone compensation.

A clock and data recovery circuit according to an embodiment of the present invention includes: a voltage controlled oscillator including a capacitor bank; A digital circuit for generating a bank code, which is a control signal for the capacitor bank, and generating an oscillator control code according to the bank code; And a comparator for comparing whether the oscillator control voltage generated according to the oscillator control code is within an allowable range, and if the oscillator control voltage is within the allowable range, operating in accordance with the bank code and the oscillator control code to restore And outputs a clock signal and a restored data signal.

The clock and data recovery circuit may further include a frequency detector outputting a first frequency detection signal, which is a logic value comparing a clock frequency and a data rate, and a second frequency detection signal, which is a flip flop output value of the first frequency detection signal .

Wherein the frequency detector comprises a half-rate detector, the half-rate detector comprising: a first flip-flop having a first clock signal and a receive data signal as inputs; A second flip-flop having an input of a second clock signal and the received data signal; A third flip-flop having an input of the third clock signal and the received data signal; A fourth flip-flop whose input is a fourth clock signal and the received data signal; A first XOR gate to which the output values of the first flip-flop and the second flip-flop are input; A second XOR gate to which the output values of the third flip-flop and the fourth flip-flop are input; A fifth flip-flop having an input of an output value of the first XOR gate and the second XOR gate; A sixth flip-flop having an input of an output value of the first XOR gate and the second XOR gate; And a seventh flip-flop having an output value of the fifth flip-flop and the sixth flip-flop as an input, wherein the first, second, third, and fourth clock signals are clock signals having different phases, The first frequency detection signal may be an output value of the fifth flip flop and the second frequency detection signal may be an output value of the seventh flip flop.

Wherein the frequency detector comprises a full-rate detector, the full-rate detector comprising an eighth flip-flop having a fifth clock signal and a receive data signal input; A ninth flip-flop having an input of the sixth clock signal and the received data signal; A tenth flip-flop in which the output values of the eighth flip-flop and the ninth flip-flop are inputs; An eleventh flip-flop in which the output values of the eighth flip-flop and the ninth flip-flop are inputs; And a twelfth flip flop in which the output values of the tenth flip-flop and the eleventh flip-flop are inputs, the fifth and sixth clock signals are clock signals having different phases, and the first frequency detection signal is And the second frequency detection signal may be an output value of the twelfth flip-flop.

Wherein the clock and data recovery circuit comprises: a phase detector receiving data and a clock signal and outputting a phase difference signal; A charge pump for supplying charge according to the phase difference signal; An oscillator control voltage regulator for regulating the oscillator control voltage according to the oscillator control code; And a loop filter connected to the charge pump or the oscillator control voltage regulator according to a loop selection signal.

The loop filter may be connected to the oscillator control voltage regulator in a frequency clamping process and may be connected to the charge pump in a phase locking process.

Wherein the digital circuitry generates a first bank code and a second bank code in accordance with the first frequency detection signal and generates a first oscillator control code for the first bank code and a second oscillator control code for the second bank code, Generate an oscillator control code and select the bank code and the oscillator control code corresponding to the oscillator control voltage within the tolerance range through the comparator.

If the index difference between the first bank code and the second bank code is not 1, the first bank code and the second bank code may be reset according to the second frequency detection signal.

The clock and data recovery circuit according to the present invention may include a temperature-compensatable voltage-controlled oscillator and a frequency detector capable of dead zone compensation.

1 is a diagram for explaining a clock and data recovery circuit according to an embodiment of the present invention.
2 is a view for explaining a frequency detector according to an embodiment of the present invention.
3 is a diagram for explaining a signal of the frequency detector.
4 is a diagram for explaining signals of the frequency detector when input jitter is large.
5 is a diagram for explaining an average value of the first frequency detection signal and the second frequency detection signal.
6 is a view for explaining a voltage-controlled oscillator according to an embodiment of the present invention.
7 is a diagram for explaining the performance of a voltage-controlled oscillator according to an embodiment of the present invention.
8 is a diagram for explaining a code determination algorithm according to an embodiment of the present invention.
9 is a diagram for explaining a process of generating a first bank code and a second bank code according to a first frequency detection signal.
10 is a diagram for explaining a process of resetting the first bank code and the second bank code according to the second frequency detection signal.
11 is a diagram for explaining a process of generating a first oscillator control code and a second oscillator control code.
12 is a diagram for explaining simulation results of a clock and data recovery circuit according to an embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification. Therefore, the above-mentioned reference numerals can be used in other drawings.

In addition, since the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, the present invention is not necessarily limited to those shown in the drawings. In the drawings, the size and thickness may be exaggerated to clearly represent the layers and regions.

1 is a diagram for explaining a clock and data recovery circuit according to an embodiment of the present invention.

Referring to FIG. 1, a clock and data recovery circuit 10 according to an embodiment of the present invention includes a voltage controlled oscillator 100, a digital circuit unit 200, and a comparator 300. The clock and data recovery circuit 10 further includes a frequency detector 400, a phase detector 500, a charge pump 600, an oscillator control voltage regulator 700, and a loop filter 800, .

The voltage controlled oscillator 100 includes a capacitor bank. The capacitor bank may be a capacitor structure located behind an adjacent delay cell, see FIG.

The voltage controlled oscillator 100 can be controlled according to the oscillator control voltage V _CTRL and can output a recovered clock signal.

The digital circuit unit 200 generates a bank code, which is a control signal for the capacitor bank, and generates an oscillator control code V _CTRL code according to the bank code.

The digital circuit unit 200 may include an oscillator control code generation module 210, a lock detector 220, and a bank code generation module 230. The bank code generation module 230 may generate the bank code according to the frequency detection signal generated by the frequency detector 400. [ The oscillator control code generation module 210 may generate an oscillator control code according to the frequency detection signal generated by the frequency detector 400 and the bank code generated by the bank code generation module 230. The oscillator control code and the bank code will be described later with reference to Figs. The lock detector 220 may lock the frequency locked loop or the phase locked loop when the oscillator control voltage V _CTRL is within the allowable range (V _L to V _H ), depending on the result of the comparator 300.

The comparator 300 compares whether the oscillator control voltage V _CTRL generated in accordance with the oscillator control code V _CTRL code is within the allowable range V _L to V _H. The clock and data restoring circuit 10 operates in accordance with the corresponding bank code and the oscillator control code when the oscillator control voltage V _CTRL is within the allowable range (V _L to V _H ) Can be output.

The frequency detector 400 may output a first frequency detection signal, which is a logic value obtained by comparing a clock frequency and a data rate, and a second frequency detection signal, which is a flip flop output value of the first frequency detection signal . The first frequency detection signal can be used alone if no dead zone occurs. The second frequency detection signal can be used to compensate for the occurrence of a dead zone. The first frequency detection signal and the second frequency detection signal will be described later with reference to Figs.

The frequency detector 400 may operate in a dual-mode according to a data rate. The dual mode includes a half-rate mode and a full-rate mode. The half-rate mode means an operation mode when the data rate has the same Nyquist frequency and clock frequency. The full-rate mode refers to an operation mode when the Nyquist frequency of the data rate is half of the clock frequency. The frequency detector 400 may include a circuit configuration for a dual mode, which will be described below with reference to FIG.

The phase detector 500 may receive the data and clock signals and output a phase difference signal. The clock signal may be a recovered clock signal output from the voltage controlled oscillator 100. [ The phase detector 500 may operate in a dual-mode depending on the data rate. The phase detector 500 outputs a restored data signal.

Charge pump 600 can supply charge according to the phase difference signal. The charge pump 600 may operate in a dual-mode depending on the data rate.

The oscillator control voltage regulator 700 can adjust the oscillator control voltage according to the oscillator control code. Referring to FIG. 1, according to one embodiment, the oscillator control voltage regulator 700 may adjust the oscillator control voltage V _CTRL output through the amplifier by adjusting the resistance ratio of the variable resistor according to the oscillator control code.

The loop filter 800 may be coupled to the charge pump 600 or the oscillator control voltage regulator 100 according to the loop select signal FLL EN. In one embodiment, the loop filter 800 may be coupled to the oscillator control voltage regulator 700 during the frequency clamping process and may be coupled to the charge pump 600 during the phase locking process. That is, in a state where the frequency fixing is not completed, the digital circuit part 200 can output the loop selection signal FLL EN having the logical value 1, and thereby the oscillator control voltage regulator 700 and the loop filter 800 are connected . When the appropriate bank code and the oscillator control code are selected and the frequency fixing is completed, the digital circuit part 200 can output the loop selection signal FLL EN having the logic value 0 and accordingly the oscillator control voltage regulator 700 and the loop The connection of the filter 800 is cut off, and the charge pump 600 and the loop filter 800 are connected, so that the phase fixing process can be performed. The connection and disconnection described above can be implemented through a switching element or the like.

The clock and data recovery circuit 10 according to this embodiment first performs a coarse FLL (Coarse FLL) process to derive a bank code, performs a fine FLL (Fine FLL) process to derive an oscillator control code, PLL process.

If there is no dead zone in the derivation of the bank code and the oscillator control code derivation, the FLL process may be terminated using only the first frequency detection signal. Here, the index difference between the first bank code and the second bank code may be one.

However, when the dead zone occurs, since the index difference between the first bank code and the second bank code derived by the first frequency detection signal exceeds 1, it is possible to use the second frequency detection signal, The code and the second bank code can be reset. This will be described later with reference to FIGS.

2 is a view for explaining a frequency detector according to an embodiment of the present invention.

Referring to FIG. 2, the frequency detector 400 according to an embodiment of the present invention includes a half rate detector 400h and a full rate detector 400f.

The half rate detector 400h includes a first flip flop 401, a second flip flop 402, a third flip flop 403, a fourth flip flop 404, a fifth flip flop 405, A sixth flip flop 406, a seventh flip flop 407, a first XOR gate 431, and a second XOR gate 432.

The first flip-flop 401 may receive the first clock signal CK0 and the received data signal DATA. The second flip-flop 402 may receive the second clock signal CK90 and the received data signal DATA. The third flip-flop 403 may receive the third clock signal CK45 and the received data signal DATA. The fourth flip-flop 404 may receive the fourth clock signal CK135 and the received data signal DATA. The first XOR gate 431 may receive the output values Q0 and Q90 of the first flip-flop 401 and the second flip-flop 402 as inputs. The second XOR gate 432 may receive the output values (Q45, Q135) of the third flip-flop 403 and the fourth flip-flop 404 as inputs. The fifth flip flop 405 may receive the output values Z1 and Z2 of the first XOR gate 431 and the second XOR gate 432 as inputs. The sixth flip flop 406 may receive the output values Z1 and Z2 of the first XOR gate 431 and the second XOR gate 432 as inputs. The seventh flip-flop 407 may receive the output values Z3 and Z4 of the fifth flip-flop 405 and the sixth flip-flop 406 as inputs.

The first, second, third, and fourth clock signals CK0, CK90, CK45, and CK135 may be clock signals having different phases. In the embodiment of FIG. 5, the voltage-controlled oscillator 100 includes a plurality of delay cells 140, and the clock signals, which are the outputs of the delay cells, can have different phases and can be used. For example, with reference to the first clock signal CK0, the second clock signal CK90 may have a 90-degree phase from the first clock signal CK0, and the third clock signal CK45 may have a 90- 1 phase from the first clock signal CK0 and the fourth clock signal CK135 may have a phase of 135 degrees from the first clock signal CK0.

The first frequency detection signal FD_H in the half-rate mode may be the output value of the fifth flip-flop 405. The second frequency detection signal DC-FD_H in the half-rate mode may be the output value of the seventh flip-flop 407.

The full rate detector 400f includes an eighth flip-flop 408, a ninth flip-flop 409, a tenth flip-flop 410, an eleventh flip-flop 411, and a twelfth flip- .

The eighth flip-flop 408 may receive the fifth clock signal CK0 and the received data signal DATA. The ninth flip-flop 409 may receive the sixth clock signal CK90 and the received data signal DATA. The tenth flip-flop 410 may receive the output values Q0 and Q90 of the eighth flip-flop 408 and the ninth flip-flop 409 as inputs. The eleventh flip-flop 411 may receive the output values Q0 and Q90 of the eighth flip-flop 408 and the ninth flip-flop 409 as inputs. The twelfth flip-flop 412 may receive the output values X1 and X2 of the tenth flip-flop 410 and the eleventh flip-flop 411.

The fifth and sixth clock signals CK0 and CK90 may be clock signals having different phases. The fifth clock signal CK0 may be the same as the first clock signal CK0, but the embodiment is not limited thereto. The sixth clock signal CK90 may be the same as the second clock signal CK90, but the embodiment is not limited thereto.

The first frequency detection signal FD_F in the full-rate mode may be an output value of the tenth flip-flop 410. The second frequency detection signal DC-FD_F in the full-rate mode may be the output value of the twelfth flip-flop 412.

FIG. 3 is a view for explaining a signal of the frequency detector, and FIG. 4 is a diagram for explaining a signal of the frequency detector when input jitter is large.

3 and 4 illustrate the case where the clock and data recovery circuit 10 of the present embodiment operates in the half-rate mode. Figures 3 and 4 illustrate a case where the clock frequency f _CK is greater than the data rate f _DATA . FIG. 3 shows a case where there is no input jitter, and FIG. 4 illustrates a case where there is an input jitter.

의 주기를 갖는 클록 신호를 생성할 수 있다. 3, unlike the full rate detector 400f, the signal Q0 and the signal Q90 are influenced by the data DATA, so that the data dependent glitches ). The half rate detector 400h includes the first XOR gate 431 and the second XOR gate 432 to remove the glitches through the XOR gates 431 and 432 so that the signals Z1 and Z2

Lt; RTI ID = 0.0 > of < / RTI >

However, when the input jitter is large, referring to FIG. 4, additional glitches occur in the signal Q0 and the signal Q90. Because of this, glitches are transmitted to the signals Z1 and Z2, and the first frequency detection signal FD_H does not output an accurate value, so accurate frequency detection may not be performed. Therefore, in this embodiment, the half-rate detecting unit 400h includes the seventh flip-flop 407, so that the signals Z3 and Z4 in the form of the purified signals Z1 and Z2 can be generated.

5 is a diagram for explaining an average value of the first frequency detection signal and the second frequency detection signal.

)(단위 ppm)에 대한 하프 레이트 검출부(400h)의 평균 출력을 시뮬레이션하고 있다. 주파수 에러(

)는 클록 주파수(f_CLK)와 데이터 레이트(f_DATA) 차이의 절대 값일 수 있다.FIG. 5 shows a graphical representation of the frequency error (in the case of 0.2-UI _PP ISI jitter, 200-MHz 0.4-UI sinusoidal jitter, 3.0 Gbps condition)

) (Unit ppm) of the half-rate detection unit 400h. Frequency error

) May be the absolute value of the difference between the clock frequency (f _CLK ) and the data rate (f _DATA ).

The average value E [FD_H] of the first frequency detection signal FD_H may be greater than the first threshold value + V _TH when the clock frequency f _CLK is faster than the data rate f _DATA . The average value E [FD_H] of the first frequency detection signal FD_H may be smaller than the second threshold value -V _TH when the clock frequency f _CLK is slower than the data rate f _DATA .

Therefore, the first frequency detection signal FD_H can be used as a valid indicator in frequency detection. But between Referring to Figure 5, in the dead zone region, the first average value of the frequency detection signal (FD_H) (E [[FD_H ]) is the first threshold value (+ V _TH) and the second threshold value (-V _TH) And can not function as a valid indicator.

When the index difference between the first bank code and the second bank code obtained by using the first frequency detection signal FD_H is not 1, that is, when the input jitter is severe, the second frequency detection signal DC- Can be used. That is, in the dead zone area, the second frequency detection signal DC-FD_H can function as an effective indicator.

The second frequency detection signal DC-FD_H also has an average value E [DC-FD_H] greater than the first threshold value + V _TH when the clock frequency f _CLK is faster than the data rate f _DATA And the average value E [DC-FD_H] may be less than the second threshold value -V _TH when the clock frequency f _CLK is slower than the data rate f _DATA .

FIG. 6 is a view for explaining a voltage-controlled oscillator according to an embodiment of the present invention, and FIG. 7 is a view for explaining the performance of a voltage-controlled oscillator according to an embodiment of the present invention.

6, a voltage controlled oscillator 100 according to an exemplary embodiment of the present invention includes a capacitor bank 110, a bandgap reference circuit (BGR) 120, a bias generator 130, (140).

The capacitor bank 110 is located at the rear end of the delay cell 140 and may include switching elements for determining the capacitor arrangement and the capacitor capacitance. The switching elements of the capacitor bank 110 can be switched and controlled by the bank code. According to one embodiment, the bank code (Bank_con <4: 0>) may be composed of 5 bits. A 5-bit bank code can represent, for example, a bank code having 32 respective indices.

The bias generator 130 may include a temperature compensation circuit. A temperature compensation circuit provides a bias current (I _VCO) required for the voltage controlled oscillator 100, the bias current (I _VCO) is CTAT current (Complementary to Absolute Temperature) (I _CTAT), PTAT current (Proportional to Absolute Temperature) (I _PTAT ), and a process compensation current I _PROC . The temperature compensation circuit can be configured to satisfy the following equations (1) and (2).

[Equation 1]

I _VCO = I _CTAT + I _PTAT - I _PROC

&Quot; (2) &quot;

I _PROC = V _BG / (V _{TH, PMOS} + V _{TH, NMOS} )

Since the process-compensating current I _PROC adjusts the bias current I _VCO according to the threshold voltages of the NMOS and PMOS, spare banks for process variations are not required. The CTAT current (I _CTAT ) and the sum of the PTAT currents (I _CTAT + I _PTAT ) compensate for temperature dependent variations in the process compensation current (I _PROC ).

Referring to FIG. 7, the measurement result of the frequency of the voltage-controlled oscillator 100 according to the temperature is shown. The voltage-controlled oscillator 100 was measured at a clock rate of 1.5 GHz and a temperature change of 20 degrees Celsius (+) to 120 degrees Celsius, and the frequency variation value measured at the free-running VCO (VCO) 4.67%.

8 is a diagram for explaining a code determination algorithm according to an embodiment of the present invention.

The code determination algorithm of FIG. 8 can be applied to the bank code generation of the course FLL. Similarly, the code determination algorithm of FIG. 8 may also be applied to the oscillator control code generation of the fine FLL.

First, the output of the frequency detector 400 is counted (S101), and the clock frequency f _CK is compared with the data rate f _DATA (S102).

If the clock frequency f _CK is smaller than the data rate f _DATA , the current value f _CODE of the code and the past value f _CODE 'of the code are compared (S103). The value of the code may be an index value.

If the past value f _CODE 'of the code is larger, the toggle value is counted and the current value f _CODE of the code is stored (S104), and 1 is added to the current value f _CODE of the code ).

If the current value f _{CODE of the} code is larger in step 103, 1 is added to the current value f _CODE of the code (S105).

Next, it is checked in step S109 whether the toggle count is 2 or not. When the toggle count reaches 2, the FLL process ends. If the toggle count is not 2, the process returns to step S101.

If the frequency f _CK is greater than the data rate f _DATA in step S102, the current value f _CODE of the code is compared with the past value f _CODE 'of the code (S106).

If the current value f _CODE of the code is larger, the toggle value is counted, the current value f _CODE of the code is stored (S107), and 1 is subtracted from the current value f _CODE of the code (S108).

If the past value f _CODE 'of the code is larger in step S106, 1 is subtracted from the current value f _CODE of the code (S108).

Next, it is checked in step S109 whether the toggle count is 2 or not. When the toggle count reaches 2, the FLL process ends. If the toggle count is not 2, the process returns to step S101.

To summarize the above algorithm briefly, the frequency code value is increased when the frequency of the clock is slower than the frequency of the data, and the frequency code value is decreased in the opposite case. At this time, when the direction of the increase / decrease of the frequency code is changed (toggling), the toggle count is increased and the corresponding frequency code is stored. Finally, when the direction of increase / decrease of the frequency code is changed twice, the target frequency is included in the range of the stored two frequency codes.

In the conventional frequency acquisition algorithm, since the frequency search is started from a small value and the target frequency is found to be long, the algorithm of the present embodiment starts from the center code of the predetermined range and searches for the target frequency, There is an effect to prevent.

9 is a diagram for explaining a process of generating a first bank code and a second bank code according to a first frequency detection signal.

Referring to FIG. 9, the course FLL is performed in a state where the oscillator control voltage V _CTRL is fixed (V _DD / 2 in this embodiment).

9 shows an example in which there is a large input jitter, even if the algorithm of FIG. 8 is performed using the first frequency detection signal in the course FLL, the adjacent first bank code Bank1 and the second bank code Bank2 ) Can not be derived. Therefore, the index difference between the derived first bank code (Bank1) and the second bank code (Bank2) exceeds one. The index difference between the first bank code (Bank1) and the second bank code (Bank2), which is illustratively shown in Fig. 9, is four. The first bank code (Bank1), the second bank code (Bank2), and the interbank codes obtained in FIG. 9 may be referred to as deadzone banks.

10 is a diagram for explaining a process of resetting the first bank code and the second bank code according to the second frequency detection signal.

Referring to FIG. 10, when the second frequency detection signal is applied to the algorithm of FIG. 8 based on the dead zone bank range obtained in FIG. 9, the first bank code (Bank 1) and the second bank code (Bank 2) are acquired . The first bank code Bank1 and the second bank code Bank2 have an index difference of 1 and the first bank code Bank1 and the second bank code Bank2 are candidates for the bank code.

11 is a diagram for explaining a process of generating a first oscillator control code and a second oscillator control code.

The oscillator control code generation module 210 may generate a first oscillator control code 901 for the first bank code Bank1 and the lock detector 220 may generate a first oscillator control code 901 for the oscillator control voltage regulator 700 and the comparator 300, It can be confirmed through the first oscillator control code 901 that the phase can be fixed. 11, since the oscillator control voltage V _CTRL according to the first oscillator control code 901 is within the reference voltage range (V _L to V _H ) of the comparator, the first bank code Bank 1 and the first oscillator control The code 901 is finally selected, and frequency fixing can be performed.

The oscillator control code generation module 210 may generate a second oscillator control code 902 for the second bank code Bank2 and the lock detector 220 may generate an oscillator control voltage regulator 700 and a comparator 800, It can be confirmed through the second oscillator control code 902 that the phase can be fixed. 11, because the oscillator control voltage V _CTRL according to the second oscillator control code 902 is outside the reference voltage range (V _L to V _H ) of the comparator, the second bank code Bank 2 and the second oscillator control The code 902 is excluded from the final selection.

When the oscillator control voltage V _CTRL is finally within the reference voltage range (V _L to V _H ) when the PLL process is finally switched, the clock and data recovery circuit 10 continuously restores the data regardless of the temperature change It is judged as possible.

In Figure 11 V _MIN to V _MAX represents the available range of the oscillator control voltage _{(V CTRL), (V L} -V MIN) K VCO or (V _MAX -V _H) K _VCO clock and data recovery circuit with the temperature Is the minimum value of the VCO frequency variation that can be covered by the antenna 10.

12 is a diagram for explaining simulation results of a clock and data recovery circuit according to an embodiment of the present invention.

According to the algorithm, it can be confirmed that the difference between the clock frequency and the data transfer rate is less than 5000 ppm through the course FLL and the fine FLL, and then the PLL is converted to the phase lock.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are illustrative and explanatory only and are intended to be illustrative of the invention and are not to be construed as limiting the scope of the invention as defined by the appended claims. It is not. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10: Clock and data recovery circuit
100: voltage-controlled oscillator
200: Digital circuit part
300: comparator
400: Frequency detector
500: phase detector
600: charge pump
700: Oscillator control voltage regulator
800: Loop filter

Claims (8)

A voltage controlled oscillator including a capacitor bank;
A digital circuit for generating a bank code, which is a control signal for the capacitor bank, and generating an oscillator control code according to the bank code; And
A comparator for comparing the oscillator control voltage generated according to the oscillator control code to an acceptable range; And
And an oscillator control voltage regulator for regulating the oscillator control voltage according to the oscillator control code,
And outputting a restored clock signal and a restored data signal according to the bank code and the oscillator control code when the oscillator control voltage is within the allowable range,
Clock and data recovery circuit. The method according to claim 1,
And a frequency detector for outputting a first frequency detection signal, which is a logic value obtained by comparing a clock frequency and a data rate, and a second frequency detection signal, which is a flip flop output value of the first frequency detection signal, to the digital circuitry
Clock and data recovery circuit. 3. The method of claim 2,
The frequency detector includes a half-rate detector,
The half-rate detector
A first flip-flop in which a first clock signal is input to a data (D) port and a received data signal is input to a clock (clk) port;
A second flip-flop in which a second clock signal is input to a data (D) port and a received data signal is input to a clock (clk) port;
A third flip-flop in which a third clock signal is input to a data (D) port and a received data signal is input to a clock (clk) port;
A fourth flip-flop in which a fourth clock signal is input to a data (D) port and a received data signal is input to a clock (clk) port;
A first XOR gate to which the output values of the first flip-flop and the second flip-flop are input;
A second XOR gate to which the output values of the third flip-flop and the fourth flip-flop are input;
A fifth flip-flop in which the output value of the first XOR gate is input to the data port and the output value of the second XOR gate is input to the clock port;
A sixth flip-flop in which the output value of the first XOR gate is input to the clock port and the output value of the second XOR gate is input to the data port; And
And a seventh flip-flop in which the output value of the fifth flip-flop is input to the data port and the output value of the sixth flip-flop is input to the clock port,
The first, second, third, and fourth clock signals are clock signals having different phases,
The first frequency detection signal is an output value of the fifth flip-flop,
Wherein the second frequency detection signal is an output value of the seventh flip-
Clock and data recovery circuit. 3. The method of claim 2,
The frequency detector includes a full-rate detector,
The full-rate detector
An eighth flip flop in which a fifth clock signal is input to a data (D) port and a received data signal is input to a clock (clk) port;
A ninth flip-flop in which a sixth clock signal is input to a data (D) port and a received data signal is input to a clock (clk) port;
A tenth flip-flop in which the output value of the eighth flip-flop is input to the data port and the output value of the ninth flip-flop is input to the clock port;
An eleventh flip-flop in which the output value of the eighth flip-flop is input to the clock port and the output value of the ninth flip-flop is input to the data port; And
And a twelfth flip-flop in which the output value of the tenth flip-flop is input to the data port and the output value of the eleventh flip-flop is input to the clock port,
Wherein the fifth and sixth clock signals are clock signals having different phases,
The first frequency detection signal is an output value of the tenth flip-flop,
Wherein the second frequency detection signal is an output value of the twelfth flip-
Clock and data recovery circuit. 3. The method of claim 2,
A phase detector receiving the data and clock signals and outputting a phase difference signal;
A charge pump for supplying charge according to the phase difference signal; And
And a loop filter coupled to the charge pump or the oscillator control voltage regulator according to a loop select signal
Clock and data recovery circuit. 6. The method of claim 5,
Wherein the loop filter is connected to the oscillator control voltage regulator in a frequency fixing process and is connected to the charge pump in a phase locking process,
Clock and data recovery circuit. 3. The method of claim 2,
The digital circuit section
Generates a first bank code and a second bank code in accordance with the first frequency detection signal,
Generating a first oscillator control code for the first bank code,
Generating a second oscillator control code for the second bank code,
And a bank code and an oscillator control code corresponding to the oscillator control voltage within the allowable range are selected through the comparator
Clock and data recovery circuit. 8. The method of claim 7,
When the index difference between the first bank code and the second bank code is not 1,
And resetting the first bank code and the second bank code in accordance with the second frequency detection signal,
Clock and data recovery circuit.

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