KR101808338B1 - Display device and method of controlling gate pulse thereof - Google Patents

Abstract

The present invention relates to a display device and a method for controlling a gate pulse thereof, wherein a voltage of the gate pulse is lowered from a gate high voltage to a first gate low voltage at a falling edge of the gate pulse, And maintains the second gate low voltage for a predetermined period after rising to the gate low voltage.

Description

DISPLAY DEVICE AND METHOD OF CONTROLLING GATE PULSE THEREOF FIELD OF THE INVENTION [0001]

The present invention relates to a display device including a gate driving circuit sequentially supplied to gate lines and a gate pulse control method thereof.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. The liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, and the like, and is rapidly applied to a television, thereby quickly replacing a cathode ray tube. The liquid crystal display device forms a liquid crystal layer having anisotropic permittivity of upper and lower transparent substrates and changes the molecular arrangement of the liquid crystal material by adjusting the intensity of an electric field formed in the liquid crystal layer according to video data to display a desired image.

A driving circuit of a liquid crystal display device includes a data driving circuit for supplying a data voltage of video data to data lines of a display panel and a gate driving circuit for applying a gate pulse (or a scanning pulse) synchronized with the data voltage to the gate lines And a gate driving circuit for sequentially supplying the driving signals to the gate driver circuit.

The gate driving circuit includes gate pulses swinging between a gate high voltage (VGH) and a gate low voltage (VGL) at n-th (n is a natural number) and n + 1 gate lines (Gn, Gn + 1) Respectively. The gate drive circuit can lower the gate high voltage (VGH) at the falling edge of the gate pulse as shown in FIG. 1, in order to reduce? Vp of the liquid crystal cell voltage due to the parasitic capacitance of the TFT. In the method of modulating the gate pulse, it is possible to reduce the flicker in which the luminance difference is displayed in accordance with the polarity in the liquid crystal cells in which the positive data voltage and the negative data voltage are charged by decreasing? Vp. However, when the gate pulse is modulated as shown in Fig. 1, the polling edge voltage of the gate pulse is modulated in two steps, and thus the polling edge voltage is delayed. The delay of the poling edge voltage of such a gate pulse is difficult to be applied to a large-area high-resolution liquid crystal display device because the RC delay becomes larger on a high resolution large screen.

The present invention provides a display device and a gate pulse control method for minimizing a polling edge delay of a gate pulse.

A display device of the present invention includes: a display panel in which data lines and gate lines cross each other; A data driving circuit for supplying a data voltage to the data lines; And a gate driving circuit for sequentially supplying a gate pulse synchronized with the data voltage to the gate lines. Wherein the voltage of the gate pulse rises from a second gate low voltage to a gate high voltage at a rising edge of the gate pulse and is lowered from the gate high voltage to a first gate low voltage at a falling edge, Up to the second gate-low voltage and maintains the second gate-low voltage for a predetermined period of time

The voltage of the gate pulse rises from the second gate low voltage to the gate high voltage at the rising edge.

The gate high voltage is a voltage between 15V and 25V, the first gate low voltage is a voltage lower than -10V and lower than -5V, and the second gate low voltage is a voltage lower than -5V and lower than 0V.

Wherein the gate driving circuit includes: a level shifter for shifting a voltage of a gate shift clock to output a clock signal; And a shift register formed on the substrate of the display panel and supplying a gate pulse to the gate lines of the display panel by shifting a gate start pulse according to a clock signal input from the level shifter.

The display device generates a gate timing control signal including the gate shift clock and a polling edge control signal synchronized with the polling edge of the gate shift clock to control the operation timing of the gate driving circuit and generate a data timing control signal And a timing controller for controlling the operation timing of the data driving circuit.

Wherein the level shifter supplies the gate high voltage to the output node in response to a high logic voltage of the gate shift clock to raise the voltage of the clock signal input to the shift register to the gate high voltage; A second transistor for lowering an output node voltage of the level shifter to the first gate low voltage in response to a voltage applied to its gate electrode; A third transistor for supplying the second gate-low voltage to an output node of the level shifter in response to a low logic voltage of the gate shift clock; An AND gate for ANDing the polling edge control signal and the gate shift clock; And a logic portion for turning on the second transistor in response to the output of the AND gate.

The display panel is one of a liquid crystal display (LCD) and an organic light emitting diode (OLED) display panel.

Wherein the gate pulse control method of the display device comprises sequentially supplying a gate pulse synchronized with a data voltage to the data lines to the gate lines, Goes low from the high voltage to the first gate low voltage, and then rises from the first gate low voltage to the second gate low voltage.

The present invention raises the gate voltage from the first gate low voltage to the second gate low voltage after lowering the gate voltage from the gate high voltage to the first gate low voltage at the falling edge of the gate pulse. As a result, the present invention can minimize the polling edge delay of the gate pulse.

1 is a waveform diagram showing a conventional gate pulse. FIG. 2 is a block diagram schematically showing a shift register of a GIP gate driving circuit. FIG.
2 is a waveform diagram showing gate pulses according to the first embodiment of the present invention.
3 is a waveform diagram showing gate pulses according to a second embodiment of the present invention.
4 is a block diagram showing a display device according to an embodiment of the present invention.
5 is a circuit diagram showing the level shifter shown in FIG. 4 in detail.
6 is a waveform diagram showing an input / output waveform of the level shifter shown in FIG.
FIG. 7 is a waveform diagram showing an experimental result in which the poling edge delay of the gate pulse is compared between the prior art and the present invention.
8 is a waveform diagram in which the gate pulse of the prior art shown in FIG. 7 is overlapped with the gate pulse of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The display device of the present invention can be implemented by any one of a liquid crystal display (LCD) and an organic light emitting diode (OLED). The liquid crystal display device can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The liquid crystal mode applicable in the present invention may be a vertical field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode or a horizontal field driving method such as IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) Mode, and all currently known liquid crystal modes are applicable.

A gate pulse control method of the present invention sequentially supplies gate pulses to gate lines of a display panel. The gate pulses may be non-overlapping as shown in FIG. 2 or may overlap as shown in FIG. The gate pulse swings between the gate high voltage (VGH) and the gate low voltage (VGL). The gate-low voltage VGL is a multi-step voltage of the first and second gate-low voltages VGL1 and VGL2. The voltage of the gate pulse rises from the second gate low voltage VGL2 to the gate high voltage VGH at the rising edge. The voltage of the gate pulse is lowered from the gate high voltage VGH to the first gate low voltage VGL1 at the falling edge and then increased from the first gate low voltage VGL1 to the second gate low voltage VGL2, And maintains the second gate-low voltage VGL2 for a period of time.

The first gate low voltage VGL1 is supplied to the gate line prior to the second gate low voltage VGL2 to rapidly discharge the voltage of the gate line to shorten the polling edge time of the gate pulse. The first gate-low voltage VGL1 is set to a voltage lower than the second gate-low voltage VGL2. The second gate low voltage VGL2 is supplied to the gate line immediately after the first gate low voltage VGL1 is supplied to the gate line to raise the voltage of the gate line. The gate high voltage VGH is a scan activation voltage set to a voltage equal to or higher than the threshold voltage of the TFT formed in the TFT array of the display panel and can be set to a voltage between 15V and 25V in the case of an LCD. The first gate low voltage VGL1 may be set to, for example, -8 V as a scan inactivation voltage lower than -10 V to -5 V lower than the threshold voltage of the TFT formed in the TFT array of the display panel. The second gate low voltage VGL2 may be set to a scan inactivation voltage lower than the threshold voltage of the TFT formed in the TFT array of the display panel by -5 V or lower but lower than 0 V, for example, -5 V in the case of the LCD. The second gate-low voltage VGL2 may be set to the same voltage as the conventional gate-low voltage.

4 shows a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 4, the display device of the present invention includes a display panel 10, a data driving circuit, a GIP (Gate In Panel) gate driving circuit, a timing controller 11, and the like.

The display panel 10 may be implemented as a display panel of a flat panel display device such as a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. Hereinafter, the display panel 10 will be described with the liquid crystal display panel as its center, but it is not limited to the liquid crystal display panel. In the TFT array substrate of the display panel 10, data lines, gate lines intersecting with data lines, TFTs formed at intersections of data lines and gate lines, TFTs connected to TFTs, A liquid crystal cell Clc driven by an electric field between the pixel electrodes 2, and a storage capacitor Cst. On the color filter array substrate of the display panel 10, a color filter array including a black matrix and a color filter is formed. The common electrode 2 is formed on the color filter array substrate in the vertical field driving mode such as the TN mode and the VA mode and is formed on the TFT array substrate together with the pixel electrode in the horizontal electric field driving mode such as the IPS mode and the FFS mode . On the TFT array substrate of the display panel 10 and the color filter array substrate, a polarizing plate whose optical axis is orthogonal is attached, and an alignment film for setting a pre-tilt angle of the liquid crystal is formed at the interface with the liquid crystal layer.

The data driving circuit includes a plurality of source drive ICs (Integrated Circuits) 12. The source drive ICs 12 receive the digital video data (RGB) from the timing controller 11. The source drive ICs 12 convert the digital video data RGB to a positive / negative analog data voltage in response to a source timing control signal from the timing controller 11, To the data lines of the display panel 10. The source drive ICs 12 may be connected to the data lines of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. 4 shows an example in which the source drive ICs are mounted on a TCP (Tape Carrier Package) and bonded to a TFT array substrate of a printed circuit board (PCB) 14 and a display panel 10 in a TAB manner.

The GIP gate driving circuit includes a level shifter 21 mounted on the PCB 14 and a shift register 22 formed on the lower glass substrate of the display panel 10 together with the TFT array.

The level shifter 21 receives gate timing control signals such as the gate shift clocks GLCK1 to GLCK1 to n and the polling edge control signal FLK from the timing controller 11. [ The level shifter 21 is supplied with a drive voltage such as a gate high voltage VGH and first and second gate low voltages VGL from a DC-DC converter (not shown). The gate shift clocks (GCLK1 to GCLKn) swing between 3.3V (high logic voltage) and 0V (low logic voltage) as n phase clock signals having a predetermined phase difference. The level shifter 21 shifts the high logic voltage of the gate shift clocks GLCK1 to GNK inputted from the timing controller 11 to the gate high voltage and outputs the high logic voltage in response to the polling edge control signal FLK Shifts the falling edge voltage of the gate shift clocks GLCK1 to GLCK1 to the first gate low voltage VGL1. Then, the level shifter 21 shifts the low logic voltage of the gate shift clocks GLCK1-n to the second gate low voltage VGL2.

The shift register 22 shifts the gate start pulse inputted from the timing controller 11 in accordance with the clock signals CLK1 to CLK inputted from the level shifter 21, Respectively.

On the other hand, the GIP gate driving circuit can be replaced with a gate TCP in which a shift register and a level shifter are integrated. The gate TCP can be TAB bonded to the TFT array of the display panel.

The timing controller 11 is mounted on the PCB 14. The timing controller 11 receives digital video data RGB from an external host computer via an interface such as a low voltage differential signaling (LVDS) interface or a transition minimized differential signaling (TMDS) interface. The timing controller 11 transmits digital video data (RGB) input from the host computer to the source drive ICs 12.

The timing controller 11 receives timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a main clock MCLK from a host computer through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 11 generates timing control signals for controlling the operation timing of the source drive ICs 12 and the GIP gate drive circuit on the basis of the timing signal from the host computer. The timing control signals include a gate timing control signal for controlling the operation time of the gate drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes a gate start pulse GSP, gate shift clocks GCLK1 to GCLKn, a polling edge control signal FLK, a gate output enable signal GOE, and the like. The gate start pulse GSP is input to the shift register 22 to control the timing of the first gate pulse. The gate shift clocks GCLK1 to GCLKn are level shifted by the level shifter 21 and then input to the shift register 22 and used as a clock signal for shifting the gate start pulse GSP. The falling edge control signal FLK controls the modulation timing of the falling edge voltage of the gate shift clocks GCLK1 to GCLK. The gate output enable signal GOE controls the output timing of the level shifter 21.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 12. [ The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 12 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

5 is a circuit diagram showing the level shifter shown in FIG. 4 in detail. 6 is a waveform diagram showing an input / output waveform of the level shifter shown in FIG.

5 and 6, the level shifter 21 includes n modulation circuits for modulating the voltages of the respective clock signals CLK1 through n, and each of the modulation circuits includes an AND gate 31, A second transistor 32, and first to third transistors T1 to T3. 5 illustrates a first modulation circuit for shifting the voltage level of the first gate shift clock GCLK1. The other modulation circuits have substantially the same circuit configuration as the first modulation circuit, and shift the voltage of each of the second to n-th gate shift clocks GCLK2 to nCLK. The transistors T1 to T3 may be implemented as an n-type MOS TFT (Metal Oxide Semiconductor TFT).

Hereinafter, the circuit configuration and operation of the first modulation circuit will be described.

The first transistor T1 supplies the gate high voltage VGH to the output node in response to the high logic voltage of the first gate shift clock GCLK1 to generate the first clock signal CLK1 input to the shift register 22 Raises the voltage to the gate high voltage VGH. The first transistor T1 is turned off in response to the low logic voltage of the first gate shift clock GCLK1. A gate high voltage VGH is applied to the source electrode of the first transistor T1 and a drain electrode of the first transistor T1 is connected to the output node of the level shifter 21. [ The first gate shift clock signal GCLK1 is input to the gate electrode of the first transistor T1.

The AND gate 31 ANDs the polling edge control signal FLK with the first gate shift clock GCLK1 and supplies the result to the logic section 32. [ The falling edge control signal FLK is generated as a pulse synchronized with the falling edge of the first gate shift clock GCLK1 as shown in FIG. Thus, the output of the AND gate 31 defines the polling edge timing of the gate shift clock GCLK1.

The logic part 32 turns on the second transistor T2 in response to the output of the AND gate 31 and supplies the first gate low voltage VGL1 to the output node of the level shifter 21 Thereby lowering the voltage of the first clock signal CLK1 to the first gate low voltage VGL1. The logic unit 32 may adjust the on / off timing of the second transistor T2 by adjusting the gate voltage of the second transistor T2 to adjust the channel current of the second transistor T2. The first gate low voltage VGL1 is applied to the drain electrode of the second transistor T2 and the source electrode of the second transistor T2 is connected to the output node of the level shifter 21. [ The gate electrode of the second transistor (T2) is connected to the output terminal of the logic section (32).

The third transistor T3 supplies the second gate low voltage VGL2 to the output node of the level shifter 21 in response to the low logic voltage of the first gate shift clock GCLK1 to generate the voltage of the clock signal CLK1 And is raised from the first gate low voltage VGL1 to the second gate low voltage VGL2. The third transistor T3 is turned off in response to the high logic of the first gate shift clock GCLK1. The first gate shift clock signal GCLK1 is applied to the gate electrode of the third transistor T3. The second gate low voltage VGL2 is applied to the drain electrode of the third transistor T3 and the source electrode of the third transistor T3 is connected to the output node of the level shifter 21. [

On the other hand, the output of the AND gate 31 may be directly applied to the gate electrode of the third transistor T3. In this case, the logic section 32 may be omitted.

FIG. 7 is a waveform diagram showing an experimental result in which the poling edge delay of the gate pulse is compared between the prior art and the present invention. 8 is a waveform diagram in which the gate pulse of the prior art shown in FIG. 7 is overlapped with the gate pulse of the present invention.

The present inventors conducted a simulation to verify the effect of the present invention. As a result, in the conventional gate pulse shown in FIGS. 7 and 8, the polling time at which the gate voltage is lowered from the gate high voltage (VGH) to the gate low voltage (VGL) is measured to be about 3.79 μsec, The pulse has a polling time at which the gate voltage is lowered from the gate high voltage (VGH) to the first gate low voltage (VGL1) at about 2.84 mu sec. Therefore, according to the present invention, the poling time delay period of the gate pulse can be shortened by about 1 mu sec as compared with the prior art. 7 and 8, CLK1 (RA) is a first clock signal output from the level shifter of the prior art, and G1 (RA) is supplied from the shift register of the related art to the first gate line of the display panel 10 Represents a first gate pulse. CLK1 is a first clock signal output from the level shifter 21 of the present invention. G1 is a first clock signal supplied from the shift register 22 of the present invention to the first gate line of the display panel 10, . In the simulation, the pulse width W2 in the gate pulse of the present invention was set smaller than that (W1) of the prior art.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 12: Source drive IC
14: PCB 21: Level shifter
22: Shift register 31: AND gate
32: Logic part T1 to T3: Transistor

Claims (10)

A display panel in which data lines and gate lines cross each other;
A data driving circuit for supplying a data voltage to the data lines; And
And a gate driving circuit for sequentially supplying a gate pulse synchronized with the data voltage to the gate lines,
Wherein the voltage of the gate pulse rises from the second gate low voltage to the gate high voltage at the rising edge of the gate pulse after being input to the second gate low voltage, Low voltage to a first gate low voltage lower than the low voltage, and then rises from the first gate low voltage to the second gate low voltage to maintain the second gate low voltage until the next rising edge.
delete The method according to claim 1,
The gate high voltage is a voltage between 15V and 25V,
The first gate low voltage is a voltage lower than -10 V and lower than -5 V,
And the second gate-low voltage is a voltage lower than -5V and lower than 0V.
The method according to claim 1,
The gate drive circuit
A level shifter for shifting a voltage of the gate shift clock and outputting a clock signal; And
And a shift register formed on the substrate of the display panel and supplying a gate pulse to the gate lines of the display panel by shifting a gate start pulse according to a clock signal input from the level shifter, .
5. The method of claim 4,
A gate timing control signal including the gate shift clock and a polling edge control signal synchronized with a polling edge of the gate shift clock to control the operation timing of the gate driving circuit and generate a data timing control signal, Further comprising a timing controller for controlling an operation timing of the display device.
6. The method of claim 5,
The level shifter includes:
A first transistor for supplying the gate high voltage to the output node in response to a high logic voltage of the gate shift clock to raise the voltage of the clock signal input to the shift register to the gate high voltage;
A second transistor for lowering an output node voltage of the level shifter to the first gate low voltage in response to a voltage applied to its gate electrode;
A third transistor for supplying the second gate-low voltage to an output node of the level shifter in response to a low logic voltage of the gate shift clock;
An AND gate for ANDing the polling edge control signal and the gate shift clock; And
And a logic portion for turning on the second transistor in response to the output of the AND gate.
The method according to claim 1,
Wherein the display panel is one of a liquid crystal display (LCD) and an organic light emitting diode (OLED) display panel.
A method of controlling a gate pulse of a display device including a display panel in which data lines and gate lines cross each other,
Sequentially supplying a gate pulse synchronized with a data voltage to the data lines to the gate lines,
Wherein the voltage of the gate pulse rises from the second gate low voltage to the gate high voltage at the rising edge of the gate pulse after being input to the second gate low voltage, And the second gate low voltage is increased from the first gate low voltage to the second gate low voltage to maintain the second gate low voltage until the next rising edge after lowering to the first gate low voltage lower than the low voltage. Pulse control method.
delete 9. The method of claim 8,
The gate high voltage is a voltage between 15V and 25V,
The first gate low voltage is a voltage lower than -10 V and lower than -5 V,
And the second gate low voltage is a voltage lower than -5V and lower than 0V.

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