KR101807850B1 - Multi-Chip System Clock Signal Distribution Synchronization Technology with In-Phase Clock Lines - Google Patents

Abstract

The present invention discloses a method for synchronizing a clock signal which designs a ring oscillator with a stable fractal structure. The method for synchronizing a clock signal comprises the following steps of: receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal; oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip; and outputting the first clock signal and the second clock signal as the clock signal having the same frequency and the same phase. The clock line connects three ends of the first chip and the second chip having the same fractal structure.

Description

TECHNICAL FIELD [0001] The present invention relates to a multi-chip system clock signal distribution and synchronization method using an in-phase clock line,

The present invention relates to a synchronization method of a multi-chip system. More particularly, to a method for distributing and synchronizing clock signals in a multi-chip system using an in-phase clock line.

The data and the clock used to recognize the data are generally set to an optimal state through a certain training process when the system is initialized. However, since the environment in which the initialization has progressed, such as the heat generated during the operation of the system and the data pattern variation, affects the operation of the system, it is possible to optimally adjust the phase of the clock even while the system is operating And a circuit for implementing it are required.

An oscillator circuit has some problems in generating a stable oscillation frequency. As the size of a conventional oscillator circuit increases, a jitter phenomenon occurs in which the frequency instantaneously shakes, and a clock skew phenomenon occurs in which the phase is delayed.

A ring-type oscillator is widely used as a clock generation circuit due to its efficiency, wide frequency range, and small area. The oscillation frequency of the ring oscillator is usually calculated according to the following equation (1).

Where N represents the number of delay cells, and td represents the delay time of one delay cell. Since the oscillation frequency of the ring oscillator is inversely proportional to N, there are limitations in operation reliability and area when many delay stages are used.

In addition, stability in the circuit generating and distributing the high-speed clock frequency of the conventional GHz class is a major factor in performance. However, since there is no oscillator using only the inverter, the oscillator is designed in a fractal structure to generate a high clock frequency .

With the development of System on Chip (SoC) design technology today, the clock signals of integrated circuits constituting the system are mostly GHz, and the operating speed is continuously increasing. Ultra high-speed clock generation and distribution is a very important technology in integrated circuit design. If clock skew occurs, the operation of a system that requires a clock signal may fail. Currently, it is preferred to use PLL (Phase Locked Loop) circuit to detect the phase difference of the generated clock signal and to solve the synchronization problem of the circuit. However, the PLL circuit is complicated in structure and has a burden of increasing the chip size due to the wiring area.

In this disclosure, a multi-chip system clock signal distribution and synchronization scheme using an in-phase clock line is proposed. The proposed scheme uses a ring oscillator circuit to simplify the connection of the same phase to the clock line, so that the clock skew generated by a plurality of chips in the system depends on the difference of the power supply voltage between the chips and the error caused by the asynchronous operation As much as possible. In a CMOS ring oscillator, all nodes operate at the same frequency when oscillating. This structure is very effective for frequency-shift keying by realizing network-wide clock signal synchronization even with partial voltage and temperature differences, and by increasing the number of inverters without the addition of a separately designed circuit. In addition, if multiple identical ring oscillators are designed to have the same phase, the ring oscillator in the entire chip will inevitably have the same frequency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a ring oscillator having a stable fractal structure.

In addition, according to the present invention, a jitter phenomenon in which an unstable frequency instantly occurs and a clock skew phenomenon in which a phase delay occurs can be reduced.

It is to be understood that the technical objectives of the present invention are not limited to the above-mentioned technical objects and other technical objects which are not mentioned in the following description are to be understood from the following description, It will be understood clearly by those with knowledge.

The method of synchronizing a clock signal according to an exemplary embodiment of the present invention includes: receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal; Oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip; And outputting the first clock signal and the second clock signal as a clock signal having the same frequency and the same phase, wherein the clock line includes a first chip having the same fractal structure, And is a clock line that connects the three ends to each other.

Preferably, the fractal structure is a fractal structure in which an inverter chain in which odd number of inverters are connected in series constitutes one fractal triangle.

Preferably, the first voltage applied to the first chip and the second voltage applied to the second chip are different voltages.

Preferably, the first chip and the second chip are ring oscillators each consisting of thirty inverters.

Advantageously, said first chip and said second chip are operated at a GHz frequency range.

According to another aspect of the present invention, there is provided a clock skew compensation method comprising: receiving a voltage source in a first chip for generating a first clock signal and a second chip for generating a second clock signal; Oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip; And adjusting the frequency and phase of the first clock signal and the second clock signal, wherein the clock line connects the three ends of the first chip and the second chip having the same fractal structure to each other The clock is the clock line.

According to still another aspect of the present invention, there is provided a multichip phase correction method comprising: receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal; Oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip; And adjusting a frequency and a phase of the first clock signal and the second clock signal to a third clock signal, wherein the clock line includes a first chip having the same fractal structure and three ends It is a clock line that connects the stages to each other.

Preferably, the third clock signal is the same signal as any one of the first clock signal and the second clock signal.

The clock signal synchronization method according to an embodiment of the present invention can achieve overall synchronization in a very simple manner without a circuit added in a plurality of chips.

Also, the clock signal synchronization method according to an embodiment of the present invention has an advantageous effect that the complexity of the circuit is not increased, while the problem of clock signal asynchronization is improved in a plurality of chips operating at super high speed.

Also, according to the clock signal synchronization method according to an embodiment of the present invention, errors due to clock skew and asynchronous operation can be minimized.

1 is a conceptual diagram of a CMOS ring oscillator according to an embodiment of the present invention.
2 is a schematic diagram of a CMOS ring oscillator according to an embodiment of the present invention.
3 is a block diagram of a circuit according to one embodiment of the present invention.
4 is a conceptual diagram of a multi-layer structure according to an embodiment of the present invention.
5 is a diagram illustrating a TTL ring oscillator network between two chips according to an embodiment of the present invention.
6 is a flowchart illustrating a synchronization process of a clock signal according to an embodiment of the present invention.
7 is a graph showing an output waveform simulation of a ring oscillator according to an embodiment of the present invention.
8 is a graph showing measured values of an output waveform of a ring oscillator according to an embodiment of the present invention.
9 is a graph showing an output waveform simulation of a ring oscillator according to an embodiment of the present invention.
10 is a graph showing measured values of an output waveform of a ring oscillator according to an embodiment of the present invention.
11 is a graph showing a skew phenomenon simulation according to an embodiment of the present invention.
12 is a graph showing skew phenomenon measured values according to an embodiment of the present invention.
FIG. 13 is a graph illustrating a clock skew value measured according to a voltage variation according to an embodiment of the present invention.
14 is a graph showing an output waveform simulation of a ring oscillator according to an embodiment of the present invention.
15 is a graph showing measured values of an output waveform of a ring oscillator according to an embodiment of the present invention.
16 is a graph showing the measured clock skew value according to voltage variation according to an embodiment of the present invention.
17 is a diagram illustrating a layout of a CMOS ring oscillator according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the same reference numerals will be used for the same constituent elements in the drawings, and redundant explanations for the same constituent elements will be omitted.

1 is a conceptual diagram of a CMOS ring oscillator according to an embodiment of the present invention.

As shown in FIG. 1, the structure of the ring oscillator is an odd number of inverters connected in series. In the simplest case, a ring oscillator consisting of three inverters has a phase difference of 120 °, but it can have the same frequency and phase at any point when passing through three inverters. In this structure, one cell is composed of three inverters and n (n is a natural number) feedback loops. Therefore, it is a fractal structure that can be extended to two or three dimensions.

For example, an inverter chain in which an odd number of inverters are connected in series in a fractal structure can constitute one fractal triangle. For example, in FIG. 1, there may be one inverter between node 1 and node 6, and there may be three, five, or more odd number of inverters in some cases. Due to the presence of an odd number of inverters, the input and output ends of the inverter can have different values.

As shown in Fig. 1, in the large triangle 1-2-3, a triangle 4-5-6 having a smaller size and a triangle 7-8-9 having a smaller size continue to have the same structure And a fractal structure that can be extended can be confirmed.

The relatively small triangle (10-11-12) can be configured as an inverter for each basic cell, and the oscillator can be configured using CMOS as an extension of the basic triangle (10-11-12).

For example, for an inverter between node 1 and node 6 in a structure composed of triangles (1-6-5), node 1 may be an input signal, and node 6 may be an output signal.

The ring oscillator of the fractal structure in the present invention can generate a high clock frequency of GHz level and can distribute the clock frequency. Fractal ring oscillator is a circuit that can stably generate a certain frequency in a circuit requiring high clock frequency of GHz. The proposed circuit has an advantageous effect of reducing the error operations that can be caused by the clock skew and jitter phenomenon of the existing complex PLL (Phase Locked Loop) circuit.

The fractal structure allows the size of the ring oscillator of the fractal structure to be extended. Fractional ring oscillators can be constructed with fewer than 15 to 45 nodes. In this case, one inverter has a phase difference of ⅓π, and three inverters constitute one cell, so that one cell has a phase difference of ⅔π. Thus, it can have one 2π cycle phase by three different inverters.

2 is a schematic diagram of a CMOS ring oscillator according to an embodiment of the present invention.

As shown in FIG. 2, in an oscillator model diagram of two oscillators to be used for two chips, each ring oscillator is composed of thirty inverters and can be used as an oscillator in two different chips 210 and 220. Two oscillator in-phase nodes are connected by three clock lines (CL, CL-1, CL-2 and CL-3). For example, node 1 of the first chip 210 and node 1 of the second chip 220 are connected through CL-1, node 5 of the first chip 210 connects CL-2 .

Even if the difference in voltage supplied to the two chips 210 and 220 slightly occurs, the entire oscillator network 200 can oscillate in the same frequency and phase by the connection of the three clock lines.

Preferably, the plurality of chips may be chips having the same structure. For example, the first chip 210 may be a ring oscillator composed of thirty inverters, and the second chip 220 may also be a ring oscillator composed of thirty inverters.

It is preferable that the first chip 210 and the second chip 220 have the same structure, and the number of inverters can be increased or decreased within a range in which the physical space inside the circuit is ensured.

3 is a block diagram of a circuit according to one embodiment of the present invention.

As shown in FIG. 3, a method of implementing a phase synchronization circuit by a proposed method without using a PLL for synchronizing a clock signal generated in two different chips 310 and 320 will be described do. Since the ring oscillator network is constructed in a simple form, there is an advantageous effect that the wiring area is reduced as compared with the PLL circuit in the layout design.

4 is a conceptual diagram of a multi-layer structure according to an embodiment of the present invention.

As shown in Fig. 4, a three-dimensional structure can be designed by the latest multi-layer CMOS processing technology. A clock bus line is located between the first chip 410 and the second chip 420 to connect the two chips. The wiring overload phenomenon can be reduced through this simplified structure .

5 is a diagram illustrating a TTL ring oscillator network between two chips according to an embodiment of the present invention.

In addition to simulation, hardware experiments using low-speed TTL chips can also explain clock signal synchronization methods. Under the experimental conditions, each of the chips 510 and 520 is composed of five TTL chips 7404, and the three clock bus lines serve to connect three different in-phase signals.

6 is a flowchart illustrating a synchronization process of a clock signal according to an embodiment of the present invention.

In step S610, a voltage source is input to the first chip for generating the first clock signal and the second chip for generating the second clock signal.

In step S620, the first clock signal and the second clock signal oscillate in the clock line located between the first chip and the second chip.

In step S630, the first clock signal and the second clock signal are output as a clock signal having the same frequency and the same phase as each other.

The clock line in the above process is a clock line connecting the three ends of the first chip and the second chip having the same fractal structure to each other.

In the same vein, you can compensate for the clock skew by:

Receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal;

Oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip;

And adjusting the frequency and phase of the first clock signal and the second clock signal,

The clock line is a clock line connecting three ends of the first chip and the second chip having the same fractal structure to each other.

Also, in the same context, the multi-chip phase can be corrected by the following process.

Receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal;

Oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip;

And adjusting the frequency and phase of the first clock signal and the second clock signal to a third clock signal,

The clock line is a clock line connecting three ends of the first chip and the second chip having the same fractal structure to each other.

Hereinafter, the effects of the present disclosure will be described on the basis of simulation and measurement results obtained by applying the above clock signal synchronization method.

FIG. 7 is a graph showing simulation of an output waveform of a ring oscillator on the assumption of the same voltage according to an embodiment of the present invention, and FIG. 8 is a graph showing an output waveform measurement value.

As shown in FIG. 7, if the same voltage source is provided on two chips, the same phase and the same frequency are generated. Even if two chips are not connected to the clock line, two central nodes (node 13 in FIG. 2) Phase state.

As shown in FIG. 8, the measured values according to the same voltage source represent the same phase and the same frequency.

FIG. 9 is a graph illustrating simulation of output waveforms of a ring oscillator on the assumption of different voltage sources according to an embodiment of the present invention, and FIG. 10 is a graph showing measured values of output waveforms.

In this experiment, a case where a voltage (3.03 V) increased by 1% is applied to the second chip while the applied voltage of the first chip is fixed at 3 V can be explained. It can be seen that the range of clock skew also increases as the voltage variation range is larger in two different chips. It can be seen that a phase difference occurs between the two clock signals in the interval of 8 ns to 10 ns.

FIG. 11 is a graph showing a skew phenomenon simulation according to an embodiment of the present invention, and FIG. 12 is a graph showing a skew phenomenon measurement value.

As shown in FIG. 11, a clock skew generated when different voltage sources are assumed is simulated, and a clock skew of about 4.8 ns is measured, as shown in FIG.

FIG. 13 is a graph illustrating a clock skew value measured according to a voltage variation according to an embodiment of the present invention.

In this experiment, a case where the voltage applied to the first chip is fixed to 3 V and the voltage is increased to 2% (3.06 V) to the second chip with a 1% variation unit (0.03 V) can be explained. Likewise, the voltage was reduced by 2% (2.94 V) to the minimum range. In the simulation result of FIG. 13, it is confirmed that the clock skew value is output up to 143 ps. It can be seen that a symmetrical phase difference of 143 ps occurs when there is a maximum 2% voltage difference between two chips. The phase difference is equivalent to 22.04% of the cycle.

FIG. 14 is a graph showing simulation values of output waveforms of a ring oscillator according to an embodiment of the present invention, and FIG. 15 is a graph showing measured values.

FIG. 14 and FIG. 15 are graphs of the experiment with two chips connected through three clock bus lines (CBL) as described in FIG. 2 and FIG.

As shown in FIG. 16, it can be seen that the simulation value is significantly reduced from the simulation value of 3% and the measured value of 1.63% than the skew phenomenon of FIG.

17 is a diagram illustrating a layout of a CMOS ring oscillator according to an embodiment of the present invention.

As shown in FIG. 17, a circuit can be designed without a PLL or a DLL circuit by using the ring oscillator described above. In FIG. 17, a circuit is configured by using 108 inverters. As the simplification of the circuit becomes possible, the chip size is reduced overall. Considering that the skew is measured within 19,51 ps despite the 2% range of asymmetric voltage conditions, a new direction in clock signal synchronization technology I expect to present it.

The description sets forth the best mode of the invention, and is provided to illustrate the invention and to enable those skilled in the art to make and use the invention. The written description is not intended to limit the invention to the specific terminology presented.

Thus, while the present invention has been described in detail with reference to the above examples, those skilled in the art will be able to make adaptations, modifications, and variations on these examples without departing from the scope of the present invention. In other words, in order to achieve the intended effect of the present invention, all the functional blocks shown in the drawings are separately included or all the steps shown in the drawings are not necessarily followed in the order shown, It can be in the range.

100: Ring oscillator
200: Full Oscillator Network
210: First chip
220: second chip

Claims (12)

Receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal;
Oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip;
Wherein the first clock signal and the second clock signal are output as a clock signal having the same frequency and the same phase,
The clock line
Wherein the clock signal is a clock line that connects the three ends of the first chip and the second chip having the same fractal structure to each other.
The method according to claim 1,
The fractal structure,
Wherein the inverter chain in which an odd number of inverters are connected in series is a fractal structure constituting one fractal triangle.
The method according to claim 1,
Wherein the first voltage applied to the first chip and the second voltage applied to the second chip are different voltages.
The method according to claim 1,
Wherein the first chip and the second chip include:
Characterized in that the clock signal is a ring oscillator consisting of thirty inverters each.
The method according to claim 1,
Wherein the first chip and the second chip are operated at a GHz frequency.
Receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal;
Oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip;
And adjusting the frequency and phase of the first clock signal and the second clock signal,
The clock line
Wherein the clock skew is a clock line connecting the three ends of the first chip and the second chip having the same fractal structure to each other.
The method according to claim 6,
The fractal structure,
Wherein the inverter chain in which the odd number of inverters are connected in series is a fractal structure constituting one fractal triangle.
The method according to claim 6,
Wherein the first voltage applied to the first chip and the second voltage applied to the second chip are different voltages.
The method according to claim 6,
Wherein the first chip and the second chip include:
Wherein the ring oscillator is a ring oscillator composed of 30 inverters each.
The method according to claim 6,
Wherein the first chip and the second chip are operated at a GHz frequency.
In the multichip phase correction method,
Receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal;
Oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip;
And adjusting the frequency and phase of the first clock signal and the second clock signal to a third clock signal,
The clock line
Wherein the first chip and the second chip have the same fractal structure and are connected to each other at three ends of the first chip and the second chip.
12. The method of claim 11,
Wherein the third clock signal is the same signal as any one of the first clock signal and the second clock signal.

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