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KR101772024B1 - Method for inspecting wafer - Google Patents

Method for inspecting wafer Download PDF

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Publication number
KR101772024B1
KR101772024B1 KR1020150144216A KR20150144216A KR101772024B1 KR 101772024 B1 KR101772024 B1 KR 101772024B1 KR 1020150144216 A KR1020150144216 A KR 1020150144216A KR 20150144216 A KR20150144216 A KR 20150144216A KR 101772024 B1 KR101772024 B1 KR 101772024B1
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KR
South Korea
Prior art keywords
wafer
defect
pattern
voltage
level
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KR1020150144216A
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Korean (ko)
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KR20170044467A (en
Inventor
이우성
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주식회사 엘지실트론
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Priority to KR1020150144216A priority Critical patent/KR101772024B1/en
Priority to PCT/KR2016/011117 priority patent/WO2017065445A1/en
Publication of KR20170044467A publication Critical patent/KR20170044467A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

(A) applying a first voltage having a level of a first range to a wafer having a pattern to find a defective area; and (c) (B) of finding a defect point where a defect occurs in the detected defect area by applying a second voltage, and determining at least one of the type of defect or the degree of defect through at least one of a cross-section or a planar shape of the defect point where the defect occurs Wherein in each of steps (a) and (b), the maximum application level of each of the first and second voltages is determined within a range in which the defect shape of the wafer is maintained.

Description

[0001] The present invention relates to a method for inspecting a wafer,

Embodiments relate to a method of inspecting wafers.

In order to manage excellent device yield of a silicon wafer, conventional metal contamination, defect level, and crystal characteristics as well as electrical characteristics are important. For this purpose, it is important to characterize GOI (Gate Oxide Integrity). GOI is an analytical technology that evaluates the quality of wafers by measuring the insulation strength of the gate oxide (gate oxide) placed on the silicon substrate in the MOS structure, which is the basic structure of the device. As an evaluation method for GOI, there is a breakdown voltage (BV) or a charge breakdown (Qbd).

The breakdown voltage is a method of measuring the current by applying a voltage to the gate oxide film while increasing the breakdown voltage until the gate oxide breaks down. However, when the voltage is applied too much, defects on the wafer to be inspected and analyzed are destroyed, so that it is difficult to accurately grasp the type and degree of defects.

Embodiments provide a method of inspecting wafers that can accurately inspect and analyze at least one of the types of defects included in the wafer or the degree of defects.

A wafer inspection and analysis method according to an embodiment includes: (a) detecting a defective area by applying a first voltage having a level of a first range to a wafer having a pattern; (B) applying a second voltage having a level in a second range lower than the first range to the wafer to find a defect point where a defect occurs in the found defective area; And (c) obtaining defect information on at least one of the kind of the defect or the degree of the defect through at least one of a cross-section or a planar shape of the defect point where the defect occurs, and (c) b) In each of the steps, the maximum application level of each of the first and second voltages may be determined within a range in which the defect shape of the wafer is maintained.

For example, each of steps (a) and (b) may include: measuring a level of a current flowing through the wafer while the first or second voltage is applied to the wafer having the pattern; And maintaining the applied level of the first or second voltage when the level of the measured current reaches the limit level.

For example, the threshold level may be 1 占.. The first range may be from 0 to -20 volts, and the second range may be from -0.5 volts to -10 volts. In addition, the level of each of the first and second voltages may be non-linear. The level of each of the first and second voltages may be stepped. The first voltage may be applied to the wafer in increments of 0.5 volts, and the second voltage may be applied to the wafer in increments of 0.1 volts.

For example, the wafer inspection and analysis method may further include marking a defect point where the found defect has occurred.

For example, the wafer having the pattern may include a silicon substrate; An insulating layer disposed on the silicon substrate; And an electrode disposed on the insulating layer.

For example, the step (c) may include: (c11) obtaining a cross-sectional shape of the wafer having the pattern; And obtaining the defect information using the obtained cross-sectional shape (c12).

For example, the step (c11) may include obtaining a TEM image of a cross section of the wafer having the pattern.

(C) removing the insulating layer and the electrode on the silicon substrate (c21); And obtaining at least one of a cross-section or a planar shape of the wafer without the insulating layer and the pattern from which the electrode is removed (c22); And obtaining the defect information using at least one of the obtained cross-section or planar shape (c23).

For example, the step (c22) may include obtaining a TEM image of a cross section of the wafer having no pattern; Or obtaining a SEM image of a plane of the wafer having no pattern.

For example, the type of the defect may include at least one of COP (Crystal Originated Pit) and PIP (Polishing Induced Pit).

For example, the type of the defect may further include a variation in the thickness of the insulating layer disposed between the silicon substrate and the electrode, and the degree of the defect may include a non-uniform degree of the thickness.

The method of inspecting a wafer according to an embodiment prevents a defect existing on a wafer from being destroyed by controlling the current applied to the wafer so as not to exceed a threshold level so that at least one of the type of defects or the degree of defects can be accurately grasped , The pattern is stripped and removed from the wafer having the pattern so that the original shape of the defect can be accurately grasped.

1 is a flowchart for explaining a wafer inspection and analysis method according to an embodiment.
2A and 2B show a schematic perspective view and a front view, respectively, of a MOS structure which is a wafer having a pattern.
Figures 3a-3f show process cross-sectional views of the wafer shown in Figures 2a and 2b.
4 shows a top plan view of a wafer having the MOS structure shown in FIG.
5A to 5C are plan views of a wafer having a plurality of patterns to be subjected to the wafer inspection and analysis method shown in FIG.
6 is a schematic cross-sectional view of a wafer inspection and analysis apparatus for performing the wafer inspection and analysis method shown in FIG.
7 is a graph showing an exemplary view of the first or second voltage.
8 is a flow chart for explaining an embodiment of step 110 or 120 shown in FIG.
9 is a graph showing changes in the breakdown voltage of the wafer in accordance with various defects.
10 is a graph for explaining the limit level of the current.
FIG. 11 shows a flowchart for explaining an embodiment of operation 140 shown in FIG.
FIG. 12 shows a flowchart for explaining another embodiment of operation 140 shown in FIG.
13A to 13C are process sectional views illustrating a process of stripping a wafer having a pattern.
14A and 14B show a cross-sectional image and a plane image of the wafer obtained by the wafer inspection and analysis method according to the comparative example, respectively.
15A to 15C are cross-sectional and plan views of an example of a wafer obtained by the wafer inspection and analysis method according to the embodiment.
16A to 16C show cross-sectional views and plan views of another example of the wafer obtained by the wafer inspection and analysis method according to the embodiment.
17A and 17B show cross-sectional and planar images of still another example of a wafer obtained by the wafer inspection and analysis method according to the embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

1 is a flowchart for explaining a wafer inspection and analysis method 100 according to an embodiment.

Before describing the wafer inspection and analysis method 100 according to the embodiment, a wafer having a pattern as a target of the wafer inspection and analysis method 100 will be described as follows.

A wafer having a pattern can be defined as a wafer having electrical characteristics by arranging various types of structures on a silicon substrate. For example, there may be a transistor or the like as a wafer having a pattern.

Hereinafter, for convenience of explanation, the wafer having the pattern is described as having a metal oxide semiconductor (MOS) structure, but the embodiment is not limited thereto.

2A and 2B show a schematic perspective view and a front view, respectively, of a MOS structure which is a wafer 200 having a pattern.

2A and 2B, the MOS structure of the wafer 200 may include a silicon substrate 202, an insulating layer (or Gate Oxide) 204, and an electrode 206. Here, the insulating layer 204 and the electrode 206 correspond to the pattern of the wafer 200 having the pattern.

The silicon substrate 202 can be obtained by sawing a single crystal silicon ingot (not shown).

The insulating layer 204 may be disposed on the silicon substrate 202. The insulating layer 204 may comprise an oxide, but embodiments are not limited to any particular material of the insulating layer 204.

The electrode 206 may be disposed over the insulating layer 204. The electrode 206 may be formed of metal, polysilicon, or the like.

When a voltage is applied to the first and second terminals T1 and T2 of the MOS structure in the wafer 200 having the above-described pattern, a current can flow in the MOS structure.

Figures 3A-3F show process cross-sectional views of the wafer 200 shown in Figures 2A and 2B.

The wafer 200 shown in Figs. 2A and 2B may be manufactured by the method shown in Figs. 3A to 3F, but the embodiments are not limited thereto.

A silicon substrate 202 is prepared as illustrated in Fig. Referring to FIG. 3B, upper and lower insulating layers 204-1 and 204-2 are formed on the upper and lower surfaces of the silicon substrate 202, respectively. Each of the upper and lower insulating layers 204-1 and 204-2 may be formed of an oxide. In some cases, only the upper insulating layer 204-1 may be formed, and the lower insulating layer 204-2 may be omitted. In this case, the upper insulating layer 204-1 corresponds to the insulating layer 204 shown in Figs. 2A and 2B.

Then, as shown in FIG. 3C, upper and lower polysilicon layers 206-1 and 206-2 are deposited on upper and lower insulating layers 204-1 and 204-2, respectively, as upper and lower electrodes, respectively, . The resulting upper and lower polysilicon layers 206-1 and 206-2 may then be annealed. Here, only the upper polysilicon layer 206-1 is formed, and the lower polysilicon layer 206-2 may be omitted. In this case, the upper polysilicon layer 206-1 corresponds to the electrode 206 shown in Figs. 2A and 2B.

3D, a photoresist (PR) 220 is formed on the upper polysilicon layer 206-1, and the photoresist 220 is exposed and developed by a conventional photolithography process The upper polysilicon layer 206-1 may be patterned to expose a portion of the upper insulating layer 204-1 at regular intervals as shown in FIGS.

Thereafter, the photoresist 220 and the lower polysilicon layer 206-2 are removed, as shown in FIG. 3F, to form the wafer 200 of a MOS structure.

FIG. 4 shows a top plan view of a wafer 200 having the MOS structure shown in FIG.

The first region A1 of the upper polysilicon layer 206-1 for measuring the breakdown voltage in FIG. 4 has a first region A1 occupied by the patterned upper polysilicon layer 206-1 shown in FIG. 3f, . Also, the second region A2 exposed between the upper polysilicon layer 206-1 in FIG. 4 is the upper insulating layer (not shown) exposed between the patterned upper polysilicon layer 206-1 shown in FIG. 3F 204-1 occupy the second area A2.

5A to 5C are top views of a wafer having a plurality of patterns to be subjected to the wafer inspection and analysis method 100 shown in FIG.

FIG. 6 shows a schematic cross-sectional view of a wafer inspection and analysis apparatus 300 that performs the wafer inspection and analysis method 100 shown in FIG.

The wafer inspection and analysis apparatus 300 shown in FIG. 6 may include supports 302 and 304, a voltage applying unit 306, a microscope 308, and a marker 310.

The supports (302, 304) serve to support the wafer (200). The portions 304 of the supports 302 and 304 that are in contact with the wafer 200 may have conductivity. Further, the support base 302 can move in at least one of the x-axis direction and the y-axis direction. This is to measure the current at various points of the wafer 200.

The microscope 308 serves to confirm the position of the defect on the wafer 200 having the pattern. Also, the marker 310 plays a role of performing step 130 shown in FIG. 1, as described later.

Although not shown, the wafer inspection and analysis apparatus 300 shown in FIG. 6 may further include an ammeter for measuring a current flowing in the wafer 200.

Hereinafter, a wafer inspection and analysis method 100 according to an embodiment will be described with reference to the above-mentioned drawings.

As described above, the electrical characteristics of the wafer 200 having a pattern are important. For this, GOI (Gate Oxide Integrity) characterization is required. GOI is an analytical technique for evaluating the quality of the wafer 200 by measuring the insulation strength of the insulating layer 204 in the wafer 200 having a MOS structure. As an evaluation method, breakdown voltage BV and breakdown voltage Qbd Charge to Breakdown). In order to grasp the characteristics of the GOI by the BV, the voltage is applied to the wafer 200 while the insulating layer 204 is broken down, and the current flowing through the wafer 200 is measured at this time. Through this process, it is possible to predict the withstand voltage and the service life of the wafer 200 before forming the device using the wafer 200.

Hereinafter, a process of obtaining defect information on the surface of the wafer 200 after determining the defect-free characteristics of the surface of the wafer 200 by measuring the breakdown voltage to evaluate the GOI will be described as follows.

In operation 110, a first voltage V1 having a level in a first range is applied to the wafer 200 having a pattern to search for a defective area. For example, assume that there are a plurality of wafers 200 having a pattern. At this time, a defective area can be found in each wafer 200 having a pattern by applying a first voltage (V1) having a level in a first range.

For example, referring to FIG. 5A, a first voltage V1 is applied to a wafer 200 having a pattern to form 10 defect regions (1, 2, 3, 4, 5, 6, 7, ⑩) can be found.

After the operation 110, a second voltage (V2) is applied to the wafer 200 having a pattern, and a defect point (hereinafter, referred to as a defect point) (Operation 120).

For example, referring to FIG. 5B, a second voltage V2 is applied to a wafer 200 having a pattern to form 10 defect regions (1, 2, 3, 4, 5, 6, 7, ⑩) You can find defect points in each.

Referring to FIGS. 5A and 5B, when a first or second voltage V1 or V2 is applied to a wafer 200 having a pattern, since a photon is emitted in a defect location, It is possible to easily identify the defective area and the defective point by using the microscope 308 shown in Fig.

As a result, step 110 is first performed to roughly find the defect region on the wafer 200 having the pattern, and the defect point is finely determined within each defect region, which is searched roughly. Step 120 is performed in order to search secondarily. Thus, the second range of the voltage level of the second voltage V2 may be lower than the first range of the voltage level of the first voltage V1. For example, the first range of the first voltage V1 may be between 0 and -20 volts and the second range of the second voltage V2 may be between -0.5 volts and -10 volts, although embodiments include, Do not.

7 is a graph showing an example of the first or second voltage V1 or V2, wherein the horizontal axis represents the level of the voltage and the vertical axis represents time.

Referring to FIG. 7, the level of each of the first and second voltages V1 and V2 may be applied to the wafer 200 while changing to a linear 402 or a non-linear 404. For example, the level of each of the first and second voltages V1 and V2 may be stepped 404, but the embodiment is not limited in this respect.

If the first and second voltages V1 and V2 are applied to the wafer 200 in a stepped manner as shown in FIG. 7, the first voltage V1 is increased by 0.5 volts, And may be applied to the wafer 200 while minimizing the second voltage V2 at a level lower than the application level interval of the first voltage V1, for example, at 0.1 volt intervals.

Since the defective area found by application of the first voltage V1 is wider than the defective area found by application of the second voltage V2, the second range is lower than the first range, as described above, The interval at which the first voltage V1 is applied is finer than the interval at which the first voltage V1 is applied.

The maximum application level of each of the first voltage V1 and the second voltage V2 applied to the wafer 200 having the pattern in steps 110 and 120 is determined such that the defect shape of the wafer 200 having the pattern is maintained And the like. This is because a current flows in the wafer 200 by applying the first and second voltages V1 and V2 and when the level of the current flowing in the wafer 200 exceeds the limit level, 200 can be destroyed. If the first or second voltage V1 or V2 is excessively increased in level, defect information can not be obtained in operation 140. [

8 is a flow chart for explaining an embodiment of step 110 or 120 shown in FIG.

Referring to FIG. 8, the level of the current flowing through the wafer 200 having the pattern is measured while the first voltage V1 is applied to the wafer 200 having the pattern (operation 112).

After operation 112, it is determined whether the measured current level has reached a compliance level (operation 114).

If it is determined that the level of the measured current has reached the limit level, the level to which the first voltage V1 is applied is fixed without being increased any more and maintained (Step 116). This is because, if the application level of the first voltage V1 is continuously increased even after the level of the measured current reaches the limit level, the defect shape of the wafer 200 having the pattern can be destroyed.

Similarly, step 120 shown in FIG. 1 may also perform the method as shown in FIG. That is, while the second voltage V2 is applied to the wafer 200 having the pattern, the level of the current flowing through the wafer 200 having the pattern is measured (operation 112).

After operation 112, it is checked whether the level of the measured current has reached a limit level (operation 114).

If it is determined that the level of the measured current has reached the limit level, the level to which the second voltage V2 is applied is fixed without being increased any more and maintained (Step 116). This is because, if the application level of the second voltage V2 is continuously increased even after the level of the measured current reaches the limit level, the shape of the defect of the wafer 200 having the pattern can be destroyed.

9 is a graph showing changes in the breakdown voltage of the wafer 200 according to various defects. The abscissa indicates an electric field (E Field) and the ordinate indicates a current. Here, 410 corresponds to a case where the wafer 200 has no defect.

Referring to FIG. 9, when the wafer 200 has the first defect Fl, even if only a slight voltage is applied to the wafer 200, a large current 412 flows to yield. Alternatively, when the wafer 200 has the second defect F2, the second defect F3 is applied to the wafer 200 having the third defect F3 higher than the voltage applied to the wafer 200 having the first defect Fl A large current 414 flows at a voltage lower than the voltage, so that breakdown occurs. Alternatively, when the wafer 200 has the third defect F3, the voltage applied to the wafer 200 that is higher than the voltage applied to the wafer 200 having the second defect F2 but has no defect (P) A large current 416 flows at a lower voltage and breakdown occurs.

As described above, the limit level for preventing the shape of the defect of the wafer 200 having the pattern from being destroyed can be obtained in advance experimentally in advance with reference to Fig.

10 is a graph for explaining the limit level of current, in which the axis of abscissas represents the voltage applied to the wafer 200 and the axis of ordinates represents the current (LI) flowing through the wafer 200.

10, if there is no defect in the wafer 200 when the threshold level is 10 mA, the wafer 200 has the same voltage / current characteristics as the reference numeral 430. However, if there is a defect in the wafer 200, Has a voltage / current characteristic equal to 432. [

10, if the threshold current is 1 A, the wafer 200 has the same voltage / current characteristics as the reference numeral 440 if there is no defect in the wafer 200, but if there is a defect in the wafer 200 Wafer 200 has the same voltage / current characteristic as reference numeral 442. [ Thus, by adjusting the levels of the voltages V (V1, V2), the level of the current LI flowing through the wafer 200 can be prevented from exceeding the limit level. When the level of the current flowing through the wafer 200 does not exceed the limit level, the shape of the defect of the wafer 200 can be maintained without being broken. For example, the threshold level may be 1 占 나, but the embodiment is not limited thereto.

Referring again to FIG. 1, after performing step 120, a defect point may be marked on the wafer 200 as shown in FIG. 5C using the marker 310 shown in FIG. 6 step). For example, a laser may be used to mark a defect point, although embodiments are not limited in this respect.

In some cases, step 130 may be omitted.

After performing operation 130, defect information on at least one of the type of defects or the degree of defects can be obtained through at least one of a cross-section or a planar shape at a point where a defect occurs in the wafer 200 step).

FIG. 11 shows a flowchart for explaining one embodiment 140A of operation 140 shown in FIG.

Referring to FIG. 11, a cross-sectional shape of a wafer having a pattern is obtained (operation 142). For this purpose, it is possible to obtain a TEM (Transmission Electron Microscope) image of the cross section of the wafer 200 having a pattern, for example, but the embodiment is not limited thereto.

After operation 142, defect information is obtained using the obtained cross-sectional shape (operation 144).

FIG. 12 shows a flowchart for explaining another embodiment 140B of operation 140 shown in FIG.

Referring to FIG. 12, a wafer 200 having a pattern is stripped. That is, the insulating layer 204 and the electrode 206 on the silicon substrate 202 are removed (operation 141).

FIGS. 13A to 13C show process cross-sectional views for explaining the process of stripping a wafer 200 having a pattern.

A wafer 200 having a pattern as shown in Fig. 13A is prepared. Thereafter, as shown in FIG. 13B, the upper polysilicon layer 206-1 corresponding to the electrodes shown in FIGS. 2A and 2B is removed. For example, the upper polysilicon layer (206-1) can be removed using a NH 4 OH.

Thereafter, the insulating layers 204-1 and 204-2 shown in Fig. 13B are removed as shown in Fig. 13C. For example, if the insulating layers 204-1 and 204-2 are implemented with an oxide, the insulating layers 204-1 and 204-2 can be removed using HF.

After step 141, at least one of a cross-section or a planar shape of the wafer (i.e., the silicon substrate 202) having no pattern in which the insulating layer 204 and the electrode 206 are removed is obtained (operation 143).

For example, in step 143, only the TEM image of the cross section of the silicon substrate 202, which is the wafer 202 having no pattern, can be obtained. Alternatively, in step 143, a TEM image of the cross section of the silicon substrate 202, which is the wafer 202 having no pattern, is obtained, and an SEM (Scanning Electron Microscope) image of the plane of the silicon substrate 202 can also be obtained have. Alternatively, in operation 143, only the SEM image of the plane of the silicon substrate 202 may be obtained.

After operation 143, in operation 145, defect information is obtained using at least one of a cross-section or a planar shape obtained in operation 143.

As described above, when the wafer 200 having a pattern is stripped, the original shape of the defect in the silicon substrate 202 can be accurately grasped.

According to another embodiment, the step 140 shown in FIG. 1 may include both the embodiment 140A shown in FIG. 11 and the embodiment 140B shown in FIG.

Meanwhile, the kinds of defects included in the defect information obtained in operation 140 shown in FIG. 1 may vary. For example, the type of defect may include at least one of a COP (Crystal Originated Pit) or a PIP (Polishing Induced Pit). In addition, the type of the defect may further include a variation in the thickness of the insulating layer 204 disposed between the silicon substrate 202 and the electrode 206. In this case, the degree of defect may include a non-uniform degree of the thickness of the insulating layer 204.

Hereinafter, a wafer inspection and analysis method of comparative examples and embodiments will be described with reference to the accompanying drawings.

14A and 14B show a cross-section image and a plane image of the wafer 200 obtained by the wafer inspection and analysis method according to the comparative example, respectively.

The comparative wafer inspection and analysis method continuously applies the voltages V1 and V2 to the wafer 200 even if the current flowing through the wafer 200 shown in FIG. 2A or 2B exceeds the threshold level . In this case, a TEM image as shown in Fig. 14A is obtained. 14A, the shape of the defect region 502 of the wafer 200 is broken and the silicon substrate 202, the insulating layer 204, and the electrode 206 are not distinguished from each other, It can be understood that the defect information can not be obtained. Further, the SEM image shown in Fig. 14B is obtained. 14B, when the insulating layer 204 and the electrode 206 are removed using NH 4 OH and HF for the strip in the state that the shape of the defect region 502 shown in FIG. 14A is broken, It can be seen that the NH 4 OH penetrates into the pin hole of the defect portion and the edge 504 of the defect portion 502 is etched and damaged.

Figs. 15A to 15C show one example of cross-section and plane image of the wafer 200 obtained by the wafer inspection and analysis method 100 according to the embodiment. 15C is a cross-sectional view taken along the line I-I 'shown in FIG. 15B.

If a COP defect exists in the wafer 200, the TEM cross-sectional image as shown in FIG. 15A can be obtained by performing the step 142. FIG. 14A, the 'A' portion of the TEM image shown in FIG. 15A shows that the shape of the COP defect 600 of the wafer 200 is not destroyed and the shape of the silicon substrate 202, the insulating layer 204, 206). As described above, according to the embodiment, the shape of the COP defect 600 can be recognized even before the insulating layer 204 and the electrode 206 are removed, as shown in FIG. 15A.

Further, when the COP defect exists in the wafer 200, by performing Steps 141 and 143, the SEM plane image shown in FIG. 15B and the TEM cross-sectional image shown in FIG. 15C can be obtained. 15B and 15C, it can be seen that the shape of the COP defect 600 existing in the wafer 200 is preserved without being destroyed. Therefore, the shape of the COP defects 600 existing in the silicon substrate 202 can be recognized as a prototype.

16A to 16C show cross-sectional views and plan views of another example of the wafer 200 obtained by the wafer inspection and analysis method 100 according to the embodiment.

If the PIP defect exists in the wafer 200, the TEM cross-sectional image as shown in FIG. 16A can be obtained by performing the step 142. FIG. 16A, the PIP defect 700 of the wafer 200 is not destroyed, but remains intact with the silicon substrate 202, the insulating layer 204, and the electrode 206 . As described above, according to the embodiment, the shape of the PIP defect 700 can be recognized even before the insulating layer 204 and the electrode 206 are removed as shown in FIG. 16A.

In addition, when the PIP defect 700 exists in the wafer 200, the SEM plane image shown in FIG. 16B and the TEM cross-sectional image shown in FIG. 16C can be obtained by performing steps 141 and 143. 16B and 16C, it can be seen that the shape of the PIP defect 700 existing in the wafer 200 is preserved without being destroyed. Particularly, it can be seen that the depth DE and the width WI of the PIP defect 700 are also clearly shown. Therefore, the shape of the PIP defects 700 existing in the silicon substrate 202 can be recognized as a prototype.

17A and 17B show cross-section and plan view images of still another example of the wafer 200 obtained by the wafer inspection and analysis method 100 according to the embodiment.

17A, the wafer 200 contaminated at a level of 1.11 x 10 11 (atoms / cm 2) per unit area of potassium (K) in the case of the metal that caused the thickness variation of the insulating layer 204 was used.

The TEM cross-sectional image as shown in FIGS. 17A and 17B can be obtained by performing operation 142. FIG. When the thickness TH1 of the insulating layer 204 is deformed in the wafer 200 having the pattern as shown in Fig. 17A, the deformation of the thickness TH1 is not destroyed, and the silicon substrate 202, the insulating layer 204 and the electrode 206 are kept in a circular shape. As shown in FIG. 17B, in comparison with the case where there is no deformation of the thickness TH2 of the insulating layer 204, it can be seen that the thickness of the insulating layer 204 grows thick in FIG. have.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

202: silicon substrate 204: insulating layer
206: electrodes 204-1, 204-2: upper and lower insulating layers
206-1 and 206-2: upper and lower polysilicon layers
300: Wafer inspection and analysis device 302, 304: Support
306: voltage applying unit 308: microscope
310: Marker 502: Defective site
504: Edge of defective area 600: COP defect
700: PIP defect

Claims (9)

(a) applying a first voltage having a level of a first range to a wafer having a pattern to find a plurality of defective areas;
(b) applying a second voltage having a level of a second range, which is lower than the first range and finely spaced, to the wafer to find a defect point where a defect occurs in each of the plurality of defective areas found; And
(c) obtaining defect information on at least one of the kind of the defect or the degree of the defect through at least one of a cross-section or a planar shape of the defect point where the defect occurs,
In each of the steps (a) and (b), the maximum application level of each of the first and second voltages is determined within a range in which the defect shape of the wafer is maintained,
Wherein the obtaining of the defect information includes disposing a wafer having the pattern on a support having conductivity at a portion in contact with the wafer having the pattern and moving in the x or y axis direction, 1 and a second voltage are applied to detect the position of the defect by detecting a photon emitted from a defect of the wafer having the pattern in the microscope to mark the position of the identified defect in the wafer having the pattern at the marker Of the wafer. The method of claim 1, wherein each of steps (a) and (b)
Measuring a level of a current flowing in the wafer while the first or second voltage is applied to the wafer having the pattern; And
Further comprising maintaining an applied level of the first or second voltage when the level of the measured current reaches a limit level. 3. The method of claim 2, wherein the threshold level is 1 占.. The wafer according to claim 1, wherein the wafer having the pattern
A silicon substrate;
An insulating layer disposed on the silicon substrate; And
And an electrode disposed on the insulating layer. 5. The method of claim 4, wherein step (c)
(c11) obtaining a cross-sectional shape of a defect point where the defect occurs in the wafer having the pattern; And
(c12) obtaining the defect information using the obtained cross-sectional shape. 5. The method of claim 4, wherein step (c)
(c21) removing the insulating layer and the electrode on the silicon substrate; And
(c22) obtaining at least one of a cross-section or a planar shape of the wafer without the insulating layer and the pattern from which the electrode is removed; And
(c23) obtaining the defect information by using at least one of the obtained cross-section or planar shape, and the defect information is the kind or degree of the defect. The method of claim 1, wherein the type of defect includes at least one of a COP (Crystal Originated Pit) and a PIP (Polishing Induced Pit). 5. The method of claim 4, wherein the type of defect further comprises a variation in the thickness of the insulating layer disposed between the silicon substrate and the electrode,
Wherein the degree of the defect includes a nonuniform degree of the thickness. The method of claim 1, wherein the first range is from 0 to -20 volts and the second range is from -0.5 volts to -10 volts.
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