KR101770464B1 - Device packages and method for forming same - Google Patents

Abstract

A device package of an embodiment includes a package substrate and first and second die bonded to the package substrate. The package substrate includes a buildup portion including a first contact pad and a plurality of bump pads. The package substrate includes an organic core attached to a buildup portion, a through via extending through the organic core and electrically connected to the first contact pad, a second contact pad on the through via, and a connector on the second contact pad, And a cavity extending through the organic core. The cavity exposes a plurality of bump pads and the first die is disposed on the cavity and bonded to the plurality of bump pads.

Description

[0001] DEVICE PACKAGE AND METHOD FOR FORMING SAME [0002]

<Priority claim and cross reference>

The present application is a continuation-in-part of U.S. Patent Application Serial No. 14 / 181,305, filed February 14, 2014, which is incorporated herein by reference in its entirety.

<Background>

In one aspect of the integrated circuit packaging technique, separate semiconductor dies are formed and initially separated. These semiconductor dies are then joined together and the die stack thus formed can be connected to other package components such as a package substrate (e.g., interposer, printed circuit board, etc.) using a connector on the bottom die of the die stack Lt; / RTI &gt;

The final package is known as Three-Dimensional Integrated Circuits (3DIC). The top die of the die stack may be electrically connected to other package components via an interconnect structure (e.g., through-substrate via, TSV) in the bottom die of the die stack. However, existing 3DIC packages may include a number of limitations. For example, a bonded die stack and other package components may result in large form factors and may require complex heat dissipation features. Conventional interconnect structures (e.g., TSV) of the bottom die are expensive to fabricate and the conduction path (e.g., signal / power path) to the top die of the die stack may be long. Moreover, packages with conventional 3D ICs, specifically high density solder balls (e.g., package-on-package (PoP) configurations), thin package structures, etc., may have solder bridges, warpage, and / or other disruptions.

BRIEF DESCRIPTION OF THE DRAWINGS The aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying drawings. Depending on the industry standard practice, the various features are not shown in full scale. In fact, the dimensions of the various features may be scaled up or down arbitrarily for convenience of explanation.
1A-1N are cross-sectional views of various intermediate stages for fabricating semiconductor packages in accordance with some embodiments.
2 is a cross-sectional view of a semiconductor package according to some alternative embodiments.
Figures 3A-3E are cross-sectional views of various intermediate stages for fabricating semiconductor packages in accordance with some alternative embodiments.
4A-4L are perspective views of various intermediate stages for fabricating a package substrate in accordance with some embodiments.
5A and 5B are cross-sectional views of a semiconductor package according to some alternative embodiments.
6A and 6B are cross-sectional and plan views of a package substrate according to some alternative embodiments.
7A and 7B are cross-sectional views of a device package including a package substrate according to some alternative embodiments.
8A-8N are different views of various intermediate stages for fabricating a package substrate in accordance with some alternative embodiments.
9A and 9B are cross-sectional views of a device package including a package substrate according to some alternative embodiments.
10 is a cross-sectional view of a device package including a package substrate according to some alternative embodiments.
11A and 11B are cross-sectional views of a device package including a package substrate according to some alternative embodiments.
12 is a process flow diagram for forming a package in accordance with some alternative embodiments.

The following description provides a number of different embodiments or examples for implementing different features of the claimed subject matter. Specific embodiments of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples, and are not intended to be limiting. For example, in the following description, the formation of the first feature on the second feature over or on may include an embodiment in which the first and second features are formed in direct contact, And an additional feature may be formed between the first and second features such that the second feature is not in direct contact. In addition, the present disclosure may repeat the reference numerals and / or characters in various embodiments. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations described.

Also, terms related to space such as "beneath", "below", "lower", "above", "upper" May be used herein for ease of description in describing the relationship between a feature and other element (s) or feature (s). Spatial terms are intended to include different orientations of the device during use or operation, as well as the orientations shown in the figures. The device may be oriented differently (rotated to 90 degrees or other orientation) and the spatial descriptor used herein may be similarly interpreted accordingly.

Various embodiments include a plurality of first die (e.g., memory die) electrically connected to one or more second die (e.g., logic die) through a first input / output (I / O) And a redistribution layer (RDL). The final die stack may be bonded to another package component, such as an interposer, a package substrate, a printed circuit board, etc., via the RDL of the second I / O pad and the second die. The package substrate may include a cavity, and the first die may be disposed within the cavity. Thus, a three-dimensional integrated circuit (3DIC), such as a chip on a fan-out package, can be configured with a relatively inexpensive relatively small form factor and can have a relatively short conduction path (e.g., signal / power path) have. Furthermore, one or more heat dissipation features may be independently formed on opposite surfaces of the first and / or second die.

1A-1N illustrate cross-sectional views of various intermediate stages for fabricating an integrated circuit (IC) package 100 (see FIG. 1n) in accordance with various embodiments. 1A shows a plurality of dies 10. The die 10 may include a substrate, an active device, and an interconnect layer (not shown). The substrate may be a bulk silicon substrate, but other semiconductor materials including Group III, Group IV, and Group V elements may be used. Alternatively, the substrate may comprise a semiconductor-on-insulator (SOI) structure. An active device such as a transistor can be formed on the top surface of the substrate. The interconnect layer may be formed over the active device and the substrate.

The interconnect layer may comprise an inter-layer dielectric (ILD) and an inter-metal dielectric layer (IMD) formed over the substrate. The ILD and IMD may be formed of a low k dielectric material with a k value of, for example, less than about 4.0 or even less than about 2.8. In some embodiments, the ILD and IMD include silicon oxide, SiCOH, and others.

A contact layer 12 comprising one or more contact pads may be formed over the interconnect structure and electrically connected to the active device through the various metal lines and vias in the interconnect layer. The contact pad in the contact layer 12 may be made of a metal material such as aluminum, but other metal materials may be used. A passivation layer (not shown) may be formed over the contact layer 12 from an inorganic material such as silicon oxide, undoped silicate glass, silicon oxynitride, or the like. The passivation layer may extend over and cover the edges of the contact pads in the contact layer 12. An opening is formed in the portion of the passivation layer covering the contact pad to expose at least a portion of the contact pad in the contact layer 12. The various features of the die 10 may be formed in any suitable manner, but will not be described in further detail herein. Also, the die 10 may be formed in a wafer (not shown) and singulated. A functional test can be performed on the die 10. Thus, the die 10 of FIG. 1A may only include what is known to be good passing one or more functional quality tests.

Next, referring to FIG. 1B, a die 10 may be disposed on the carrier 14. In FIG. The carrier 14 can be made of a suitable material, such as glass or carrier tape. The die 10 may be attached to the carrier 14 via one or more adhesive layers (not shown). The adhesive layer may be formed of any temporary adhesive material such as ultraviolet (UV) tape, wax, glue and the like. In some embodiments, the adhesive layer further comprises a die attach film (DAF), which may optionally be formed below the die 10 prior to placing the die 10 on the carrier 14 .

1C, a molding compound 16 may be used to fill the gap between the dies 10 and cover the top surface of the die 10. [ Molding compound 16 may comprise any suitable material such as epoxy resin, molded underfill, and the like. Suitable methods for forming the molding compound 16 may include compression molding, transfer molding, encapsulant molding, and the like. For example, molding compound 16 may be dispensed between dies 10 in liquid form. A curing process may then be performed to solidify the molding compound 16.

1D, a planarization process such as a grinding process (e.g., chemical mechanical polishing (CMP) or mechanical grinding) or etching back to expose the contact layer 12 (and any contact pads therein) A process may be performed on the molding compound 16. In a top view (not shown) of the die 10, the molding compound 16 may surround the die 10.

 1E illustrates forming a redistribution layer (RDL) 18 over the die 10 and the molding compound 16. 1E, the RDL 18 may extend laterally beyond the edge of the die 10 above the molding compound 16. The RDL 18 may comprise an interconnect structure 20 formed in one or more polymer layers 22. The polymer layer 22 can be formed from any suitable material (e.g., polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, Silicon, acrylates, nano-filled phenol resins, siloxanes, fluorinated polymers, polynorbornenes, etc.).

Interconnect structures 20 (e.g., conductive lines and / or vias) may be formed in the polymer layer 22 and electrically connected to the contact layer 12 of the die 10. The formation of the interconnect structure 20 may include patterning the polymer layer 22 (e.g., using a combination of photolithography and etching processes), patterning the patterned polymer layer 22 (e.g., Interconnect structure 20) using a mask layer that defines the shape of the interconnect structure 20). The interconnect structure 20 may be formed of copper or a copper alloy, but other metals such as aluminum and gold may be used. The interconnect structure 20 may be electrically connected to the contact pads of the contact layer 12 (and consequently the active device) in the die 10.

1F and 1G illustrate forming the connector 24 over the RDL 18. In particular, connectors 24 and 26 are formed on the same side of die 10 (i.e., on the same side of RDL 18). The connectors 24, 26 may be formed of any suitable material (e.g., copper, solder, etc.) using any suitable method. In some embodiments, the formation of the connectors 24 and 26 is accomplished by first forming under bump metallurgies (UBM) 24 '/ 26' electrically connected to the active devices in the die 10 via the RDL 18 . &Lt; / RTI &gt; The connectors 24 and 26 may extend laterally beyond the edge of the die 10 to form a fanout interconnect structure. By including the RDL 18, the number of connectors 24 and 26 (e.g., input / output pads) connected to the die 10 can be increased. As the number of connectors 24, 26 increases, the bandwidth may increase and the processing speed may increase (e.g., as the signaling path becomes shorter) in a subsequently formed IC package (e.g., package 100 of Figure 1n) , The power consumption can be reduced (e.g., as the power induction path becomes shorter).

Further, the connectors 24 and 26 may have different sizes. For example, the connector 24 may be a micro bump having a pitch of about 40 microns or greater, and the connector 26 may be a controlled collapse chip connection (C4) bump having a pitch between about 140 microns and about 150 microns. In an alternative embodiment, the connectors 24, 26 may include different dimensions. Thus, as shown in Figs. 1F and Ig, the connector 24 can be formed before the connector 26 in consideration of the size difference.

By varying the size of the connectors 24 and 26, different electrical devices (e.g., connectors having different sizes) can be bonded to the die 10. For example, the connector 24 may be used to electrically connect the die 10 to one or more other device dies 28 (see FIG. 1H), and the connector 26 may connect the die 10 to the package substrate 30) (e.g., printed circuit board, interposer, etc., see Figure 1K). In addition, since the connectors 24, 26 are formed on the same side of the die 10, different electrical devices can also be bonded to the same side of the die 10. (10) and RDL (18), alternative embodiments may employ alternate configurations (e.g., different configurations of RDL 18 and / or connectors 24/26) .

In FIG. 1h, a plurality of die 32 may be bonded to die 10 to form die stack 10/32 through connector 24 (e.g., by reflowing connector 24). The die 32 may be electrically connected to the active device in the die 10 via the RDL 18. [ In some embodiments, the die stack 10/32 may include a memory die 32 (e.g., a dynamic random access memory (DRAM) die) that is bonded to the die 10, Or may be a logic die that provides control functionality to the die 32. In an alternative embodiment, other types of die may be included in the die stack 10/32. Next, the underfill 34 can be distributed around the connector 24 between the die 32 and the RDL 18, as shown in FIG. The underfill 34 can support the connector 24.

1J illustrates removing carrier 14 from die stack 10/32 using any suitable method. For example, in one embodiment where the adhesion between the die 10 and the carrier 14 is a UV tape, the die 10 can be removed by exposing the adhesive layer to UV light. Subsequently, the die stack 10/34 is unified and packaged into an IC package. Unification of the die stack 10/34 may involve the use of appropriate pick-and-place tools.

Next, each die stack 10/32 can be bonded to the package substrate 30 through the connector 26, as shown in Fig. 1K. Reflow may be performed on the connector 26 to bond the die stack 10/32 to the package substrate 30. Subsequently, the underfill 46 can be distributed around the connector 26 between the die stack 10/32 and the package substrate 30, as shown in FIG. The underfill 46 may be substantially the same as the underfill 34.

The package substrate 30 may be an interposer, a printed circuit board (PCB), or the like. For example, the package substrate 30 may include a core 37 and one or more buildup layers 39 (designated 39A and 39B) disposed on both sides of the core 37. Interconnect structures 38 (e.g., conductive lines, vias, and / or through vias) may be included within the package substrate 30 to provide functional electrical use of power, ground, and / or signal layers. Other configurations of the package structure 30 may also be used.

In addition, the package substrate 30 may include a cavity 36. The cavity 36 can not extend through the package substrate 30. Instead, some or all of buildup layer 39A (e.g., buildup layer 39 disposed on the same side of die stack 10/32 and core 37) may be patterned to form cavity 36 have. As shown in FIG. 11, the cavity 36 includes a core 37 and / or a buildup layer 39B (a buildup layer disposed on the opposite side of the core 37 from the die stack 10/32) 39) can not be influenced. The configuration of the package substrate 30 may be designed such that the active interconnection structure 38 (e.g., power, ground, and / or signal layers within the buildup layer 39A) Therefore, the cavity 36 will not substantially interfere with the functionality of the package substrate 30.

The package substrate 30 may be formed using any suitable method. For example, FIGS. 4A-4L illustrate perspective views of various intermediate stages for fabricating the package substrate 30 in accordance with various embodiments. In Figure 4a, a core 37 is provided. The core 37 may be a metal-clad insulated substrate such as a copper-clad epoxy-impregnated glass-cloth laminate or a copper-clad polyimide-impregnated glass-cloth laminate. 4B, the cavity 36 and / or the through hole 52 may be formed in the core 37 using, for example, a mechanical drilling or milling process. The mechanical drilling / milling process may extend the through hole 52 through the core 37. However, the mechanical drilling / milling process can not extend the cavity 36 through the core 37.

Next, in Fig. 4C, the surfaces of the through holes 52 and the cavity 36 can be plated with the metallic material 54, for example, using an electrochemical plating process. In some embodiments, the metallic material 54 may comprise copper. Plating of the through hole 52 may form a through via that provides electrical connection from one side of the core 37 to the other side. Moreover, the metallic material 54 'on the surface of the cavity 36 can function as a laser stopping layer in subsequent processing steps (see FIG. 4k). 4D, the cavity 36 and the through hole 52 can be filled with a suitable material 56 (e.g., ink). The material 56 may fill the cavity 36 / through hole 52 to provide a substantially level surface to form one or more buildup layers on the core 37. Grinding or other planarization techniques may be performed on the core 37. [

One or more layers 39 having interconnect structures 38 may be formed on either side of the core 37, as shown in Figures 4E-4I. Formation of the buildup layer 39 may include plating the core 37 with a conductive layer 58 comprising copper, for example, as shown in Figure 4E. Next, as shown in FIGS. 4F and 4G, the conductive layer 58 may be patterned to form a conductive line 38 '. Patterning of the conductive layer 58 may include laminating a dry film 60 (e.g., photoresist) over the conductive layer 58, patterning the dry film 60 (e.g., using an appropriate exposure technique) , And etching the conductive layer 58 using the patterned dry film 60 as a mask. Then, the dried film 60 can be removed.

In FIG. 4h, a buildup layer 39 'may be laminated over the conductive line 38' (shown faintly). The laminate of the buildup layer 39 'may comprise a curing process (e.g., heat treatment or pressure treatment). The opening 62 may be patterned within the buildup layer 39 '(e.g., via laser piercing), and the opening 62 may be aligned with the conductive line 38'. As shown in Figure 4i, additional conductive lines 38 "are formed using processes (e.g., conductive layer plating and patterning) that are substantially the same as those shown in Figures 4E-4H for forming conductive lines 38 ' The conductive layer plating process used to form the conductive lines 38 &quot; may be formed by plating the openings 62 (not shown in Figure 4h) to form a buildup layer &lt; RTI ID = 0.0 & (Not shown) for interconnecting the conductive lines 38 ', 38 "through the openings 62. The conductive lines 38" As shown in FIG. The process steps shown in FIGS. 4E-4I may be repeated as desired to form any build-up layer (e.g., power, ground, and / or signal layer) in the package substrate 30. 4E-4I illustrate forming the interconnect structure 38 / buildup layer 39 only on one side of the core 37, it will be appreciated that the same process may be performed on the opposite side of the core 37, Structure 38 / build-up layer 39 as shown in FIG.

4J, a solder resist 64 may be formed on the buildup layer 39 (e.g., on both sides of the core 37). Next, as shown in Fig. 4K, the cavity 36 can be patterned in the package substrate 30. Fig. The formation of the cavity 36 may include patterning the solder resist 63 (e.g., using an exposure technique), laser etching the buildup layer 39 using the material 54 'as a laser stop layer . &Lt; / RTI &gt; Thus, the cavity 36 can not extend through the package substrate 30. Furthermore, the patterning of the solder resist 64 may pattern an opening (not shown) around the cavity 36 to expose the interconnect structure 38 in the buildup layer 39. These openings may be plated with a suitable material (e.g., nickel, aluminum, etc.) to form a contact pad 66 on the package substrate 30. [ The contact pad 66 may be electrically connected to the interconnect structure 38 in the buildup layer 39. Subsequently, a connector 68 (e.g., a solder ball) may be formed on the contact pad 66 for bonding with the die stack 10/32, as shown in FIG.

Referring again to FIG. 11, when the die stack 10/34 is bonded to the package substrate 30, the die 32 may be disposed at least partially within the cavity 36. In a top view (not shown) of the package 100, the cavity 36 may surround the die 32. Thus, the bonded structure can preferably have a relatively small form factor and high bandwidth. The die 32 may also be electrically connected to the package substrate 30 via the RDL 18 and connectors 24/26. In some embodiments, the die 10 may include less or no substrate through vias TSV for electrically connecting the die 32 to the package substrate 30. The cost of manufacturing the die 10 can be further reduced by reducing the number of TSVs.

Next, referring to FIG. 1M, a heat dissipating feature 40 is disposed on the die 10. The heat dissipation feature 40 may be disposed on the surface of the die 10 opposite the RDL 18, the connector 24, and the die 32. The heat dissipating feature 40 may be a high thermal conductivity, such as a contour lid having a wattage per meter kelvin of about 200 W / mK or more and a contour lid of about 400 W / Or the like. For example, the heat dissipating features 40 may include metals and / or metal alloys such as Al, Cu, Ni, Co, combinations thereof, and the like. The heat dissipation feature 40 may also be formed of a composite material such as silicon carbide, aluminum nitride, graphite, or the like. In some embodiments, the heat dissipating features 40 may also extend above the surface of the molding compound 16.

The package 100 is not used to be electrically connected to the die 32 or the package substrate 30 as compared to a conventional 3D IC in which the package substrate 30 and the die 32 are disposed on both sides of the die 10 (10 ') to the die (10). Thus, the heat dissipating pitch 40 can be placed directly on the surface 10 'of the die 10 for improved heat dissipation.

An interfacing material 42 may be disposed between the heat dissipating features 40 and the die 10 / molding compound 16. The interfacial material 42 may comprise a thermal interface material (TIM), such as a polymer having a good thermal conductivity of at least about 5 W / m 占 내지, such as about 3 W / m 占 K (watts per meter kelvin) . Because the TIM can have good thermal conductivity, the TIM can be placed (e.g., in contact) directly between the die 10 and the heat dissipating features 40. The interface material 42 may also include an adhesive (e.g., epoxy, silicone resin, etc.) for attaching the heat spreading lid 40 to the die 10 / molding compound 16. The adhesive used may be more adhesive and thermally conductive than TIM. For example, the adhesive used may have a thermal adhesion of less than about 0.5 W / m · K. Thus, the bonding portion of the interface material 42 can be disposed on a region where the heat radiation requirement is low (for example, on the surface of the molding compound 16).

After attachment of the heat dissipating feature 40, a marking process (e.g., laser marking) may be performed for display on the package 100. 1N, a connector 44 (e.g., a ball-and-array (BGA) ball) is mounted on the surface of the package substrate 30 opposite the connector 26 and the die stack 10/32 . The connector 44 may be used to electrically connect the package 100 to a motherboard (not shown) or another device component of the electrical system.

FIG. 1n shows the completed package 100. Because the die 32 is disposed within the cavity 36 of the package substrate 30, the package 100 can have a relatively small form factor and high bandwidth. By including the RDL 18, it is possible to further increase the number of I / O pads relative to the die stack 10/32, thereby achieving various performance advantages such as increased speed and reduced power consumption. In addition, the package substrate 30 and the die 32 are disposed on the same side of the die 10 so that the heat dissipating features 40 can be placed directly on one side of the die 10 for improved heat dissipation.

FIG. 2 shows a cross-sectional view of a package 200 according to various alternative embodiments. Package 200 is substantially similar to package 100 and like reference numerals designate like elements. The contoured ring portion 40 'that may be included in the heat dissipation feature 40 may extend through the die 10 and the RDL 18 to the top surface of the package substrate 30. In a top view (not shown) of the package 200, a contoured ring portion 40 'may surround the die 10. The contoured ring portion 40 'is formed of substantially the same material as the remaining portion of the heat-radiating lid 40 (e.g., high Tk material) and can provide additional heat dissipation for the package 200. [ The contoured ring portion 40'can be attached to the package substrate 30 using any suitable material such as an adhesive layer 42 'disposed between the contoured ring portion 40' and the package substrate 30. [

3A-3E illustrate various intermediate steps for fabricating the package 300 in accordance with an alternative embodiment. Figure 3A shows a plurality of dies 10 having an RDL 18 and a connector 26 formed on the die 10. The various features shown in Fig. 2A can be formed using steps substantially similar to those formed in Figs. 1A-IJ, wherein like numerals denote like elements and are substantially similar to those features. Thus, the details of the features and their formation are omitted for the sake of brevity. 2A, however, the die 10 (including the RDL 18 and the connector 24) is separated from the carrier (e.g., the carrier 14) without being bonded onto the die 32 . Also, the connector 24 may not be formed on the RDL 18. Instead, the structure shown in FIG. 2A includes a connector 26 that belongs to substantially the same size on the RDL 18. FIG. For example, the connector 26 may be a C4 bump.

Figure 3b illustrates unification of the die 10 (e.g., along a scribe line with any pick and place tool) and attachment of the die 10 to the package substrate 30 via the connector 26 . In particular, the die 10 may be bonded to the package substrate 30 before the die 32 is attached to the package 300.

The configuration of the package substrate 30 in the package 300 may be changed from the configuration in the package 100. [ For example, the cavity 36 may be disposed on the opposite surface (not the same surface) of the package substrate 30. [ Within the package 300, the die 10 may be bonded to the surface 30A of the package substrate 30. The surface 30A may be substantially horizontal. The package substrate 30 may further include a surface 30B (e.g., in the cavity 36) and a surface 30C opposite the die 10. By including the cavity 36, the surfaces 30B and 30C may not be substantially horizontal. For example, in the orientation shown in FIG. 3B, the surface 30B may be higher than the surface 30C.

The formation of the package substrate 30 having the cavities 36 may be performed by forming the core 37, the buildup layer 39B (e.g., placed on the opposite side of the core 37 from the die 10) and / 39A) (e.g., disposed on the same side of die 10 and core 37). In various embodiments, the cavity 36 can not extend through the package substrate 30.

FIG. 3C illustrates the formation of various other features of the package 300. For example, reflow can be done on the connector 26 and the underfill 46 can be distributed around the connector 26. The connector 44 may be attached to the surface 30C of the package substrate 30 in opposition to the die 10. In addition, heat dissipating features 40 may be disposed on the die 10 / molding compound 16. An interfacial material 42 (including a TIM and / or an adhesive material) may be disposed between the heat dissipating features 40 and the die 10 / molding compound 16.

Functional testing may then be performed on the package 300 prior to attachment of the die 32. For example, the electrical connection between the die 10 and the package substrate 30 can be tested. If the package 300 passes the test, the die 32 may be attached to the package 30 using a connector 24 formed, for example, as shown in FIG. 3D. The connector 24 may be formed on the die 32 using any suitable method prior to attaching the die 32 to the package 300. By performing a functional test on the package 300 prior to attachment of the die 32, the die 32 can be attached only to a known good package. A package that fails the functional test is not attached to the die 32. Thus, cost savings can be achieved by avoiding the attachment of the die 32 to the defective package.

The connector 24 (e.g., micro-bumps) may be formed on the die 32 using any suitable method. The connector 24 may be of a different size than the connector 26 and the connector 24 may be attached to a contact pad on the package substrate 30. [ The connector 24 is mounted on the die 10 via the interconnection structure 38 (e.g., interconnect structure 38 '), the connector 26, and the RDL 18 in the package substrate 30, Can be electrically connected.

The die 32 may be disposed within the cavity 36 of the package substrate. Within the package 300, the die 32 and the die 10 may be disposed on opposite sides of the package substrate 30. Attaching the die 32 may include stepping the package 300 upside down (e.g., causing the connector 24 to point upward) and aligning the die 32 within the cavity 36. (E.g., to electrically connect the die 32 to the die 10 / package substrate 30), and the underfill 34 may be dispensed around the connector 24 .

With the configuration of the package 300, a heat dissipation pitch (e.g., heat dissipation pitch 70) may be disposed on the surface die 32. [ The interface material 72 may be disposed between the heat dissipating pitch 70 and the die 32 so that the interface material 72 may be in physical contact with the die 32. [ The heat dissipation feature 70 and the interface material 72 may be substantially the same as the heat dissipation feature 40 and the interface material 42, respectively. Alternative manufacturing processes can then be used to form the package 300.

Figures 5A and 5B show cross-sectional views of semiconductor packages 400 and 500, respectively. The packages 400 and 500 are substantially similar to the package 100, and the same reference numerals denote the same elements. On the other hand, the packages 400 and 500 may further include a plurality of dies 10 (denoted by 10A and 10B). Dies 10A and 10B may be part of the same fan-out package. For example, the dies 10A and 10B may be surrounded by the molding compound 14 and the RDL 18 may be formed on the surfaces of the dies 10A and 10B. The RDL 18 can electrically connect the dies 10A, 10B to the die 32. [ Also, the dies 10A, 10B may be substantially horizontal. The formation of the dies 10A, 10B may be substantially the same as the process shown in Figs. 1A-IJ, but the unification can be done at different locations (e.g., the scribe lines for the pick and place tool are configured at different locations . In some embodiments, the die 32 may be disposed in a cavity formed in the substrate 30 (as shown in Fig. 5A). In another embodiment, the die 32 may be disposed in the through hole 74 in the substrate 30 (as shown in Fig. 5B). The through hole 74 may be formed in the substrate 30 using, for example, a laser drilling process.

6A and 6B illustrate cross-sectional and plan views of a package substrate 150 in accordance with some alternative embodiments. Fig. 6A shows a sectional view and Fig. 6B shows a plan view. The package substrate 150 includes a coreless buildup portion 316 and a laminate portion 318 on the coreless buildup portion 316. In various embodiments, the coreless build-up portion 316 is a thin profile (e.g., because there is no core) so that it can be integrated into an advanced node application to achieve the full scene package profile.

The coreless buildup portion 316 may include one or more embedded pattern process (EPP) layers, such as one or more buildup layers 106 (e.g., dielectric layers), including conductive features 102, . The conductive feature 102 may be at least partially exposed at the top surface 316A of the coreless build-up portion 316 and the exposed portion of the conductive feature 102 may be exposed at a portion of the die (e.g., die 202 in FIG. 7A) And may be used as a bump pad for bonding to the package substrate 150. In some embodiments, the conductive features 102 may have a pitch of about 40 [mu] m to about 150 [mu] m for fine pitch bonding. Depending on the substrate design, other dimensions for the conductive features 102 may be employed in other embodiments.

In addition, the conductive features 102 may be electrically connected to the conductive features 104. For example, one or more interconnection layers (not shown) having conductive interconnect structures (e.g., conductive lines and / or vias) that electrically connect the conductive features 102 and 104 are formed on the core- As shown in FIG. Conductive feature 102, on the other hand, may be a conductive trace line that may be physically connected to conductive feature 104. The conductive feature 104 may be used to provide electrical connection to the contact pad 110 on the bottom surface 316B of the coreless build-up portion 316, electrically connected to the via 108. For example, in the illustrated embodiment, vias 108 extend through the dielectric layer 106. The solder resist 122B may be disposed on the bottom surface 316B of the coreless buildup portion 316 and the opening in the solder resist 122B may expose the contact pad 110. [ An external connector (e.g., a ball grid array (BGA) ball, see FIG. 7A) may then be placed on the contact pad 110.

The laminate portion 318 may be disposed over the coreless build-up portion 316. In various embodiments, the laminate portion 318 includes a dielectric layer 112 and a via 116 extending through the core 114. The dielectric portion 112 may be used to join the core 114 to the coreless build-up portion 316. The laminate portion 318 further includes a cavity 120 in which a die (e.g., die 202 of FIG. 7A) bonded to the conductive feature 102 may be disposed. In some embodiments, the cavity 120 may have a transverse dimension W greater than about 30 micrometers and a longitudinal dimension T greater than about 30 micrometers.

The laminate portion 318 further includes a contact pad 118 that may be used to bond another package feature, such as another device die, another device package (e.g., package 204 of FIG. 7A), and the like. In some embodiments, the contact pad 118 may have a pitch of about 200 [mu] m to about 400 [mu] m for fine pitch bonding. Depending on the substrate design, other dimensions for the conductive features 118 may be employed. The contact pad 118 (and other underlying features of the laminate portion 318) may be stopped by the cavity 120 and the exposed conductive pitch 102, as shown in the top view of the package substrate 150 of Figure 6B have.

The via 116 is electrically connected to the conductive pitch 104 and the dimensions of the via 116 are such that the standoff height sufficient to place the die 202 on the cavity 120 (e.g., vertical dimension T) ). &Lt; / RTI &gt; Vias 116 and contact pads 118 may be used in place of conventional large solder balls for bonding another device package to reduce the risk of solder bridging and increase yield. In addition, the core 114 of the laminate portion 318 can provide enhanced stiffness to the deformation control of the package substrate 150. A solder resist 122A may be disposed on the core 114 and an opening may be patterned in the solder resist 122A to expose the contact pad 118. [

Figs. 7A and 7B show cross-sectional views of a package 250 having a package substrate 150 as shown in Figs. 6A and 6B. A die 202 may be disposed within the cavity 120 and bonded to the exposed conductive features 102 through a connector 206 (e.g., BGA ball, micro bump, C4 bump, etc.). In some embodiments (as shown in FIG. 7A), the underfill 212 may be distributed around the connector 206. In another embodiment (as shown in FIG. 7B), the molding compound 214 may be dispensed around the die 202 to fill the cavity 120 at least partially. Die 202 may be exposed by molding compound 214 (as shown in FIG. 7B), or molding compound 214 may cover die 202 (not shown).

In addition, another device package 204 may be bonded to the contact pad 118 by a connector 208 (e.g., BGA ball, micro bump, C4 bump, etc.). Device package 204 may include various features (not individually shown), such as one or more device dies, including die stacks, and interconnect structures (e.g., various fanout RDLs, throughvia, Poser, etc.). &Lt; / RTI &gt; In some embodiments, the package 204 may be a memory package, such as a dynamic random access memory (DRAM) package. The laminate portion 318 of the package substrate 150 provides a sufficient standoff height to allow the die 202 to be placed within the cavity 120 without contacting the package 204. [ The external connector 210 may be disposed on the contact pad 110 of the bottom surface 316B of the coreless buildup portion 316. [ The external connector 210 can be used to bond the package 250 to another package component such as an interposer, a package substrate, a printed circuit board, and the like.

8A-8N illustrate cross-sectional views of various intermediate steps for fabricating a package substrate 150 in accordance with some embodiments. The fabrication of the substrate 150 can be divided into two logic stages. In the first stage (shown in Figs. 8A-8G), the coreless buildup portion 316 is formed using the carrier 302 for temporary structural support. Subsequently, in the second stage (shown in Figs. 8h-8m), a laminate portion 318 having a cavity 120 is formed over the core-less build-up portion 316. Fig.

Referring now to FIG. 8A, there is provided a carrier substrate 302 having a seed layer 304 disposed on both sides. The carrier substrate 302 provides temporary mechanical and structural support for processing of buildup layers during subsequent processing steps. In some embodiments, the carrier 302 may comprise organic core materials such as epoxy-impregnated glass-fiber laminates, polymer-impregnated glass-fiber laminates, and the like. On the other hand, the carrier 302 may include other materials such as stainless steel, glass, and the like.

A seed layer 304 comprising a conductive material (e.g., copper) is formed on both sides of the carrier 302. The seed layer 304 is formed using any suitable process. For example, if the carrier 302 comprises an organic core material, the seed layer 304 may be formed by laminating a conductive foil (e.g., a copper foil) on both sides of the carrier 302. As another example, if the carrier 302 comprises stainless steel, glass, etc., the seed layer 304 may be formed using a plating or sputtering process.

A patterned photoresist 306 is formed on the seed layer 304 (e.g., a patterned photoresist 306 is formed on both sides of the carrier 302), as shown further in FIG. 8A. For example, a photoresist 306 may be coated or laminated as a blanket layer on each seed layer 304. Next, a portion of the photoresist 306 is exposed using a photomask (not shown). The exposed or unexposed portions of the photoresist 306 are removed depending on whether the resist used is negative or positive. The final patterned photoresist 306 may include openings 308 that expose each seed layer 304.

8B illustrates filling openings 308 with a conductive material such as copper, silver, gold, etc. to form conductive features 102, 104. As shown in FIG. Depending on the substrate design, the conductive features 102 may have different dimensions. For example, conductive features 102 may be used as bump pads for bonding device die 202 in subsequent process steps (e.g., see FIG. 3n), and through vias in subsequent process steps The conductive feature 104 may be used as a contact to form the through-via 116). Thus, the conductive features 102 may have a smaller pitch and / or width than the conductive features 104.

The filling of the openings 308 may include plating (e.g., electrochemically plating) the openings 308 with a conductive material using the seed layer 304. The conductive material may overfill the openings 308 so that planarization may be performed to remove excess portions of the conductive material over the photoresist 306. [ Planarization may include, for example, a chemical mechanical polishing (CMP) process, a mechanical grinding process, or other etch back techniques. Subsequently, a plasma ashing and / or a wet stripping process may be used to remove the photoresist 306. Optionally, after the plasma ashing process, wet dipping in a sulfuric acid (H ₂ SO ₄ ) solution may be followed to clean the structure and remove the remaining photoresist material.

Next, a buildup layer 106 is formed on both sides of the carrier 302, as shown in Fig. 8C. For example, each buildup layer 106 may be disposed over a corresponding seed layer 304 and conductive features 102/104. The build layer 106 includes dielectric materials such as prepregs (e.g., FR4 epoxy resin, M6 epoxy resin, etc.) and Ajinomoto build-up film (ABF) that can be applied by laminae can do. For example, a vacuum laminator may be used to place the dielectric material on the carrier 302 and an oven curing process may be applied to adhere the dielectric material to the seed layer 304 and the conductive features 102/104 have. As another example, a hot process process may be used to heat the dielectric material to the seed layer 304 and the conductive features 102/104 (e.g., 102/104) under suitable heat and / or pressure conditions for a suitable period of time ).

Alternatively, or additionally, the buildup layer 106 may be formed of silicon dioxide, silicon nitride, silicon oxynitride, oxide, nitrogen containing oxide, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, Or other materials. The buildup layer 106 may be formed by sputtering, spin on coating, CVD, low pressure CVD, rapid thermal CVD, atomic layer CVD, and / or plasma enhanced CVD using tetraethyl orthosilicate and oxygen as the precursor . The buildup layer 106 may also be formed by an oxidation process, such as wet or dry thermal oxidation, and / or other processes in an ambient atmosphere comprising oxygen, water, nitrogen monoxide or a combination thereof.

As further shown in FIG. 8C, the buildup layer 106 may be patterned to include openings 308 that expose the conductive features 104. The patterning of the buildup layer 106 may include any suitable process such as laser drilling and combination of photolithography and etching.

Figure 8d illustrates the formation of additional conductive features, such as conductive vias 108 and contact pads 110. [ Conductive vias 108 may be formed by filling openings 308 with a conductive material. In one embodiment, the conductive material may be formed by depositing a seed layer on the sidewalls of the opening 308. [ The seed layer (not shown) may be formed of copper, nickel, gold, any combination thereof, and / or the like. When the seed layer is deposited in the opening, tungsten, titanium, aluminum, copper, any combination thereof and / or the same conductive material is filled into the opening using, for example, an electrochemical plating process. The conductive material may be overcharged in the opening 308 to remove excess material (e.g., excess conductive material) from the surface of the buildup layer 106. In some embodiments, a planarization process, such as a CMP process, a mechanical grinding process, or other etch back technique, is used to remove excess material to form vias 108.

In addition, the contact pad 110 may be formed on the buildup layer 106. The contact pad 110 may be formed using substantially the same process as the conductive features 102/104. For example, a patterned photoresist (not shown) may be formed over the buildup layer 106. The openings in the patterned photoresist can be used to define the shape of the contact pad 110. Such openings can be filled with a conductive material, for example, by first laminating a seed layer (not shown) on the bottom and / or sidewalls of the opening and filling the opening using an electrochemical plating process. The contact pad 110 is electrically connected to the contact 104 by a via 108 and an external connector (e.g., a solder ball) may be disposed on the contact pad 110 (e.g., see FIG. 2B). Thus, two coreless build-up portions 316 are formed on both sides of the carrier 302. Although each build-up layer portion 316 includes only a single build-up layer 106, in alternative embodiments, any of the build-up layers with conductive features (e.g., conductive lines and / or vias) . 8A-8D illustrate the simultaneous formation of two buildup layer portions 316 on the carrier 302, but in an alternative embodiment, a single core-unfolded buildup portion 316 is provided on the carrier 302 ). &Lt; / RTI &gt;

8E and 8F illustrate the removal of the buildup layer portion 316 (denoted as 316 ') from the carrier 302. In some embodiments, buildup layer portion 316 'is removed using mechanical force. For example, referring to FIG. 8E, a mechanical tool 310 is wedged between the carrier 302 and the seed layer 304. The mechanical tool 310 separates between the carrier 302 and the seed layer 304 at the edge of the carrier 302. Next, a vacuum clamp 312 may be used to apply a mechanical force to both sides of the carrier 302. The vacuum clamp 312 applies a mechanical force in both directions (indicated by arrows 314) and the mechanical force physically separates the buildup layer portion 316 'from the carrier 302. In some embodiments, the buildup layer portion 316 'is separated from the carrier 302 without significantly damaging other features in the structure shown due to the relatively weak adhesive bonding between the carrier 302 and the seed layer 304 . For example, the seed layer 304 may be applied to the carrier 302 using a relatively weak lamination process (e.g., without large area curing). The weak bonding between the carrier 302 and the seed layer 304 can be further exploited by separating the carrier 302 and the seed layer 304 at the edge portion by application of the mechanical tool 310. [ Thus, the build-up portion 316 'may be removed from the carrier 302 as shown in FIG. 8F. The buildup portion 316 on the carrier 302 may also be removed using the same process.

Referring now to FIG. 8G, the seed layer 304 may be removed, for example, using a suitable etching process. Etching of the seed layer 304 may further recess the conductive features 102, 104 at the top surface of the dielectric layer 106. In some embodiments, etching of the seed layer 304 may utilize a suitable chemical etchant, depending on the material of the seed layer 304. For example, where the seed layer 304 comprises copper, a suitable chemical etchant includes a sulfuric acid (H ₂ SO ₄ ) or hydrogen peroxide (H ₂ O ₂ ) based chemical etchant. Thus, the conductive features 102, 104 may be exposed at the top surface 316A of the coreless build-up portion 316. [

Figures 8h-8m illustrate various intermediate steps of forming the laminate portion 318 over the coreless build-up portion 316. [ First, referring to FIG. 8H, core 114 may be bonded to coreless build-up portion 316 by patterned dielectric layer 112. For example, an uncured dielectric layer 112 comprising a suitable material such as a prepreg (e.g., FR4 epoxy resin, M6 epoxy resin, etc.), ABF, or the like can be applied over the coreless buildup portion 316. The dielectric layer 112 may be patterned to include a cavity 120 that can be aligned with the exposed conductive features 102. In some embodiments, the cavity 120 may be pre-patterned in the dielectric layer 112 (e.g., using a punching process) before the dielectric layer 112 is deposited on the coreless build-up portion 316. Other methods of patterning the dielectric layer 112 (before or after being laminated on the coreless build-up portion 316) may be employed. The core 114 may then be disposed over the dielectric layer 112 and a curing process may be applied to adhere the core 114 to the coreless buildup portion 316. [ The core 114 may include organic core materials such as, for example, epoxy-impregnated glass-fiber laminates, polymer-impregnated glass-fiber laminates, and the like.

8i and 8j illustrate the formation of a conductive feature in the dielectric layer 112 and core 114. First, in Fig. 8i, the opening 320 in the core 114 and the dielectric layer 112 can be patterned, for example, using a laser drilling process. The openings 320 may extend through the core 114 and dielectric layer 112 to expose the conductive features 104.

Figure 8j illustrates the formation of additional conductive features, such as conductive vias 116 and contact pads 118. Conductive vias 118 may be formed by filling openings 320 with a conductive material. In one embodiment, the conductive material may be formed by depositing a seed layer on the sidewalls of the opening 320. The seed layer (not shown) may be formed of copper, nickel, gold, any combination thereof, and / or the like. When the seed layer is deposited in the opening, tungsten, titanium, aluminum, copper, any combination thereof and / or the same conductive material is filled into the opening using, for example, an electrochemical plating process. In some embodiments, the conductive material may not fill the opening 320 completely. For example, FIG. 8K shows a top view of an exemplary via 116 that may include a hollow central portion 322. FIG. In another embodiment, the conductive material fully or substantially fills the openings 320. The via 116 may extend through the core 114 and the dielectric layer 112 to electrically connect to the conductive features 104 of the coreless buildup portion 316. [

In addition, a contact pad 118 may be formed on the core 114. The contact pad 118 may be formed using substantially the same process as the contact pad 110. For example, a patterned photoresist (not shown) may be formed on the core 114. The openings in the patterned photoresist can be used to define the shape of the contact pad 118. Such openings can be filled with a conductive material, for example, by first laminating a seed layer (not shown) on the bottom and / or sidewalls of the opening and filling the opening using an electrochemical plating process. The contact pad 118 may be electrically connected to the contact 104 by a via 116 and the contact pad 118 may be electrically connected to another package (e.g., package 204 of FIG. 7A) . &Lt; / RTI &gt;

Next, in Fig. 81, solder resists 122A and 122B are formed on the package substrate 150. Fig. The solder resist 122A may be disposed on the core 114 and the solder resist 122B may be disposed on the bottom surface of the coreless buildup portion 316. [ Solder resists 122A and 122B may be patterned to expose at least portions of the contact pads 118 and 110, respectively. The solder resists 122A and 122B may comprise a heat resistant coating material and may assist in protecting the various layers of the package substrate 150.

In FIG. 8M, a portion of the core 114 (denoted by reference numeral 114 ') on the cavity 120 is removed to expose the conductive feature 102 and to extend the cavity 120. Removal of the core portion 114 ' may be done using any suitable method, such as laser drilling, mechanical drilling, and the like. Process conditions (e.g., mechanical puncture time, laser perforation focus, etc.) can be controlled to remove the core portion 114 'without damaging the bottom features of the package substrate 150. In some embodiments, a protective layer (e.g., including a metal, not shown) may be included under the core portion 114 'to protect the underlying features upon removal of the core portion 114'. After the core portion 114 'is removed, the protective layer may also be removed to expose the conductive features 102. Thus, the package substrate 150 having the core-less build-up portion 316 and the laminated portion 318 is formed. In a subsequent process step, a die 202 is disposed on the cavity 120 and bonded to the conductive feature 102, as shown in Figure 8n. Further features may be formed around the package substrate 150 and the die 202, as shown in Figures 7A, 7B, and 9A-11B.

9A and 9B illustrate cross-sectional views of a package 450 having a package substrate 150 according to some alternative embodiments. Package 450 is similar to package 250 and like reference numerals designate like elements. A die 202 is disposed within the cavity 120 and may be bonded to the exposed conductive features 102 through the connector 206. In some embodiments (as shown in FIG. 9A), the underfill 212 can be distributed around the connector 206. In another embodiment (as shown in FIG. 9B), the molding compound 214 may be dispensed around the die 202 to fill the cavity 120 at least partially. The die 202 may be exposed by the molding compound 214 (not shown) or the molding compound 214 may cover the die 202 (shown in FIG. 9B).

9A and 9B, another device package 204 may be disposed on the opposite side of the coreless build-up portion 316 to the die 202. In this case, For example, the device package 204 may be bonded to a contact pad 110, not by reference numeral 118, The contact pad 110 is positioned on the bottom surface 316B of the coreless build-up portion 316 (in the orientation shown in FIGS. 9A and 9B) because the cavity 120 does not extend through the coreless buildup portion 316 May be disposed in a full grid array on a top surface (shown as a top surface). Thus, additional contacts may be provided for package 204 bonding. The laminate portion 318 of the package substrate 150 provides a sufficient standoff height such that the die 202 can be disposed within the cavity 120. In this embodiment, The external connector 210 may be disposed on the contact pad 118 on the same side of the die 202 and the package substrate 150. The external connector 210 may be used to bond the package 450 to another package component such as an interposer, a package substrate, a printed circuit board, and the like.

10 illustrates a cross-sectional view of a package 550 having a package substrate 150 according to some alternative embodiments. The package 550 is similar to the package 450 and the same reference numerals denote the same elements. In the package 550, however, the interposer 216 is attached to the contact pad 110 by a connector 218 (e.g., BGA ball, C4 bump, micro bump, etc.) instead of another device package 204 Can be bonded. Interposer 216 may include conductive features such as through vias 222. (E.g., die 220, another device package, etc.) may be bonded to interposer 216 and conductive features (e.g., via vias 222) in interposer 216 may be bonded to another package The component can be electrically connected to the package substrate 150.

11A and 11B illustrate cross-sectional views of an intermediate step in fabricating a package 650 with a package substrate 150 in accordance with some alternative embodiments. Package 650 is similar to package 450 and like reference numerals designate like elements. Referring first to FIG. 11A, a pre-solder 224 may be disposed on a subset of contact pads 110 (designated 110A). While the other contact pads 110B may remain exposed. The pre-solder can be disposed in the opening defined by the solder resist 122B. The pre-solder 224 may then be used to bond another device die 220 to the contact pad 110A. Contacts 226 (e.g., BGA balls, C4 bumps, micro bumps, etc.) on die 220 may be bonded with pre-solder 224. On the other hand, the pre-solder 224 may be omitted and the contact 226 may be directly bonded onto the contact pad 110A.

After the die 220 is bonded, the underfill 228 may be dispensed between the die 220 and the package substrate 150, as shown in FIG. 11B. Another package component (e.g., package 204) may be bonded to contact pad 110B by solder ball 230, as further shown in FIG. 11B. In some embodiments, bonding of package 204 may include forming pre-solder on contact pad 110B first. The solder ball 230 should be large enough to provide a standoff height sufficient to place the die 220 between the package 204 and the package substrate 150.

Figure 12 illustrates a process flow 700 for forming a package (e.g., a package 250, 450, 550, or 650) in accordance with some embodiments. At step 702, a coreless buildup portion (e.g., a coreless buildup portion 316) is formed with exposed conductive features (e.g., bump pad 102 and contact pad 104) For example, various buildup layers with conductive features may be formed on the temporary core to provide structural support, and the buildup layer may be formed on the temporary core, The seed layer can be removed to expose the conductive features (e.g., features 102, 104) in the buildup layer.

Next, at step 704, a core (e.g., core 114) is attached to the coreless build-up portion. In some embodiments, the core is attached using a dielectric layer (e.g., dielectric layer 112) that can be patterned to include a cavity (e.g., cavity 120). In step 706, a through hole (e.g., via 116) extending through the core is formed. The through holes may be electrically connected to the first subset of conductive features (e.g., contact pad 104). In step 708, a contact pad (e.g., contact pad 118) may be formed on the through hole.

In step 710, the core portion (e.g., portion 116 ') of the core is removed to form the cavity 120. The cavity can be defined by the remaining portion of the core that can surround the cavity. A second subset of conductive features (e.g., bump pads 102) may be exposed by cavity 120. Thus, a package substrate (e.g., substrate 150) is formed according to some embodiments. Subsequently, at step 712, a die (e.g., die 202) may be bonded to the second subset of conductive features (e.g., bump pad 102). The die may be disposed within the cavity. In step 714, a connector may be formed on the contact pad on the throughvia. In some embodiments, other package components (e.g., package 204) may be bonded to the contact pads on the via. In another embodiment, another package component (e.g., package 204, interposer 216, die 220, etc.) may be coupled to a contact pad formed on the opposing face of the coreless build- Or may be bonded.

Thus, as described above, the package substrate may include a cavity. A first die may be bonded to the package substrate, the cavity being on the same side of the first die and the package substrate, or on the opposite side of the package substrate with the first die. One or more second die may be bonded to the package substrate and the first die, and the second die may be disposed within the cavity. The second die may be directly bonded to the first die or the second die may be bonded directly to the package substrate. Thus, with this package substrate configuration, it is possible to package with a relatively thin form factor. Also, with this configuration of the die in the package, a relatively simple heat dissipation element can be attached to at least the first die.

According to one embodiment, a device package includes a package substrate and first and second die bonded to the package substrate. The package substrate includes a buildup portion including a first contact pad and a plurality of bump pads. The package substrate includes an organic core attached to a buildup portion, a through via extending through the organic core and electrically connected to the first contact pad, a second contact pad on the through via, and a connector on the second contact pad, And a cavity extending through the organic core. The cavity exposes a plurality of bump pads, and the first die is disposed on the cavity and bonded to the plurality of bump pads.

According to another embodiment, a method of forming a device package includes providing a package substrate and bonding the first and second die to the package substrate. The package substrate includes a buildup portion having a plurality of bump pads, an organic core attached to the buildup portion, a through via extending through the organic core, and a cavity extending through the organic core. The through vias are electrically connected to conductive features within the first build-up portion, and the plurality of bump pads are exposed by the cavities. The bonding of the first die includes bonding the first die to the plurality of bump pads, wherein the first die is at least partially disposed within the cavity.

According to yet another embodiment, a method of forming a device package includes forming a buildup portion having a first contact pad and a plurality of bump pads. The method includes attaching an organic core to a build-up portion, patterning an opening extending through the organic core, forming a through via in the opening to contact the first contact pad, Forming a second contact pad on the via; and forming a connector on the second contact pad. Subsequently, a portion of the organic core is removed to form a cavity extending through the remainder of the organic core. The cavity exposes a plurality of bump pads.

The foregoing is a summary of features of the various embodiments to enable those skilled in the art to more fully understand aspects of the disclosure. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to accomplish the same purpose and / or achieving the same effects of the embodiments presented herein. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of this disclosure and that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the disclosure.

Claims (10)

In a device package,
As a package substrate,
A build-up portion including a first contact pad and a plurality of bump pads on a first surface,
A dielectric layer attached to the first surface of the buildup portion;
An organic core attached to the dielectric layer,
A through via extending through the organic core and electrically connected to the first contact pad,
A second contact pad on the through via,
A connector on the second contact pad,
A cavity extending through the organic core and the dielectric layer, the cavity exposing the plurality of bump pads,
The package substrate comprising:
A first die disposed within the cavity and bonded to the plurality of bump pads,
A second die bonded to the package substrate,
An underfill disposed between the first die and the package substrate,
/ RTI &gt;
Wherein the underfill is different from the dielectric layer. The device package of claim 1, wherein the package substrate is bonded to the second device package including the second die by the connector. The package of claim 1, wherein the package substrate further comprises a third contact pad on an opposite surface of the build-up portion to the first surface, and wherein the third contact pad comprises a second device A device package in which packages are bonded. The device package of claim 1, further comprising an interposer bonded to the package substrate, wherein the second die is bonded to the opposite face of the interposer to the package substrate. 2. The device package of claim 1, further comprising a third device package bonded to the package substrate, wherein the second die is disposed between the third device package and the package substrate. delete delete The device package of claim 1, wherein the build-up portion is a coreless build-up portion. A method of forming a device package,
Providing a package substrate, the package substrate comprising:
A buildup portion including a plurality of bump pads,
An organic core attached to the build-up portion by a dielectric layer,
A throughvia extending through the organic core and electrically connected to a conductive feature in the buildup portion;
A cavity having a first height extending through the organic core and the dielectric layer and exposing the plurality of bump pads;
Bonding a first die disposed at least partially within the cavity to the plurality of bump pads,
Bonding a second die to the package substrate,
Wherein the first die has a second height that is less than the first height. A method of forming a device package,
Forming a buildup portion including a first contact pad and a plurality of bump pads,
Attaching an organic core to the buildup portion;
Patterning an opening extending through the organic core to expose the first contact,
Forming a through via in the opening to contact the first contact pad;
Forming a second contact pad on the through via,
Forming a connector on the second contact pad;
Removing a portion of the organic core to form a cavity extending through the remainder of the organic core
Wherein the cavity exposes the plurality of bump pads.

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