KR101761188B1 - semiconductor memory device and method of controlling the same - Google Patents

Abstract

The semiconductor memory device includes a memory array, an address controller, and a logic circuit. The memory array includes a plurality of banks divided into a first bank block and a second bank block. The address control unit accesses the memory array. Wherein the logic circuit causes the first bank block and the second bank block to operate in common in a first operation mode and the first bank block and the second bank block in a second operation mode based on a command and an address signal, And a logic circuit for controlling the address controller to be operated individually.

Description

Description SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device and a control method thereof.

A semiconductor memory device such as a DRAM performs various operations according to the control of the memory controller. The amount of data to be processed in modern multimedia devices is increasing and data processing speed is increasingly required. As the operating speed of such a semiconductor memory device increases, more and more frequent accesses are required to the core, such as the memory cells of the semiconductor memory device.

It is an object of the present invention to provide a semiconductor memory device capable of solving a column access frequency limitation.

It is another object of the present invention to provide a method of controlling the semiconductor memory device.

According to an aspect of the present invention, there is provided a semiconductor memory device including a memory array, an address controller, and a logic circuit. The memory array includes a plurality of banks divided into a first bank block and a second bank block. The address control unit accesses the memory array. Wherein the logic circuit causes the first bank block and the second bank block to operate in common in a first operation mode and the first bank block and the second bank block in a second operation mode based on a command and an address signal, And a logic circuit for controlling the address controller to be operated individually.

In one embodiment, the logic circuit is configured to receive the same internal address signal decoded from the address signal in the first bank block and the second bank block in the first mode of operation and to perform an operation indicated by the command The address control unit can be controlled.

In an embodiment, the logic circuit is configured such that in the second mode of operation, the first bank block and the second bank block receive respective first and second internal address signals decoded from the address signal, And to control the address control unit to perform an operation.

In one embodiment, in the first operation mode, the first bank block and the second bank block are divided into at least two bank groups in response to the command and the address signal, It is possible to operate in the same one of the non-group modes accessible in each bank unit.

When the first bank block and the second bank block operate in the group mode, consecutive commands for the banks included in the same group can be activated with a temporal gap.

When the first bank block and the second bank block operate in the group mode, consecutive commands for the banks included in different groups may be activated in a gapless manner.

In an embodiment, the logic circuit comprises a command decoder for decoding the command and providing a mode register set (Binary MRS) command, and a controller for controlling the address controller in response to the MRS command and the address signal 1 mode control signal and a second mode control signal.

 The first mode control signal designates an operation mode of the first bank block and the second bank block and the second mode control signal designates a group mode of the first bank block and the second bank block .

In one embodiment, the first column access time when at least one bank block among the first bank block and the second bank block operates in a group mode accessible in a group unit including at least two banks, At least two times greater than the second column access time when at least one of the one bank block and the second bank block operates in a non-group mode accessible in each bank unit.

According to an aspect of the present invention, a method for controlling a semiconductor memory device includes dividing a memory cell array into a first bank block and a second bank block each having a plurality of banks. The first bank block and the second bank block are accessed in common in the first operation mode based on the command and the address signal. And the first bank block and the second bank block are individually accessed in the second operation mode based on the command and the address signal.

According to embodiments of the present invention, it is possible to solve the frequency limitation problem of column access by separately grouping the bank blocks according to the operation mode.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
2 is a block diagram showing the configuration of the memory array and the address control unit of FIG.
3 shows an MRS command according to an embodiment of the present invention.
Figures 4 and 5 illustrate the operation of the bank blocks of Figure 1 according to the operating mode.
FIG. 6 shows the operation of the bank blocks of FIG. 1 according to the first and second mode control signals.
7 is a table showing address pairs of the semiconductor memory device of FIG.
8 is a table showing the addressing scheme of the semiconductor memory device of Fig. 1 according to the storable capacity.
9 is a table showing bank groups according to the storable capacity.
10 is a timing chart showing the operation of the semiconductor memory device of FIG. 1 according to an embodiment of the present invention.
11 is a block diagram illustrating a memory system in accordance with one embodiment of the present invention.
12 to 15 are views showing examples of a memory module according to embodiments of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Similar reference numerals have been used for the components in describing each drawing.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

1, a semiconductor memory device 10 according to an embodiment of the present invention includes a logic circuit 100, an address register 200, an address control unit 400, a memory array 300, and an input / output circuit 50).

The logic circuit 100 receives a plurality of control signals 20, / CS, / WE, / CAS, / RAS and address signals 30, A0 to A12, BA0 to BA3, The address control unit 400 accesses the memory array 300 based on the command and address signals A0 to A12 and BA0 to BA3 indicated by the address signals CS, / WE, / CAS and / RAS. The memory array 300 includes a first bank block 310 and a second bank block 320 as described below with reference to FIG. The first bank block 310 includes a plurality of banks 311 to 318 and the second bank block 320 includes a plurality of banks 321 to 328. The logic circuit 100 causes the first bank block 310 and the second bank block 320 to operate in common in the first operation mode based on the command and address signals A0 to A12 and BA0 to BA3, In the second operation mode, the address controller 400 is controlled so that the first bank block 310 and the second bank block 320 are individually operated. The logic circuit 100 may also receive a clock enable signal / CKE, a clock signal CK, and an inverted clock signal / CK.

The address register 200 receives the address signal 30 and outputs the received address signals A0 to A12 and BA0 to BA3 to the logic circuit 100 in synchronism with the clock signal CK or the inverted clock signal / To the address control unit (400).

The input / output circuit 50 provides the data DQ to the memory array 300 or the data DQ from the memory array 300 to the outside.

The logic circuit 100 includes a command decoder 110 and a mode register 120. The command decoder 110 decodes a command represented by a plurality of control signals 20, / CS, / WE, / CAS and / RAS and outputs a mode register set (MRS) (120). The mode register 120 outputs the mode control signals MCS1 and MCS2 to the address control unit 400 in response to the MRS command MRS CMD supplied from the command decoder 110. Here, May be related to the operation mode of the first bank block 310 and the second bank block 320 of FIG. 2 and the second mode control signal MCS2 may be related to the operation mode of the first bank block 310 and the second bank block 320 of FIG. May be associated with the group mode and the non-group mode of each of the two bank blocks 320.

2 is a block diagram showing the configuration of the memory array and the address control unit of FIG.

Referring to FIG. 2, the memory array 300 includes a first bank block 310 and a second bank block 320. The first bank block 310 may include a plurality of banks 311 to 318 and the second bank block 320 may include a plurality of banks 321 to 322. In FIG. 2, although the memory array 300 is formed of sixteen banks, and the first bank block 310 and the second bank block 320 are each shown to include eight banks, in another embodiment, Depending on the capacity of the data, the memory array 300 may be composed of eight banks. In this case, the first bank block 310 and the second bank block 320 may each be constituted by four banks.

The address control unit 400 may include an address decoder 410, an address multiplexer 420, and a decoder unit 430. The decoder unit 430 includes a first row decoder 431, a first column decoder 432, a second row decoder 433, a second column decoder 433, a first bank decoder 435, Lt; RTI ID = 0.0 > 436 < / RTI > The first row decoder 431, the first column decoder 432 and the first bank decoder 435 access the first bank block 310 and the second row decoder 433, the second column decoder 433, And the second bank decoder 436 access the second bank block 320.

The address decoder 410 decodes the address signals A0 to A12 and BA0 to BA3 provided from the address register 200 of FIG. 1 and provides them as an internal address IADD. The address multiplexer 420 multiplexes the internal address IADD in response to the first and second mode control signals MCS1 and MCS2 and supplies the row address RADD, the column address CADD, and the bank address BADD to the address (430).

More specifically, when the first mode control signal MCS1 indicates the first non-thread mode, the first row decoder 431 and the second row decoder 433 are provided with the same row address, The first column decoder 432 and the second column decoder 434 are provided with the same column address. When the first mode control signal MCS2 indicates a second mode of operation, a first row decoder 431 and a second row decoder 433 are provided with separate row addresses and a first column decoder 432, And the second column decoder 434 are also provided with separate column addresses. When the second mode control signal MCS2 indicates the group mode, the first bank decoder 435 causes the first bank block 310 to operate in the group mode in response to the bank address BADD, The third bank block 435 causes the first bank block 310 to operate in the group mode in response to the bank address BADD.

3 shows an MRS command according to an embodiment of the present invention.

In general, the MRS command is divided into an address code portion of A0 to A12 and a bank address code portion of BA0 to BA3. Here, the bank address code portion of BA0 to BA3 designates the mode of the MRS. The address code portion of A0 to A12 is a portion for specifying an operation code (Operational Code) of the mode determined by the bank address code portion of BA0 to BA3. In the MRS command according to the embodiment of the present invention, the first operation mode or the second operation mode is determined by the logic level of the address code A12, and the group mode or the non-group mode is selected by the address codes A11 to A10 Can be determined. In addition, various other operation modes (for example, self refresh, internal clock, RDQS mode, etc.) can be designated by the address codes A9 to A0.

For example, when the address code A12 is at the logic low level, the first mode control signal MCS1 designates the first operation mode. When the address code A12 is at the logic high level, the first mode control The signal MCS2 designates the second operation mode. When the address code A11 is at a logic low level, it specifies the non-group mode of the banks regardless of the logic level of the address code A10. When the address code A11 is at the high level, . At this time. A gap between accesses of consecutive commands among the banks belonging to different groups can be determined according to the logic level of the address code A10.

Figures 4 and 5 illustrate the operation of the bank blocks of Figure 1 according to the operating mode.

4 shows the operation of the bank blocks 310 and 320 when the first mode control signal MCS1 indicates the first operation mode.

Referring to FIG. 4, when the first mode control signal MCS1 indicates the first operation mode since the address code A12 is low level, the first row decoder 431 and the second row decoder 433 have the same The same column address CADD is applied to the first column decoder 432 and the second column decoder 434 so that the first bank block 310 and the second bank block 320 The data DQ is written to the same position or the data DQ is read from the same position of the first bank block 310 and the second bank block 320. At this time, the first bank block 310 and the second bank block 320 operate in a non-group mode or a group mode in common according to the second mode control signal MS.

5 shows the operation of the bank blocks 310 and 320 when the first mode control signal MCS1 indicates the second operation mode.

5, when the first mode control signal MCS2 indicates the second operation mode since the address code A12 is high level, the first row address RADD1 is input to the first row decoder 431 And the second row address RADD2 is input to the second row decoder 433. [ A first column address CADD1 is input to the first column decoder 432 and a second column address CADD2 is input to the second column decoder 434. [ The data DQ1 and DQ2 are written to the first bank block 310 and the second bank block 320 at different positions or the data DQ1 and DQ2 are written from the other positions of the first bank block 310 and the second bank block 320, Data DQ1 and DQ2 are read out. At this time, the first bank block 310 and the second bank block 320 operate individually in either a group mode or a non-group mode according to the second mode control signal MS. For example, the first bank block 310 and the second bank block 320 may operate in a non-group mode or a group mode, respectively. Also, any one of the first bank block 310 and the second bank block 320 may operate in a group mode and the other may operate in a non-group mode.

FIG. 6 shows the operation of the bank blocks of FIG. 1 according to the first and second mode control signals.

In FIG. 6, the first mode control signal MCS1 indicates a second operation mode (thread mode), and the first bank block 310 and the second bank block 320 operate separately. The second mode control signal MCS2 corresponding to the first bank block 310 indicates a group mode so that the banks 311 to 318 of the first bank block 310 are connected to the first group (GPA), groups 313 and 314 form a second group GPB, groups 315 and 316 form a third group GPC, groups 317 and 318 form a third group GPC, To form the fourth group (GPC). At this time, the second mode control signal MCS2 corresponding to the second bank block 320 indicates the non-group mode, and the banks 321 to 328 of the second bank block 320 operate in the non-group mode. That is, when the one mode control signal MCS1 indicates the second operation mode, the operations of the first bank block 310 and the second bank block 320 are individually controlled by the second mode control signal MCS2 Lt; / RTI >

That is, the first mode control signal MCS1 may be composed of one bit, and the second mode control signal MCS2 may be composed of two bits. The following table shows each bit of the first mode control signal MCS1 and the second mode control signal MCS2.

[table]

That is, when the first mode control signal MCS1 indicates a first operation mode because the first mode control signal MCS1 is at a logic low level, the two bits of the second mode control signal MCS2 have the same logic level, The two bank blocks 320 operate simultaneously in the group mode or in the non-group mode. Also, when the first mode control signal MCS2 is at a logic high level to indicate the second operation mode, the two bits of the second mode control signal MCS2 may have the same logic level or may have different logic levels. When the first mode control signal MCS2 is at a logic high level to indicate the second operation mode and the two bits of the second mode control signal MCS2 have different logic levels, the first bank block 310 may operate in the group mode and the second bank block 320 may operate in the non-group mode.

7 is a table showing address pairs of the semiconductor memory device of FIG.

1, a clock signal CK and an inverted clock signal / CK are received. The address signals BA3 to BA0 and A12 to A8 at the rising edge of the clock signal CK are supplied to the semiconductor memory device of FIG. The address signals A3, A4, A5, A2, RFU, A6, A0, A1 and A7 are applied to the address signals BA3 to BA0 and A12 to A8 at the rising edge of the inverted clock signal / ) Through the same pin. Therefore, the number of pins required can be reduced.

8 is a table showing the addressing scheme of the semiconductor memory device of Fig. 1 according to the storable capacity.

Referring to FIG. 8, it is understood that the address signals BA0 to BA2 are used as the bank address BADD in the capacity of 512M, and the address signals BA0 to BA3 are used as the bank address BADD in the 1G and 2G capacitors . In addition, the row address (RADD) and the column address (CADD) used in the X32 mode and the X16 mode can be known from 512M, 1G and 2G capacitors, respectively.

9 is a table showing bank groups according to the storable capacity.

Referring to FIG. 9, it can be seen that, in the capacity of 512M, two banks of eight banks are divided into four bank groups (GPA, GPB, GPC and GPD) by bank addresses BA0 to BA2. Also, in the capacity of 1G and the capacity of 2G, it can be seen that four banks of fourteen banks are divided into four bank groups (GPA, GPB, GPC, and GPD) by the bank addresses BA0 to BA3.

10 is a timing chart showing the operation of the semiconductor memory device of FIG. 1 according to an embodiment of the present invention.

The operation of the semiconductor memory device 10 of FIG. 1 will now be described in detail with reference to FIGS. 1 to 6 and 10. FIG. 10, the case where the second bank block 320 operates in the non-group mode and the first bank block 310 operates in the group mode will be mainly described. Reference numeral 510 in FIG. 10 relates to when the second bank block 320 operates in the non-group mode, reference numeral 520 refers to when the first bank block 310 operates in the group mode do. In FIG. 10, only signals for explaining the group mode and the non-group mode are shown and other signals (for example, active command precharge command) are not shown.

10, when the second mode control signal MCS2 indicates the non-group mode and the second bank block 320 operates in the non-group mode, a read command for the bank 321 at time T0 The column select signal CSL 513 for activating the bit lines belonging to the bank 321 is activated and the column select signal CSL 513 is activated for a time T1 The data DQ is read from the bank 321. [ The read command RD 512 for the bank 322 is activated at a time T2 after a certain period of time has elapsed (one cycle of the clock signal CK has passed), and thus the bit lines belonging to the bank 322 The column selection signal CSL 514 for activation is activated. Data DQ is read from bank 322 for a period of time (T3, T4) in response to the activated column select signal CSL 514. It can be seen that the period of the column selection signal CSL for reading data belonging to each bank in the non-group mode is twice the clock signal CK.

Referring again to FIG. 10, when the second mode control signal MCS2 indicates the group mode and the first bank block 310 operates in the group mode, the first bank group GPA is read at time T0 The command RDA is activated so that the column selection signals CSL1 and 521 for activating the bit lines belonging to the first bank group GPA are activated. Data DQ is read out from the first bank group GPA for a period of time (T2 to T3) in response to the activated column selection signal CSL1, 521. Next, at time T2, the read command RDB for the second bank group GPB is activated, whereby the column select signals CSL2 and 523 for activating the bit lines belonging to the second bank group GPB, Is activated. Data DQ is read out from the second bank group GPB for a period of time (T5 to T6) in response to the activated column selection signals CSL2 and 523. Next, the read command RDA for the first bank group GPA is activated again at time T4, and the column selection signals CSL1 and 522 for activating the bit lines belonging to the first bank group GPA Is activated. Data DQ is read out from the first bank group GPA for a period of time (T6 to T7) in response to the activated column selection signals CSL1 and 522. [ It can be seen that the period of the column selection signals CSL1 and CSL2 for reading data belonging to each bank group in the group mode becomes four times the clock signal CK. Therefore, the period of the column selection signal in the group mode is twice the period of the column selection signal in the non-group mode.

In addition, the command for the same bank group (the first bank group GPA in Fig. 10) can not be activated continuously (without gap), and the other bank groups (the first bank group GPA in Fig. The two bank groups (GPB)) can be activated continuously. Therefore, the period of the column selection signal CSL when the bank block 320 operates in the group mode is longer than that in the case where the period of the column selection signal CSL operates in all the non-groups. The increase in the period of the column selection signal CSL means an increase in the timing margin for the column access operation, so that the frequency limit that can occur in the operation of the non-group mode can be solved.

10, the first mode control signal MCS1 indicates a second mode of operation (thread mode), and the first bank block 310 indicates a second mode control signal MCS2 indicating a group mode And the second bank block 320 may operate when operating in the non-group mode by the second mode control signal MCS2.

11 is a block diagram illustrating a memory system in accordance with one embodiment of the present invention.

Referring to FIG. 11, the memory system 600 includes a memory controller 610 and a semiconductor memory device 700.

The memory controller 610 controls the semiconductor memory device 700 by providing the semiconductor memory device 700 with the command CMD, the address signal ADD and the clock signal CK and the inverted clock signal / CK. The semiconductor memory device 700 performs an operation under the control of the memory controller 610 and exchanges data DQ with the memory controller 610.

The semiconductor memory device 700 may include a logic circuit 710, an address portion 720, and a memory array 720. The memory array 720 includes a plurality of banks divided into a first bank block and a second bank block. The logic circuit 710 causes the first bank block and the second bank block to operate in common in the first operation mode and the first bank block and the second bank block in the second operation mode based on the command CMD and the address signal ADD, The address unit 720 can be controlled so that the second bank blocks are individually operated. The semiconductor memory device 700 of FIG. 11 can employ the memory device 10 of FIG. Accordingly, the address control unit 720 may include an address decoder, an address multiplexer, and an address unit to control operations of the first bank block and the second bank block according to the first and second mode control signals, as in FIG.

A control method of a memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

In the control method of the semiconductor memory device 10, the memory cell array 300 is divided into a first bank block 310 and a second bank block 320 each having a plurality of banks. The division of the first bank block 310 and the second bank block 320 can be performed based on the address signals A0 to A12 and BA0 to BA3. The first bank block 310 and the second bank block 320 are commonly accessed in the first operation mode based on the command and address signals A0 to A12 and BA0 to BA3. The first bank block 310 and the second bank block 320 are individually accessed in the second operation mode based on the command and address signals A0 to A12 and BA0 to BA3. The first bank block 310 and the second bank block 320 operate in the group mode or the non-group mode in common in the first operation mode. The first bank block 310 and the second bank block 320 operate separately in a group mode or a non-group mode in the second operation mode.

12 to 15 are views showing examples of a memory module according to embodiments of the present invention.

Referring to FIG. 12, the memory module 800 may be an unbuffered dual in-line memory module (UDIMM). The memory module 800 may include a plurality of semiconductor memory devices 810 and 820, each of which receives data DQ externally. Semiconductor memory devices 810 may be connected in a tree structure to first command / address transmission lines CA1 and semiconductor memory devices 820 may be connected in a tree structure to second command / address transmission lines CA2. have. The semiconductor memory devices 810 and 820 may include a memory array, an address controller, and a logic circuit, each having a plurality of banks divided into first bank blocks and second bank blocks in FIGS. 1 to 6, respectively. The semiconductor memory devices 810 receive the corresponding command and address signal through the first command / address transmission lines CA1 and the first bank block and the second bank block included in the semiconductor memory devices 810 are connected to the first The operation mode or the second operation mode. The semiconductor memory devices 820 receive the corresponding command and address signal through the second command / address transmission lines CA2 and the first bank block and the second bank block included in the semiconductor memory devices 820 are connected to the first The operation mode or the second operation mode. The semiconductor memory devices 810 and semiconductor memory devices 820 can operate in different modes since the first command / address transmission line CA1 and the second command / address transmission line CA2 are separated.

Referring to FIG. 13, the memory module 900 may be an unbuffered dual in-line memory module (UDIMM). The memory module 800 may include a plurality of semiconductor memory devices 910 each receiving data DQ externally and a module termination resistor portion 920 connected to one end of the command / address transmission line CA . The semiconductor memory devices 910 may be connected in a fly-by-daisy chain manner to the semiconductor memory devices 910 via a command / address transmission line CA. Semiconductor memory devices 910 each include a memory array having a plurality of banks divided into a first bank block and a second bank block, an address controller and a logic circuit, as shown in FIGS. 1 to 6, Or in a second mode of operation.

Referring to FIG. 14, the memory module 1000 may be a Registered Dual In-line Memory Module (RDIMM). The memory module 1000 is connected to the plurality of semiconductor memory devices 1020 and 1030 and the command / address transmission lines CA which receive data DQ externally and is connected to the semiconductor memory devices 1020 and 1030, A command / address register 1010 for providing command / address signals to the command / address transmission lines CA and module termination resistors 1040 and 1050 connected to both ends of the command / address transmission lines CA. The command / address register 1710 may be daisy-chained with the semiconductor memory devices 1020 and 1030. Semiconductor memory devices 1020 and 1030 each include a memory array having a plurality of banks divided into a first bank block and a second bank block as shown in FIGS. 1 to 6, an address controller, and a logic circuit, And may operate in the first operation mode or the second operation mode based on the address signal.

Referring to FIG. 15, the memory module 1100 may be a Registered Dual In-line Memory Module (RDIMM). The memory module 1100 is connected to the plurality of semiconductor memory devices 1120 and 1130 and the command / address transmission lines CA which receive data DQ from the outside and each of the semiconductor memory devices 1120 and 1130, A command / address register 1010 that provides a command / address signal to the command / address transmission lines CA and a module termination resistance portion 1140 that is connected to one end of the command / address transmission lines CA. The command / address register 1720 may be connected to the semiconductor memory devices 1120 and 1130 in a fly-by-daisy-chain manner. Semiconductor memory devices 1120 and 1130 each include a memory array having a plurality of banks divided into a first bank block and a second bank block as shown in FIGS. 1 to 6, an address controller, and a logic circuit, And may operate in the first operation mode or the second operation mode based on the address signal.

The semiconductor memory device according to the embodiments of the present invention can solve the frequency limitation problem of column access by individually grouping the bank blocks according to the operation mode, and thus can be applied to high-speed memory devices and memory systems.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. It will be understood that the invention may be modified and varied without departing from the scope of the invention.

Claims (10)

A memory array having a plurality of banks divided into a first bank block and a second bank block; And
An address control unit for accessing the memory array; And
The first bank block and the second bank block are operated in common in the first operation mode and the first bank block and the second bank block are operated separately in the second operation mode based on the command and the address signal And a logic circuit for controlling the address control section,
The logic circuit
A command decoder for decoding the command and providing a mode register set (MRS) command; And
And a mode register for generating a first mode control signal and a second mode control signal for controlling the address control unit in response to the MRS command and the address signal. 2. The integrated circuit of claim 1,
And in the first operation mode, the first bank block and the second bank block receive the same internal address signal decoded from the address signal, and control the address control unit to perform an operation indicated by the command Semiconductor memory device. 2. The integrated circuit of claim 1,
In the second operation mode, the first bank block and the second bank block receive respective first and second internal address signals decoded from the address signal and control the address control section to perform an operation indicated by the command And the semiconductor memory device. The method according to claim 1, wherein, in the first operation mode,
Wherein the first bank block and the second bank block are divided into at least two bank groups in response to the command and the address signal and are accessible in each group unit and in a non-group mode accessible in each bank unit And operates in the same one mode. 5. The method of claim 4,
Wherein when the first bank block and the second bank block operate in the group mode, consecutive commands for the banks included in the same group are activated with a temporal gap. 5. The method of claim 4,
Wherein when the first bank block and the second bank block operate in the group mode, consecutive commands for the banks included in different groups are activated in a gapless manner. delete The method of claim 1, wherein the first mode control signal specifies an operation mode of the first bank block and the second bank block, and the second mode control signal specifies an operation mode of the first bank block and the second bank block And the group mode is designated. The method according to claim 1,
Wherein the first column access time when at least one bank block of the first bank block and the second bank block operates in a group mode accessible in a group unit including at least two banks, Wherein at least one bank block of the second bank block is at least twice as large as the second column access time when operating in a non-group mode accessible in each bank unit. Dividing a memory cell array into a first bank block and a second bank block each having a plurality of banks;
Accessing the first bank block and the second bank block in common in a first operation mode based on a command and an address signal; And
And separately accessing the first bank block and the second bank block in a second operation mode based on the command and the address signal,
Wherein the first column access time when at least one bank block of the first bank block and the second bank block operates in a group mode accessible in a group unit including at least two banks, Wherein at least one bank block of the second bank block is at least twice as large as the second column access time when operating in a non-group mode accessible in each bank unit.

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