KR101768064B1 - Low drop-out regulator using an adaptively controlled negative capacitance circuit for improved psrr - Google Patents

Abstract

The LDO regulator includes a pass transistor for regulating an input voltage and outputting an output voltage, a feedback circuit for receiving a feedback signal corresponding to the output voltage and a reference voltage, a first node connected to a gate electrode of the pass transistor, An error amplifier for outputting a first control signal for controlling the pass transistor, and a compensation circuit for providing a negative capacitance to the first node.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an LDO regulator,

An embodiment according to the inventive concept relates to an LDO regulator, and more particularly to an LDO regulator having an improved power supply rejection ratio (PSRR).

A voltage regulator is used to supply stable power to an electronic device such as a display device. Voltage regulators are classified as linear regulators and switching regulators.

DC-DC converter (DC-DC converter) is a kind of switching regulator. DC-DC converters have high conversion efficiency. However, the output voltage of the dc-to-dc converter contains more noise than the output voltage of the linear regulator.

A low-dropout (LDO) regulator is a type of linear regulator. LDO regulators have low conversion efficiency, but have a fast response time. In addition, the output voltage of the LDO regulator includes a small amount of noise compared to the output voltage of the DC-DC converter. Therefore, an LDO regulator can be used to compensate for the shortcomings of the DC-DC converter. In particular, an LDO regulator may be used to power a noise sensitive device or a device that must be driven at high performance.

The supply power noise rejection rate (PSRR) is the ratio of the input voltage noise to the output voltage noise. The PSRR is used as an indicator of the degree to which the input voltage noise is effectively blocked by a voltage regulator in a certain frequency band and is stably supplied with voltage. When the input voltage of the voltage regulator includes noise, the output voltage of the voltage regulator does not maintain a constant value due to noise. Particularly, in a high frequency band of several hundred kHz or a few MHz or more, which is larger than the gain crossover frequency of the closed loop of the linear regulator, the input voltage noise of the linear regulator is not effectively blocked. Therefore, it is difficult to form a stable output voltage in the high frequency band.

Korean Patent Publication No. 10-2015-0069869

SUMMARY OF THE INVENTION It is an object of the present invention to provide an LDO regulator having an improved power supply noise rejection ratio (PSRR) over the entire current driving range.

A LDO regulator according to an embodiment of the present invention includes a pass transistor for outputting an output voltage by regulating an input voltage, a feedback transistor for receiving a feedback signal and a reference voltage corresponding to the output voltage, An error amplifier for outputting a first control signal for controlling the pass transistor to a node, and a compensation circuit for providing a negative capacitance to the first node.

The LDO regulator according to the embodiment of the present invention has an effect of improving the supply power noise cancellation rate in the entire current driving range by using the compensation circuit that provides the negative capacitance.

In addition, the LDO regulator according to the embodiment of the present invention does not use a high-capacity load capacitor, thereby reducing the size of the regulator.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more fully understand the drawings recited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a circuit diagram of a conventional LDO regulator.
Fig. 2 shows a small-signal equivalent model of the LDO regulator shown in Fig.
3 is a circuit diagram of an LDO regulator according to an embodiment of the present invention.
Fig. 4 shows a small-signal equivalent model of the LDO regulator shown in Fig.
5 is an exemplary functional block diagram of the compensation circuit shown in FIG.
Fig. 6 shows the negative capacitance circuit shown in Fig.
7 is an exemplary circuit diagram of the current sensor shown in FIG.
FIG. 8 shows an embodiment of the compensation capacitor shown in FIG.
FIG. 9 shows an embodiment of the second resistor shown in FIG.

It is to be understood that the specific structural or functional description of embodiments of the present invention disclosed herein is for illustrative purposes only and is not intended to limit the scope of the inventive concept But may be embodied in many different forms and is not limited to the embodiments set forth herein.

The embodiments according to the concept of the present invention can make various changes and can take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example, without departing from the scope of the right according to the concept of the present invention, the first element may be referred to as a second element, The component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "having" and the like are used to specify that there are features, numbers, steps, operations, elements, parts or combinations thereof described herein, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings attached hereto.

1 is a circuit diagram of a conventional LDO regulator.

Referring to FIG. 1, the LDO regulator 10 regulates an input voltage V _dd and supplies a regulated output voltage V _OUT to a load (not shown). The LDO regulator 10 may include a pass transistor M _p , an error amplifier 12, a feedback circuit 14, and a load capacitor C _L.

Pass transistor M _p may include a first electrode (e.g., a source electrode) for receiving an input voltage V _dd and a second electrode (e.g., a drain electrode) connected to a second node N ₂ . The output voltage V _OUT may be output through the second node N ₂ . The pass transistor M _p may receive the control signal CTRL for adjusting the input voltage V _dd and outputting the output voltage V _OUT . That is, the voltage level of the output voltage V _OUT may correspond to the magnitude of the control signal CTRL. The pass transistor M _p may be implemented as a p-type transistor such as a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET).

The feedback circuit 14 includes a second feedback voltage corresponding to the node (N ₂₎ and comprising a first resistance (R ₁₎ and a second resistor (R ₂₎ connected in series between ground and the output voltage (V _OUT) (V _FB ). The feedback voltage V _FB may be the voltage at which the output voltage V _OUT is divided by the ratio of the first resistor R ₁ and the second resistor R ₂ . The feedback circuit 14 may output the feedback voltage V _FB to the error amplifier 12. [

The error amplifier 12 receives the reference voltage V _REF and the feedback voltage V _FB through the inverting terminal (-) and the non-inverting terminal (+), respectively and outputs the reference voltage V _REF and the feedback voltage V _FB ) Can be compared. The error amplifier 12 can provide the comparison signal to the first node N ₁ connected to the gate electrode of the pass transistor M _p , according to the comparison result. The comparison signal may be a control signal CTRL for controlling the operation of the pass transistor M _p .

The comparison signal may include information about a change in the output voltage (V _OUT ) of the LDO regulator (10). That is, the feedback voltage V _FB changes as the output voltage V _OUT changes, and the error amplifier 12 generates the comparison signal in accordance with the change of the feedback voltage V _FB . For example, when the feedback voltage V _FB is less than the reference voltage V _REF , the comparison signal of the error amplifier 12 controls the pass transistor M _p so that the voltage level of the output voltage V _OUT is increased . When the feedback voltage V _FB is greater than the reference voltage V _REF , the comparison signal can control the pass transistor M _p so that the voltage level of the output voltage V _OUT is reduced. Thus, the pass transistor M _p can change the voltage level of the output voltage V _{OUT in} order to stabilize the output voltage V _OUT in response to the comparison signal acting as the control signal CTRL. As such, the LDO regulator 10 generally maintains a stable output by using a feedback signal. However, in the case where the input voltage (V _dd) comprising the noise, the pass transistor (M _p), the feedback circuit 14 and the error path transistor (M _p) according to a signal flow in the loop formed by the amplifier 12 The control signal CTRL applied to the control signal CTR also includes noise. As a result, the control signal CTRL can not efficiently control the pass transistor M _p .

Fig. 2 shows a small-signal equivalent model of the LDO regulator shown in Fig.

Referring to FIG. 2, a first parasitic capacitor C _p1 may be formed in association with a first node N ₁ connected to the gate electrode of the pass transistor M _p . The first parasitic capacitor C _p1 may be formed based on the layout of the error amplifier 12 located adjacent to the first node N ₁ . The pass transistor gate electrode and the source electrode, the gate between the (M _p) - may be formed of the source capacitor (C _gs), the pass transistor (M _p) to the gate between the gate electrode and the drain electrode of the to-drain capacitor (C _gd) Can be formed. And an effective load capacitor (which describes the first parasitic capacitor C _p2 and the first voltage control current source VCCS ₁ , the second voltage control current source VCCS ₂ , the resistive load R _LT , and the load capacitor C _L ) C _LT may be connected to the second node N ₂ . The effective load capacitor C _LT can be expressed by the sum of the load capacitor C _L and the second parasitic capacitor C _p2 . A second parasitic capacitor C _p2 may be formed in association with the second node N ₂ . For example, the second parasitic capacitor C _p2 may be associated with the layout of the load device.

The first node voltage V _N1 which is the voltage of the first node N ₁ may be generated by the input voltage V _dd and may be independent of the comparison signal output from the error amplifier 12. If the input voltage (V _dd) comprising the noise, the input voltage (V _dd), so can include a frequency component, the first node voltage (V _N1) is based on the small-signal equivalent circuit shown in Figure 2 below, Can be expressed as Equation (1).

In Equation (1), "s" means a Laplace variable, and "R _g " means a lump resistance connected to the first node N ₁ . According to Equation (1), it can be seen that the first node voltage V _N1 is proportional to the input voltage V _dd . When noise is included in the input voltage V _dd , the voltage of the first node voltage V _N1 due to the first parasitic capacitor C _p1 and the gate-drain capacitor C _gd , which are the components of the denominator in Equation 1, The degree of change may be smaller than the degree of change of the input voltage (V _dd ).

The gate-source voltage V _gs capable of driving the pass transistor M _p has a voltage applied to the source electrode, that is, a first node voltage V _dd , which is the voltage of the first node N ₁ , V _N1 ). &_Lt; / RTI > Therefore, the gate-source voltage V _gs may change when the input voltage V _dd and the first node voltage V _N1 change to different degrees from each other. Thus, even when the comparison signal of the error amplifier 12 is constant, the first node voltage V _N1 changes to a different degree with respect to the input voltage V _dd , so that the control signal CTRL changes the path transistor M _p It does not control efficiently. Therefore, the PSRR characteristic of the LDO regulator 10 is degraded. The PSRR characteristic of the LDO voltage regulator 10 can be further degraded to output an unstable output voltage V _OUT when the high frequency component is included in the input voltage V _dd .

Referring again to FIG. 1, the LDO regulator 10 may include a high capacity load capacitor C _L connected to the second node N ₂ to stabilize the output voltage V _OUT . A high capacitance load capacitor C _L may be used to counter the effects of relatively high output impedance. However, the large-capacity, large-capacity load capacitor C _L is a stumbling block in realizing a compact LDO regulator.

FIG. 3 is a circuit diagram of an LDO regulator according to an embodiment of the present invention, and FIG. 4 shows a small signal equivalent model of the LDO regulator shown in FIG.

Referring to FIGS. 3 and 4, the LDO regulator 20 includes a compensation circuit 200. However, the LDO regulator 20 may not include a high capacity load capacitor C _L , unlike the LDO regulator 10 shown in FIG. In the description of the LDO regulator 20, the same reference numerals are used for the same configurations as those of the LDO regulator 10 shown in FIG. 1 in the configuration of the LDO regulator 20 to avoid redundant description, Are omitted.

The compensation circuit 200 can sense the load current flowing in the load (not shown) and generate a negative capacitance corresponding to the sensed load current. The equivalent capacitance of the compensation circuit 200 may have a negative value at the first node N ₁ . The magnitude of the equivalent capacitor C _eq of FIG. 4 is the sum of the parasitic capacitance C _gd between the gate electrode and the drain electrode of the pass transistor M _p and the parasitic capacitance C _gd of the first parasitic capacitance C _p1 at the node N ₁ . Sum. That is, the capacitance value of the equivalent capacitor C _eq may be - (C _p1 + C _gd ).

The equivalent capacitor C _eq may be connected in parallel with the gate-drain capacitor C _gd and the first parasitic capacitor C _p1 of the pass transistor M _p .

The first node voltage V _N1 'may be generated according to the input voltage V _dd regardless of the comparison signal of the error amplifier 12. [ The input voltage (V _dd) when to contain the noise, the input voltage (V _dd) may include a frequency component due to the noise, the first node voltage (V _N1 ') is a small-signal equivalent circuit of Figure 4 Can be expressed as Equation (2) below.

In Equation (2), the first node voltage V _N1 'changes at the same rate as the input voltage V _dd . For example, when the input voltage V _dd including the noise changes, the equivalent capacitor C _eq having a negative capacitance affects the influence of the first parasitic capacitance C _p1 and the gate-drain capacitance C _gd The first node voltage V _N1 'may vary to the same degree as the input voltage V _dd .

The gate-source voltage V _gs capable of driving the pass transistor M _p is a voltage applied to the source electrode, that is, the input voltage V _dd and the voltage of the first node N ₁ , (V _N1 '). Therefore, when the input voltage V _dd and the first node voltage V _N1 'change to the same degree, the gate-source voltage V _gs becomes constant. Therefore, the PSRR characteristic of the LDO regulator 20 can be improved.

Therefore, the LDO regulator 20 can output a stable output voltage V _OUT even when noise having a high frequency component is included in the input voltage V _dd . In addition, the LDO regulator 20 need not have a high-capacity load capacitor C _L associated with the second node N ₂ in the LDO regulator 10 shown in Fig.

5 is an exemplary functional block diagram of the compensation circuit shown in FIG.

Referring to FIG. 5, the compensation circuit 200 includes a control unit 210 and a negative capacitance circuit 230.

The controller 210 may sense a load current and output a second control signal _Vcont corresponding to the sensed load current. The controller 210 may be implemented with a current sensor 211, an analog-to-digital converter 213, and a mapper 215.

The current sensor 211 senses the load current and can output a sense signal (V _sns ) corresponding to the sensed load current. The analog-to-digital converter 213 receives the sense signal V _sns from the current sensor 211 and generates an n-bit digital signal V _ADC (where n is a natural number equal to or greater than 1) corresponding to the received sense signal V _sns Can be output. The mapper 215 may receive the digital signal V _ADC from the analog digital converter 213 and output a second control signal V _cont corresponding to the received digital signal V _ADC . That is, the mapper 215 may output the mapping value corresponding to the received digital signal V _ADC as the second control signal V _cont . The second control signal _Vcont may be implemented as an n-bit digital signal. The mapper 215 may be implemented as a ROM (Read Only Memory), a register, or the like.

The negative capacitance circuit 230 receives the second control signal _Vcont outputted from the mapper 215 of the control unit 210 and generates a negative capacitance corresponding to the second control signal _Vcont .

Fig. 6 shows the negative capacitance circuit shown in Fig.

Referring to FIG. 6, the negative capacitance circuit 230 includes a non-inverted amplifier 231, a source folower circuit 233, and a compensation capacitor C _M.

The non-inverting amplifier 231 may include a first resistor R _f and a second resistor R _var connected in series between the output terminal of the operational amplifier 235 and the operational amplifier 235 and the ground. The first control signal CTRL corresponding to the comparison signal of the error amplifier 12 may be applied to the non-inverting terminal (+) of the operational amplifier 235 and the output signal of the operational amplifier 235 may be fed back to the operational amplifier (-) of the inverters 235 and 235, respectively. The gain of the non-inverting amplifier 231 can be expressed as (1 + R _f / R _var ).

The comparison signal output from the error amplifier 12 may be input to the non-inverting terminal (+) of the operational amplifier 235. [ However, since the comparison signal has a relatively high voltage level as an input signal to the operational amplifier 235, the operational amplifier 235 may fail to perform a normal operation. Therefore, the negative capacitance circuit 230 may include a source follower circuit 233 capable of lowering the voltage level of the comparison signal of the error amplifier 12. [ A source follower circuit 233 may include an n-type transistor, such as a nMOSFET (M _s). Transistor (M _s) is a gate electrode for receiving the comparison output from the second terminal, and error amplifier 12 connected to the first terminal, the current sinking circuit 237 which receives an input voltage (V _dd) signal can do. A source follower circuit 233 can be by the threshold voltage of the transistor (M _s) to lower the voltage level of the comparison signal.

The compensation capacitor C _M may be connected in parallel with the non-inverting amplifier 231. Accordingly, one terminal of the compensation capacitor (C _M) is connected to the output terminal of the non-inverting amplifier 231, the other terminal of the compensation capacitor (C _M) may be connected to the gate electrode of the transistor (M _s). According to the embodiment, the other terminal of the compensation capacitor C _M may be connected to the non-inverting terminal (+) of the operational amplifier 235.

When the compensation capacitor C _M is connected in parallel with the non-inverting amplifier 231, the equivalent capacitance C _eq at the time of looking at the negative capacitance circuit 230, that is, the capacitance at the first node N ₁ to the negative capacitance circuit 230 equivalent capacitance (C _eq) of) can be expressed as shown in equation 3 below.

In Equation (3), "A _CL " means a gain of the non-inverting amplifier 231. In Equation (3), the equivalent capacitance C _eq is determined according to the values of the compensation capacitor C _M , the first resistor R _f , and the second resistor R _var . Therefore, the present invention discloses a method for disregarding the equivalent passive capacitance (C _eq ) by varying the values of the compensation capacitor (C _M ), the first resistor (R _f ) and the second resistor (R _var ).

A method of implementing the compensation capacitor C _M with a variable capacitor having a capacitance corresponding to the second control signal _Vcont will be described with reference to FIG. A method of implementing the first resistor R _f or the second resistor R _var as a variable resistor having a resistance value corresponding to the second control signal _Vcont will be described with reference to FIG.

7 is an exemplary circuit diagram of the current sensor shown in FIG.

The current sensor shown in FIG. 7 is an example of a current sensor used in the related art, and a detailed description thereof will be omitted. Further, the scope of right of the present invention is not limited to the structure and operation of the current sensor shown in FIG.

Since the first to fourth transistors M ₁ to M ₄ included in the current sensor 211 of FIG. 7 operate as a common gate amplifier, the drain voltage of the transistor M _s is lower than the drain Is equal to the drain voltage of transistor M _p . The transistor (M _s) and a transistor (M ₅₎ are of the same size, the transistors (M ₁₎ and a transistor (M ₆₎ is equal to the load current (I _LOAD) of the size of the polymer satisfies the above equation (4) below.

Further, the current (I _sns ) is converted into the sensing voltage (V _sns ) while flowing at R _sns . The current sensor 211 may output the sensing voltage V _sns as a sensing signal.

FIG. 8 shows an embodiment of the compensation capacitor shown in FIG.

Referring to FIG. 8, the compensation capacitor C _M includes a plurality of capacitors each of which is connected in series with the switching element. That is, the first capacitor unit includes a first capacitor C ₁ and a first switching unit SW ₁ connected in series, and the second capacitor unit includes a second capacitor C ₂ and a second capacitor C ₂ connected in series. a switching element (SW _2). Similarly, the k-th capacitor unit includes a k-th capacitor C _k and a k-th switching unit SW _k connected in series. When the first capacitor unit to the k-th capacitor unit are connected in parallel, a compensation capacitor C _M implemented as a variable capacitor can be implemented. The second control signal _Vcont output from the control unit 210 may control the capacitance of the compensation capacitor C _M by controlling the operation of each of the plurality of switching elements.

FIG. 9 shows an embodiment of the second resistor shown in FIG.

Referring to FIG. 9, the second resistor R _var includes a plurality of resistors and a plurality of switching elements. The second control signal V _cont output from the controller 210 may control the resistance of the second resistor R _var by controlling the operation of each of the plurality of switching elements. The second resistor R _var shown in FIG. 9 is only one embodiment, and the second resistor R _var of the present invention can be implemented in various forms.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10: LDO regulator
12: Error amplifier
14: Feedback circuit
20: LDO regulator
200: compensation circuit
210:
211: Current sensor
213: Analog to Digital Converters
215: Mapper
230: Negative capacitance circuit

Claims (10)

A pass transistor for regulating an input voltage to output an output voltage;
An error amplifier receiving a feedback signal corresponding to the output voltage and a reference voltage and outputting a first control signal for controlling the pass transistor to a first node connected to a gate electrode of the pass transistor; And
And a compensation circuit for providing negative capacitance to the first node. The method according to claim 1,
Wherein the LDO regulator further comprises a feedback circuit that generates the feedback signal based on the output voltage and outputs the feedback signal to the error amplifier. The method according to claim 1,
Wherein the pass transistor is a p-type transistor including a first electrode for receiving the input voltage, a second electrode for outputting the output voltage, and the gate electrode for receiving the first control signal, LDO regulator. The method according to claim 1,
Wherein the error amplifier includes an inverting terminal for receiving the reference voltage and a noninverting terminal for receiving the feedback signal and for outputting the first control signal corresponding to a result of comparison between the reference voltage and the feedback signal, . The method according to claim 1,
Wherein a magnitude of the negative capacitance provided by the compensation circuit is a sum of a magnitude of a gate-drain capacitor formed between a gate electrode of the pass transistor and a drain electrode of the pass transistor and a size of a first parasitic capacitor associated with the first node, The same, LDO regulator. The method according to claim 1,
Wherein the compensation circuit comprises:
A control unit for detecting a load current which is a current flowing in the load and generating a second control signal based on the detected load current; And
And a negative capacitance circuit for providing a negative capacitance in response to the second control signal output from the control section. The method according to claim 6,
Wherein,
A current sensor for sensing the load current and outputting a sensing signal corresponding to the sensed load current;
An analog digital converter for outputting a digital signal corresponding to the sensing signal; And
And a mapper for receiving the digital signal and outputting a mapping value corresponding to the digital signal as the second control signal. The method according to claim 6,
Wherein the negative capacitance circuit comprises:
A non-inverting amplifier including an operational amplifier, a first resistor, and a second resistor connected in series with the first resistor between an output terminal of the operational amplifier and ground; And
And a compensation capacitor connected between the first node and an output of the non-inverting amplifier. 9. The method of claim 8,
Wherein the compensation capacitor is a variable capacitor having a capacitance corresponding to the second control signal. 10. The method of claim 9,
Wherein the first resistor or the second resistor is a variable resistor having a resistance value corresponding to the second control signal.

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