[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

KR101731862B1 - Optoelectronic semiconductor device and method for manufacturing same - Google Patents

Optoelectronic semiconductor device and method for manufacturing same Download PDF

Info

Publication number
KR101731862B1
KR101731862B1 KR1020150089435A KR20150089435A KR101731862B1 KR 101731862 B1 KR101731862 B1 KR 101731862B1 KR 1020150089435 A KR1020150089435 A KR 1020150089435A KR 20150089435 A KR20150089435 A KR 20150089435A KR 101731862 B1 KR101731862 B1 KR 101731862B1
Authority
KR
South Korea
Prior art keywords
layer
semiconductor
graphene
thermally conductive
forming
Prior art date
Application number
KR1020150089435A
Other languages
Korean (ko)
Other versions
KR20160016586A (en
Inventor
서은경
서태훈
박아현
Original Assignee
전북대학교산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 전북대학교산학협력단 filed Critical 전북대학교산학협력단
Publication of KR20160016586A publication Critical patent/KR20160016586A/en
Application granted granted Critical
Publication of KR101731862B1 publication Critical patent/KR101731862B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02606—Nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Led Devices (AREA)

Abstract

In the present invention, by including the graphene layer and the thermally conductive layer including the carbon nanotube layer formed on the graphene layer on the back surface of the semiconductor optoelectronic structure, it is possible to improve the lattice constant and the thermal expansion coefficient There is provided a semiconductor optoelectronic device capable of exhibiting improved device efficiency with a reduced penetration dislocation and strain and improved heat dispersion.

Description

[0001] OPTOELECTRONIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME [0002]

The present invention reduces the threading dislocation and strain caused by the difference in lattice constant and thermal expansion coefficient between the substrate and the semiconductor optoelectronic structure and improves heat dissipation, To an optoelectronic device and a method of manufacturing the same.

Semiconductor optoelectronic devices that can emit light of various colors by constituting a light emitting source by recombination of electrons and holes in the pn junction of semiconductors can have a long life, can be reduced in size and weight, have excellent light directivity, Resistant to impact and vibration, does not require preheating time and complicated driving, can be packaged in various forms, and can be applied to various applications.

As a result, research and development on semiconductor light emitting devices have been actively conducted. Among them, gallium (Ga), aluminum (Al), indium (In), and the like having excellent thermal stability and having a direct transition type energy band structure A nitride semiconductor optoelectronic device using a nitride containing a Group 3 element of the nitride semiconductor has recently been actively researched and developed.

The nitride semiconductor optoelectronic device 100 typically comprises a substrate 1 such as sapphire (Al 2 O 3 ) or silicon carbide (SiC), and an n-type nitride-based semiconductor Type semiconductor layer 2c in which a p-type semiconductor layer 2c, a p-type semiconductor layer 2c and a p-type semiconductor layer 2c are sequentially stacked, And an n-type electrode 4 is provided on the exposed top surface of the n-type semiconductor layer 2a on which the top surface is partially exposed by etching during the manufacturing process.

The nitride semiconductor opto-electronic device 100 having the above structure is formed by forming a semiconductor optoelectronic structure 2 having a laminated structure of a nitride-based semiconductor including GaN on the substrate 1 by MOCVD, HVPE, do. However, due to the difference in lattice constant and thermal expansion coefficient between the substrate 1 and the nitride-based semiconductor thin film in the semiconductor optoelectronic structure 2, many threading dislocations occur in the nitride-based semiconductor thin film, There is a problem that the photoelectric efficiency is significantly lowered. Also, the low thermal conductivity of a substrate including sapphire or the like makes it difficult to drive a device at a high current, resulting in a large amount of heat loss.

In order to solve such a problem, a method of epitaxial lateral overgrowth (hereinafter referred to as " epitaxial lateral overgrowth ") is performed using metal clusters such as Pt, Au, Ag, or SiO 2 nano rods between the back surface of the nitride- There have been proposed methods for decreasing the threading dislocation by ELOG or forming graphene on the substrate or forming a patterned graphene layer to reduce heat loss, but the effect is not satisfactory enough.

Specifically, in the case of a method of forming a patterned graphene layer, there is a fear of heat loss due to a decrease in graphene area, and there is a problem that separation is difficult due to strong bonding between the substrate and the nitride-based semiconductor thin film layer .

Korean Patent Publication No. 2000-0074447 (published on December 15, 2000) Korean Patent Laid-Open Publication No. 2013-0030840 (published on March 28, 2013)

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor optoelectronic device and a method of manufacturing the semiconductor optoelectronic device exhibiting improved device efficiency by reducing the threading dislocations and strains generated internally in the semiconductor layer in the semiconductor optoelectronic structure and improving the heat dispersion.

A semiconductor optoelectronic device according to an embodiment of the present invention includes a thermally conductive layer and a semiconductor optoelectronic structure disposed on the thermally conductive layer, wherein the thermally conductive layer includes a graphene layer, And a carbon nanotube layer formed between the optoelectronic structures and including a carbon nanotube (CNT).

In the semiconductor optoelectronic device, the surface energy at the interface between the graphene layer and the carbon nanotube layer in the graphene layer and the surface energy at the interface between the graphene layer and the carbon nanotube layer, There is a difference in surface energy.

In the heat conduction layer, the carbon nanotubes may have an average diameter of 500 nm or less and a length of 10 to 20 mu m.

In the semiconductor optoelectronic device, the semiconductor optoelectronic structure may be a multilayer structure in which a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer are sequentially laminated.

In the semiconductor optoelectronic structure, the first conductivity type semiconductor layer may be an n-type semiconductor layer, and the second conductivity type semiconductor layer may be a p-type semiconductor layer.

The semiconductor optoelectronic structure may further include a nitride semiconductor layer located on a rear surface side of the first conductivity type semiconductor layer.

The nitride semiconductor layer may include a nitride semiconductor grown in a horizontal direction.

In addition, the semiconductor optoelectronic structure may further include a reflective layer or a transparent electrode positioned on the second conductive type semiconductor layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor optoelectronic device, comprising: forming a graphene layer including graphene on a substrate and a carbon nanotube layer including carbon nanotubes sequentially on the graphene layer to form a thermally conductive layer ; And forming a semiconductor optoelectronic structure on the thermally conductive layer.

In the method for manufacturing a semiconductor optoelectronic device, the thermally conductive layer forming step may include forming a graphene layer on a substrate using a Scotch-tape method, a transfer method, or a spin coating method, And then forming a tube layer.

The method for manufacturing a semiconductor optoelectronic device may further include removing a substrate located on a rear surface of the thermally conductive layer after the step of forming the semiconductor optoelectronic structure.

Other specific embodiments of various aspects of the present invention are included in the detailed description below.

In the semiconductor optoelectronic device according to the present invention, due to the difference in lattice constant and thermal expansion coefficient between the substrate and the semiconductor optoelectronic structure, the threading dislocations and strains generated internally in the semiconductor layer of the semiconductor optoelectronic structure contacting the substrate are reduced, Lt; RTI ID = 0.0 > photovoltaic < / RTI > efficiency.

1 is a cross-sectional structural view schematically showing a conventional semiconductor optoelectronic device.
2 is a schematic cross-sectional view of a semiconductor opto-electronic device according to an embodiment of the present invention.
FIG. 3A shows a thermally conductive layer (a) including CNT-graphene (CGH) formed on a substrate in the fabrication of the LED according to Example 1-1, FIG. 3B shows the initial GaN layer grown on the thermally- 3C and 3D are photographs of the surface and cross section of the GaN layer observed by a scanning electron microscope (SEM) after the growth process for 2 hours.
4 is a photograph of the surface of the GaN layer formed during the fabrication of the light emitting diode according to Comparative Example 1-2 with a scanning electron microscope (SEM).
5 is a PL spectrum of a GaN layer in a light emitting diode manufactured according to Example 1-1 and Comparative Example 1-1.
6 is a schematic view showing a process of manufacturing a semiconductor optoelectronic device in the following production example.
FIGS. 7A to 7C are Raman mapping images of a GaN buffer layer formed on the thermally conductive layer in the semiconductor optoelectronic device fabricated in Example 2-1, and FIG. 7D is Raman spectra of regions A and B in FIG.
FIG. 8A is an AFM image of the GaN epilayer produced in Example 2-1, and FIG. 8B is an AFM image of the GaN epilayer produced in Comparative Example 2-1.
9A and 9B are XRD omega rocking curves for the (a) symmetry plane (002) and (b) asymmetry plane (102) reflections of the GaN thin films produced in Example 2-1 and Comparative Example 2-1. 9A and 9B, the red graph is for the GaN thin film produced in Example 2-1, and the black graph is for the GaN thin film prepared in Comparative Example 2-1.
10A and 10B are (a) Raman spectra and (b) PL spectra of the GaN thin films prepared in Example 2-1 and Comparative Example 2-1.
FIGS. 11A and 11B are PL spectra measured at 10 K and 300 K of the semiconductor optoelectronic device manufactured in Comparative Example 2-1 and Example 2-1. FIG.
12A to 12C are IV characteristics (a), LI curves, and (c) EL spectra of the semiconductor optoelectronic device manufactured in Example 2-1 and Comparative Example 2-1. 12A to 12C, the red graph is for the semiconductor optoelectronic device manufactured in Example 2-1, and the black graph is for the semiconductor optoelectronic device manufactured in Comparative Example 2-1.

The present invention is capable of various modifications and various embodiments and is intended to illustrate and describe the specific embodiments in detail. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present invention, terms such as "comprises" or "having" are used to designate the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In this specification, "nano" means a dimension of less than about 1 μm, preferably not more than 100 nm.

The present invention relates to a method of manufacturing a semiconductor optoelectronic device by interposing a thermally conductive layer including a carbon nanotube having good thermal conductivity and graphene in a two-layer structure so as to form a step difference in surface energy between a substrate and a semiconductor optoelectronic structure To reduce the threading dislocations and strains generated between the substrate and the semiconductor optoelectronic structure, and to improve the photoelectric efficiency of the device through effective heat dissipation.

That is, the semiconductor opto-electronic device according to an embodiment of the present invention includes:

A heat conduction layer, and

And a semiconductor optoelectronic structure positioned above the thermally conductive layer,

The thermally conductive layer includes a graphene layer including graphene, and a carbon nanotube layer formed between the graphene layer and the semiconductor optoelectronic structure and including carbon nanotubes.

The thermally conductive layer may be formed by forming a graphene layer on a substrate by a transfer method or a spin coating method in which grafting grown by a Scotch-tape method or a chemical vapor deposition method is transferred using polymethylmethacrylate (PMMA) , A method of forming a carbon nanotube layer on the graphene layer, and a two-layer structure of a graphene layer and a carbon nanotube layer formed thereon. This structural feature creates a step according to the difference in surface energy within the thermally conductive layer. In detail, when the thermally conductive layer is formed, the carbon nanotubes are dispersed and positioned on the graphene layer so that graphene in the graphene layer and carbon nanotubes in the carbon nanotube layer are in contact with each other at the contact interface between the graphene layer and the carbon nanotube layer And a portion where the graphene and the carbon nanotube are not in contact with each other are formed. The surface energy at the interface between the graphene layer and the carbon nanotube in the graphene layer and the surface energy at the portion where the graphene does not contact with the carbon nanotube are different from each other , The surface energy at the interface where the graphene and the carbon nanotube are in contact with each other is higher than the surface energy at the interface. In the subsequent formation of the GaN thin film layer, GaN growth occurs at a portion having a high surface energy as described above.

Generally, when a GaN layer is formed directly on a graphene layer, it is difficult to form a substantially clean, two-dimensional GaN (2-dimentional GaN) layer. However, by forming the CNT layer on the graphene layer as described above, a step corresponding to the surface energy difference at the interface between the graphene layer and the CNT layer is formed, and the GaN is grown from the portion having a high surface energy, And it is also possible to form a high-quality GaN layer using a horizontal growth technique. Therefore, the heat conduction layer is applicable not only to LED but also to HEMT or LD using GaN material.

In addition, since the carbon nanotube and graphene are mixed in the two-layer structure as described above, the thermal conductivity of the carbon nanotube and graphene is more excellent than that of the carbon nanotube and graphene in the heat conduction layer. Photons) can be significantly reflected in the external quantum efficiency.

2 is a schematic cross-sectional view of a semiconductor opto-electronic device according to an embodiment of the present invention. FIG. 2 is an illustration for illustrating the present invention, but the present invention is not limited thereto.

2, a semiconductor opto-electronic device 200 according to an embodiment of the present invention includes a thermally conductive layer 20 and a semiconductor opto-electronic structure 30 disposed on the thermally conductive layer, Optionally, the substrate 10 may be further positioned on the backside of the thermally conductive layer.

In the semiconductor opto-electronic device 200, the substrate 10 can be used without any particular limitation as long as it is usually used as a semiconductor substrate. More specifically, the substrate 10 may be a substrate for growing a semiconductor monocrystal, and more specifically, may be a sapphire substrate, Al 2 O 3 , AlN, BN, GaAs, GaN, LiAlO 2 , LiGaO 2 , MgAl 2 O 4 , MgO, silicon (Si), silicon carbide (SiC), zinc oxide (ZnO), glass and the like. For example, when the substrate 10 is formed of sapphire, the sapphire has a Hexa-Rhombo R3c symmetry, and has a concavo-convex constant of 13.001 angstroms in the c-axis direction and 4.765 angstroms in the a- And may have a C (0001) plane, an A (1120) plane, an R (1102) plane or the like as an orientation plane of the sapphire. In the case of the C-plane of the sapphire substrate layer, the nitride thin film can be easily grown and stable at high temperature. The substrate 10 may be removed as needed.

In the semiconductor opto-electronic device 200, the thermally conductive layer 20 is formed on the substrate 10, and includes a graphene layer including graphene, and a semiconductor layer formed on the graphene layer between the graphene layer and the semiconductor optoelectronic structure. And includes a carbon nanotube layer including carbon nanotubes, thereby reducing the threading potential generated between the substrate 10 and the semiconductor optoelectronic structure 30 and improving the heat dispersion.

Specifically, in the graphene layer of the thermally conductive layer 20, graphene is a material having a hexagonal planar array structure of a carbon monolithic material. Even though the thickness is very thin, the graphene has a conductivity superior to that of a metal, Excellent strength properties. The graphen acts as a mask for the horizontal growth technique to reduce the threading potential generated between the substrate and the semiconductor optoelectronic structure.

The larger the distribution area of the graphene in the heat conduction layer 20 is, the better the heat dispersion effect is, and the greater the graphene thickness, that is, the loading amount of graphene, the better the thermal conductivity.

Specifically, it is preferable that the graphene has a specific surface area of 100 to 3,000 m 2 / g. By having such a large surface area, it is possible to exhibit further improved effects on reduction of threading dislocation and heat dispersion.

The shape of the graphene is not particularly limited. Specifically, a graphene sheet, a graphene nanoribbon having a band shape by partial etching, or graphene nanomesh having a plurality of pores formed therein .

The graphene can be produced by a conventional graphene production method, and specifically includes a chemical vapor deposition method, an epitaxy synthetic method, a physical exfoliation method using scotch-tape, a graphite oxidation ultrasound A pulverization method, an organic synthesis method using tetraphenylbenzene, and the like, but the present invention is not limited thereto.

The graphene layer containing the graphene layer may be formed by directly forming graphene on the substrate by various methods such as the graphene formation method to form a graphene layer or by growing a graphene on an arbitrary substrate by chemical vapor deposition or the like, A transfer method in which transfer is performed using methyl methacrylate (PMMA), a spin coating method using graphene oxide, or the like.

The above-described graphene layer may serve as a support substrate for the semiconductor optoelectronic structure when the semiconductor optoelectronic device does not include a separate substrate.

On the other hand, the carbon nanotube layer in the heat conduction layer 20 is located on the graphene layer and includes carbon nanotubes.

The carbon nanotube serves as a heat spreader for effectively dispersing the heat generated between the substrate and the semiconductor optoelectronic structure due to its excellent thermal conductivity and serves as a nucleation site for GaN growth, GaN layer plays an important role in growth.

Specifically, the carbon nanotubes may have an average diameter (or average thickness) of about 500 nm or less, or about 20 to 200 nm, or about 40 to 50 nm, and a length of about 10 to 20 m. More specifically, it may be a nanostructure having a large aspect ratio (ratio of length to width) of 10 or more, or 100 or more, or 250 to 500 within the above-described average diameter and length. When the average diameter and the length and the aspect ratio within the above range are satisfied, it exhibits efficient and improved thermal conductivity, and the reduction of the threading dislocation and the heat dispersion effect are significant.

In the semiconductor opto-electronic device 200, the semiconductor opto-electronic device 30 converts electrical energy into light energy and emits light or converts light energy into electrical energy. It can be used without any particular limitations as long as it is commonly used in the technical field depending on the kind of the compound.

Specifically, when the semiconductor optoelectronic device is a nitrogen-based semiconductor optoelectronic device, the semiconductor optoelectronic device 30 may include a first conductivity type semiconductor layer 31, an active layer 32 disposed on the first conductivity type semiconductor layer, And a second conductive semiconductor layer 33 positioned on the active layer are sequentially stacked.

In the semiconductor optoelectronic structure 30, the first conductivity type semiconductor layer 31 may include a nitride semiconductor doped with a first conductivity type impurity.

Specifically, the nitride semiconductor may be Al x In y Ga (1-xy) N (where 0? X? 1, 0? Y ? 1 , 0? X + y? 1) GaN, AlGaN, InGaN, and the like. The first conductive impurity doped in the nitride semiconductor may be an n-type impurity, and may be specifically Si, Ge, Se, Te, or the like.

In the semiconductor optoelectronic structure 30, the active layer 32 located on the first conductivity type semiconductor layer is a region where electrons and holes are recombined, and a quantum well layer (not shown) and a quantum barrier layer (not shown) . When the semiconductor optoelectronic device is a light emitting device, the active layer emits light having a predetermined wavelength, and when the semiconductor optoelectronic device is a light receiving device or a photovoltaic power generating device, the active layer absorbs light having a predetermined wavelength. Therefore, the wavelength of the light emitted or absorbed by the active layer may vary depending on the type of the material constituting the active layer.

Specifically, when the semiconductor optoelectronic device is a nitrogen-based semiconductor optoelectronic device, the active layer 32 is formed of a semiconductor material such as In x Ga 1-x N (0 <x <1) so that the band gap energy can be controlled according to the indium content .

In addition, the active layer 32 may have a multi-quantum well (MQW) structure in which quantum barrier layers and quantum well layers are alternately stacked. Specifically, the active layer may be formed by repeatedly laminating InGaN and GaN, and may be formed by repeatedly laminating AlGaN and GaN.

Meanwhile, in the semiconductor optoelectronic structure 30, the second conductive semiconductor layer 33 located on the active layer 32 may include a nitride semiconductor doped with a second conductive impurity.

Specifically, the nitride semiconductor may be Al x In y Ga (1-xy) N (where 0? X? 1, 0? Y ? 1 , 0? X + y? 1) GaN, InN, AlGaN, InGaN, or the like. The second conductivity type impurity to be doped in the nitride semiconductor may be a p-type impurity, specifically, Mg, Zn, Be, or the like.

Although the first and second conductivity type semiconductor layers 31 and 33 are described as the n-type and p-type semiconductor layers, respectively, they may be p-type and n-type semiconductor layers, respectively.

The first and second conductivity type semiconductor layers 31 and 33 may be independently a single layer or may have a multilayer structure of two or more layers.

In the semiconductor optoelectronic structure 30, a nitride semiconductor layer 34 (not shown) is formed under the first conductivity type semiconductor layer 31, that is, on the surface side of the first conductivity type semiconductor layer 31 in contact with the heat conduction layer 20 ) May be further included. Specifically, the nitride semiconductor layer 34 includes a nitride semiconductor of Al x In y Ga (1-xy) N (where 0? X? 1, 0? Y ? 1 , 0? X + y? 1) And more specifically GaN, AlGaN, InGaN, or the like.

The nitride semiconductor layer 34 may be formed according to a conventional method of forming a nitride semiconductor layer such as a vapor deposition method. In the present invention, as the graphene layer 20c under the nitride semiconductor layer 34 is patterned, The nitride semiconductor forming the layer 34 grows horizontally to form a layer. As a result, the penetration voltage in the GaN thin film layer can be reduced.

A transparent electrode (not shown) is formed on the second conductivity type semiconductor layer to uniformly supply power to the second conductivity type semiconductor layer (or the p-type nitride semiconductor layer) May be formed.

In general, the p-type nitride semiconductor layer has a resistance of several ohms in a vertical direction and a resistance of several hundreds of kilohms in a horizontal direction, so that no current flows in the horizontal direction and a current flows only in the vertical direction. Therefore, when power is locally applied to the p-type nitride semiconductor layer, current does not flow through the p-type semiconductor layer as a whole, so that current can flow through the p-type semiconductor layer as a whole with excellent conductivity, It may be desirable to form a transparent electrode using a transparent conductive material so that light can be transmitted well. Specifically, the transparent conductive material may be ITO, IZO, ZnO, RuO x , TiO x , IrO x , or the like.

In addition, a reflective layer (not shown) may be further formed on the second conductivity type semiconductor layer 33 to reflect light emitted toward the p-type electrode toward the upper side.

The reflective layer may preferably include a material having a high reflectance while lowering the contact resistance with the p-type nitride semiconductor layer having a relatively large energy bandgap. More specifically, it may include Ag, Ni, Al, Ph, Pd, Ir, Ru, Mg, Zn, Pt, Au or an alloy thereof.

Meanwhile, the semiconductor opto-electronic device 200 according to the present invention having the above structure may include first and second electrodes 40 and 50 spaced apart from each other on the semiconductor optoelectronic structure. More specifically, the first electrode 40 is located apart from the active layer 32 and the second conductive type semiconductor layer 33 on the first conductive type semiconductor layer 31, which is partially exposed by etching. type electrode, and the second electrode 50 may be a p-type electrode located on the second conductivity type semiconductor layer 33.

The first and second electrodes 40 and 50 may also be used without limitation, as long as they are commonly used in the related art depending on the type of the semiconductor optoelectronic device.

More specifically, the first and second electrodes may include a conductive material such as Ti, Cr, Au, Al, Ni, Ag, Zn, etc., if the semiconductor optoelectronic device is a nitrogen-based semiconductor optoelectronic device. , Or an alloy thereof.

Each of the first and second electrodes 40 and 50 may have a single layer structure or a multi-layer structure of two or more layers, and the second electrode (or the p-type electrode) Or may be formed in a plurality of electrode patterns.

More specifically, the first electrode (or the n-type electrode) 40 is formed by sequentially depositing Ti / Al and the second electrode (or the p-type electrode) 50 is formed by sequentially depositing Ni / Lt; / RTI &gt;

The semiconductor optoelectronic device having the above structure includes sequentially forming a graphene layer including graphene on a substrate and a carbon nanotube layer including carbon nanotubes on the graphene layer to form a thermally conductive layer; And forming a semiconductor optoelectronic structure on the thermally conductive layer.

Specifically, the first step for manufacturing the semiconductor optoelectronic device is a step of forming a thermally conductive layer on the substrate.

The thermally conductive layer forming step can be manufactured by forming a graphene layer and then forming a carbon nanotube layer by various conventional graphene growth methods or graphene layer forming methods as described above. Specifically, , A step of forming a graphene layer by a transfer method or a spin coating method, and a step of forming a carbon nanotube layer by spin coating on the graphene layer.

The substrate may be the same as described above.

The method of forming the graphene layer on the substrate can be carried out by a conventional method such as a scatching method, a transfer method and a spin coating method.

Specifically, in the case of the transfer method, the graphene can be chemically vapor-deposited (CVD) on any substrate and then transferred onto the substrate of the semiconductor optoelectronic device using polymethyl methacrylate.

In the case of the spin coating method, it may be formed by dispersing graphene oxide in an organic solvent, applying the dispersion on a substrate for a semiconductor optoelectronic device, and heat-treating the resultant mixture in a temperature range in which only the organic solvent can be removed, have.

The carbon nanotube layer may be formed on the graphene layer by a conventional method. Specifically, a composition for forming a carbon nanotube layer, which is prepared by dispersing carbon nanotubes in an organic solvent, Followed by a drying process to remove the organic solvent in the composition.

The graphene and carbon nanotubes are as described above.

The second step is a step of forming a semiconductor optoelectronic structure by sequentially laminating a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer on the carbon nanotube layer of the heat conduction layer manufactured in the above step.

The first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer may be formed by a conventional method, for example, metalorganic chemical vapor deposition (MOCVD), hydride vapor the first conductive type semiconductor forming material, the active layer forming material, and the second conductive type semiconductor forming material are formed on the heat conduction layer by using a method such as a phase epitaxy (HVPE), MOCVD or molecular beam epitaxy (MBE) And then growing them sequentially. At this time, the first conductive type semiconductor forming material, the active layer forming material, and the second conductive type semiconductor forming material may be the same as described above.

When the semiconductor optoelectronic device further includes a nitride semiconductor layer between a surface of the semiconductor optoelectronic device and a surface in contact with the thermally conductive layer below the first conductivity type semiconductor layer, the manufacturing method further includes a step of forming a nitride semiconductor layer after formation of the thermal conductive layer . At this time, the method of forming the nitride semiconductor layer may be performed according to a conventional method of forming a semiconductor layer, such as deposition, and the material for forming the nitride semiconductor layer is the same as described above. In addition, the nitride semiconductor in the nitride semiconductor layer grows horizontally due to the patterned graphene layer formed at the bottom.

When the semiconductor optoelectronic device further includes a transparent electrode or a reflective layer on the second conductivity type semiconductor layer, the manufacturing method may further include a step of forming a transparent electrode or a reflective layer after the semiconductor optoelectronic structure is manufactured .

The transparent electrode and the reflective layer may be formed by a conventional method, and the material for forming a transparent electrode and the material for forming a reflective layer may be the same as those described above.

Next, the first and second electrode forming processes may be performed.

Since the first electrode is formed on the first conductive semiconductor layer exposed through the etching process after the formation of the semiconductor optoelectronic structure, the active layer and the second conductive semiconductor layer in the semiconductor optoelectronic structure are etched. If a reflective layer or a transparent electrode is additionally formed on the second conductive semiconductor layer, the reflective layer and the transparent electrode may be etched.

After the completion of the etching process, the first and second electrodes may be formed. In this case, the electrode may be formed according to an ordinary electrode forming method using the electrode forming material as described above.

The semiconductor optoelectronic device manufactured by the above manufacturing method is characterized in that a thermally conductive layer including carbon nanotubes and graphene having good thermal conductivity is sandwiched between the substrate and the semiconductor optoelectronic structure so that the threading dislocations generated between the substrate and the semiconductor optoelectronic structure It is possible to exhibit remarkably improved device efficiency by reducing the strain and improving the heat dispersion property.

Specifically, the semiconductor optoelectronic device includes an optical device including a photodiode, a laser diode, a photodetector, or a solar cell; Or a thin film transistor.

Hereinafter, embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[ Experimental Example  One]

( Example  1-1)

Graphene was grown on the amorphous substrate by the CVD method. The graphene layer formed on the amorphous substrate was transferred onto a sapphire substrate using polymethylmethacrylate (PMMA).

Next, a composition for forming a carbon nanotube layer, prepared by dispersing carbon nanotubes (average diameter: about 40 nm, length: about 10 to 20 μm) as a dispersion medium in NMP, was spin-coated on a graphene layer formed on a sapphire substrate and dried Thereby forming a carbon nanotube layer.

Next, a GaN thin film layer was formed on the heat conduction layer by MOCVD to form a GaN thin film layer. Then, a semiconductor optoelectronic structure was formed by successively growing n-GaN, MQW (Multi Quantum Well) and p-GaN on the GaN thin film layer.

Thereafter, Ti / Al was deposited on the n-GaN exposed by wet etching to separate the MQW and p-GaN to form a first electrode, and Ni / Au was deposited on the p-GaN to form a second electrode . The first and second electrodes utilized an optical lithography process and a deposition process using an electron beam evaporator. As a result, a light emitting diode was fabricated.

( Comparative Example  1-1)

A light emitting diode was fabricated in the same manner as in Example 1-1 except that the GaN thin film layer was directly formed on the sapphire substrate without performing the heat conduction layer forming step.

( Comparative Example  1-2)

A light emitting diode was fabricated in the same manner as in Example 1-1 except that the GaN thin film layer was directly formed on the graphene layer formed on the sapphire substrate without forming the carbon nanotube layer on the graphene layer.

( Test Example  1-1)

In Example 1-1, a thermal conductive layer was formed on the substrate, a GaN thin film was formed on the heat conductive layer, and a scanning electron microscope was used for 2 hours after the GaN growth process. The results are shown in Figs. 3A to 3D.

FIG. 3A shows a thermally conductive layer (a) including CNT-graphene (CGH) formed on a substrate in the fabrication of the LED according to Example 1-1, FIG. 3B shows the initial GaN layer grown on the thermally- 3C and 3D are photographs of the surface and cross section of the GaN layer observed by a scanning electron microscope (SEM) after the growth process for 2 hours.

In addition, for comparison, observation was performed using a scanning microscope after the GaN growth process was performed for 2 hours in the manufacturing process of the light emitting diode in Comparative Example 1-2. The results are shown in Fig.

As shown in FIGS. 3A to 3D, it can be seen from FIG. 3B that the CNT in the thermally conductive layer acts as a nucleation site to form a GaN thin film layer, and from FIGS. 3C and 3D, a GaN layer having a flat and clean surface is formed can confirm. On the other hand, as shown in FIG. 4, when GaN is directly grown on the graphene layer to form a thin film layer, it can be seen that the surface of the formed GaN thin film layer is not two-dimensionally flat and forms a three-dimensional layer.

( Test Example  1-2)

In the light emitting diodes manufactured according to Example 1-1 and Comparative Example 1-1, a PL spectrum was observed with respect to the GaN layer. The results are shown in Fig.

As shown in FIG. 5, the PL intensity of the GaN layer of Example 1-1 grown on the CGH increased more than twice as compared to Comparative Example 1-1 in which the GaN layer was formed on the sapphire substrate. This is because the growth of the GaN layer grown on the CNTs by the horizontal growth technique resulted in a decrease in the threading dislocation, resulting in an increase in the PL intensity.

[ Experimental Example  2]

6 is a process diagram schematically illustrating a process of manufacturing a semiconductor optoelectronic device in Example 2-1 below. Hereinafter, a semiconductor optoelectronic device was fabricated as shown in FIG.

( Example  2-1)

(Step 1: Grapina  Synthesis and transcription)

Graphene was synthesized on a Cu-foil with a thickness of approximately 35 μm using a CVD (chemical vapor deposition) method. Then, PMMA (poly methyl methacrylate) was formed on the graphene synthesized on the Cu-foil, and the transfer process was performed on the c-plane sapphire substrate. Annealing was then performed at 500 ° C for 30 min at a gas flow rate of H 2 : Ar = 90: 10 sccm to remove PMMA.

(Step 2: SWCNTs (Single Walled Carbon Nanotubes ) formation)

Arc-SWCNTs were purified by heat and acid treatment and then dispersed in sodium dodecyl sulfate water. SWCNTs were formed on a c-plane sapphire substrate by spin coating at 4000 rpm for 10 seconds.

(Step 3: GaN  layer growth)

A GaN thin film was grown on a carbon nanotube-graphene hybrid structure (CGH) formed on a sapphire substrate using metal-organic chemical vapor deposition (MOCVD). GaN buffer layer was formed at 560 ° C, 635 mbar, and 5 min, and the un-doped GaN layer was formed at 1130 ° C, 100 mbar, 2 hours, and 3 μm.

(Step 4: blue-LED epi  structure growth and device fabrication)

Si doped n-GaN layer (2 μm, 1100 ° C, 400 mbar, 60 min), InGaN quantum wells (3 nm, 720 ° C) and GaN barrier (12 nm, 810 ° C) were grown on the grown un- , And an Mg-doped p-GaN layer (150 nm, 980 ° C).

Then, mesa etching was performed with an inductively coupled plasma (ICP) etcher to etch the n-GaN layer using Cl 2 / BCl 3 / Ar gas for n-pad formation to fabricate a 350 × 350 μm 2 size device. Then, a 200 nm thick indium tin oxide (ITO) layer was deposited as a transparent layer, and then a metal layer of Cr (50 nm) / Au (250 nm) was deposited using an electron beam evaporator to form n-, p- .

( Comparative Example  2-1)

A semiconductor optoelectronic device was fabricated in the same manner as in Example 2-1 except that the thermally conductive layer was not formed in Example 2-1 and the semiconductor optoelectronic structure was formed on the sapphire substrate.

( Test Example  2-1)

FIGS. 7A to 7C are Raman mapping images of a GaN buffer layer formed on the thermally conductive layer in the semiconductor optoelectronic device fabricated in Example 2-1, and FIG. 7D is Raman spectra of regions A and B in FIG. 7C.

7A is represented by the RBM mode of the CNT, and the image of FIG. 7B is represented by the A 1 (LO) mode of the GaN. It can be seen from FIG. 7A that the GaN is formed on the thermally conductive layer structure Can be confirmed. In FIG. 7C, it can be seen that the green color associated with GaN is observed near the red color associated with the RBM of CNT by overlapping FIG. 7A and FIG. 7B. As a result of the Raman measurement of the regions A and B shown in FIG. 7C, it can be seen that the GaN buffer layer is grown near the CNT.

( Test Example  2-2)

FIG. 8A is an AFM image of the GaN epilayer fabricated in Example 2-1, and FIG. 8B is an AFM image of the GaN epilayer fabricated in Comparative Example 2-1.

As a result of the RMS measurement on the surface roughness, it was confirmed that the GaN thin film grown on the sapphire substrate of FIG. 8B was 0.21 nm, and the GaN thin film grown on the thermal conductive layer of FIG. 8A had a surface roughness of 0.16 nm.

In addition, the pits shown in FIGS. 8A and 8B are associated with pure-screw or mixed dislocations propagating to the surface of the GaN thin film. When the heat conduction layer is applied, the etch pit density is reduced and the quality of the thin film is improved Can be observed.

( Test Example  2-3)

9A and 9B are XRD omega rocking curves for the (a) symmetric (002) and (b) asymmetric (102) reflections of the GaN thin films prepared in Example 2-1 and Comparative Example 2-1. 9A and 9B, the red graph is for the GaN thin film produced in Example 2-1, and the black graph is for the GaN thin film prepared in Comparative Example 2-1.

9A and 9B, the full width half maximum (FWHM) value of the (002) plane rocking curve is related to the screw or mixed dislocation in the film, and the FWHM value of the rocking curve of the (102) edge, screw, and mixed dislocation.

As a result of measurement, the FWHM value of the (102) plane is reduced to 490 arcsec for the GaN thin film grown in Example 2-1, while the FWHM value of the (002) plane is similar. This indirectly indicates that the edge dislocation in the thin film is reduced when the thermally conductive layer is applied.

( Example  2-4)

10A and 10B are (a) Raman spectra and (b) PL spectra of the GaN thin films prepared in Examples 2-1 and 2-1. The Raman spectra and PL spectra were measured at room temperature.

Referring to FIGS. 10A and 10B, it can be seen that the stress of the GaN thin film produced in Example 2-1 is relaxed as compared with the GaN thin film prepared in Comparative Example 2-1 as a result of Raman measurement, and E 2 it can be observed that the quality of the thin film is improved by decreasing the FWHM of the high peak. As a result of PL measurement, the improvement of intensity of near band-edge peaks and red-shift shows that the compressive strain in the thin film is effectively mitigated and the quality of the thin film is improved similarly to the Raman result.

(Embodiment 2-5)

11A and 11B are PL spectra measured at 10 K and 300 K of the semiconductor optoelectronic device manufactured in Comparative Examples 2-1 and 2-1.

Referring to FIGS. 11A and 11B, the internal quantum efficiency (IQE) can be calculated from the low temperature PL at 10 K and the room temperature PL at 300 K. The calculated IQE is 32% for the semiconductor optoelectronic device manufactured in Comparative Example 2-1 and 39% for the semiconductor optoelectronic device manufactured in Example 2-1, which means that the IQE increases. This is because the threading dislocation in the thin film is effectively reduced by the thermally conductive layer.

( Example  2-6)

Figs. 12A to 12C are (a) I-V characteristics, (b) L-I curves, and (c) EL spectra for the semiconductor optoelectronic device manufactured in Example 2-1 and Comparative Example 2-1. FIG. 12C is a graph of the injection current measured at 20 mA. 12A to 12C, the red graph is for the semiconductor optoelectronic device manufactured in Example 2-1, and the black graph is for the semiconductor optoelectronic device manufactured in Comparative Example 2-1.

Referring to FIGS. 12A to 12C, as a result of current-voltage measurement, the forward voltage of each device was 3.86 eV for the semiconductor optoelectronic device manufactured in Comparative Example 2-1, and the semiconductor optoelectronic device manufactured in Example 2-1 It can be confirmed that when the thermally conductive layer structure is applied to an LED device, the electrical characteristics of the device are not deteriorated. As a result of the improvement of the light output power and the improvement of the electroluminescence peak intensity, the efficiency of the device is effectively improved when the thermally conductive layer is applied.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention as set forth in the appended claims. The present invention can be variously modified and changed by those skilled in the art, and it is also within the scope of the present invention.

1, 10: substrate 20: thermally conductive layer
2, 30: Semiconductor optoelectronic structure 2a, 31: First semiconductor layer
2b, 32: active layer 2c, 33: second conductivity type semiconductor layer
34: a nitride semiconductor layer 3, 40: a first electrode
4, 50: second electrode 100, 200: semiconductor optoelectronic element

Claims (11)

Board,
A thermally conductive layer disposed on the substrate, and
And a semiconductor optoelectronic structure positioned above the thermally conductive layer,
Wherein the thermally conductive layer comprises a graphene graphene layer and a carbon nanotube layer formed between the graphene layer and the semiconductor optoelectronic structure and including a carbon nanotube,
Wherein the semiconductor optoelectronic structure includes a multilayer structure in which a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer are sequentially stacked. The method according to claim 1,
The surface energy at the interface between the graphene layer and the carbon nanotube layer in the graphene layer and the surface energy at the interface between the graphene layer and the carbon nanotube layer are different from the surface energy at the interface between the graphene layer and the carbon nanotube layer, Optoelectronic device. The method according to claim 1,
Wherein the carbon nanotubes have an average diameter of 500 nm or less and a length of 10 to 20 mu m. delete The method according to claim 1,
The first conductivity type semiconductor layer is an n-type semiconductor layer, and the second conductivity type semiconductor layer is a p-type semiconductor layer. The method according to claim 1,
Wherein the semiconductor optoelectronic structure further comprises a nitride semiconductor layer located between the first conductive semiconductor layer and the thermally conductive layer. The method according to claim 6,
Wherein the nitride semiconductor layer comprises a nitride semiconductor grown horizontally. The method according to claim 1,
Wherein the semiconductor optoelectronic structure further comprises a reflective layer or a transparent electrode on the second conductive type semiconductor layer. Forming a thermally conductive layer by sequentially forming a graphene layer including graphene on the substrate and a carbon nanotube layer including carbon nanotubes on the graphene layer; And
Forming a semiconductor optoelectronic structure on the thermally conductive layer
Gt; a &lt; / RTI &gt; semiconductor optoelectronic device. 10. The method of claim 9,
The thermally conductive layer forming step may be performed by forming a graphene layer on a substrate using a Scotch-tape method, a transfer method, or a spin coating method, and then forming a carbon nanotube layer on the graphene layer by spin coating &Lt; / RTI &gt; 10. The method of claim 9,
And removing the substrate located on the back surface of the thermally conductive layer after the step of forming the semiconductor optoelectronic structure.
KR1020150089435A 2014-08-01 2015-06-24 Optoelectronic semiconductor device and method for manufacturing same KR101731862B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20140099280 2014-08-01
KR1020140099280 2014-08-01

Publications (2)

Publication Number Publication Date
KR20160016586A KR20160016586A (en) 2016-02-15
KR101731862B1 true KR101731862B1 (en) 2017-05-02

Family

ID=55357260

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020150089435A KR101731862B1 (en) 2014-08-01 2015-06-24 Optoelectronic semiconductor device and method for manufacturing same

Country Status (1)

Country Link
KR (1) KR101731862B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109103308B (en) * 2018-09-18 2024-07-30 佛山市国星半导体技术有限公司 LED wafer and manufacturing method thereof
CN109671818B (en) * 2018-11-28 2020-05-19 华灿光电（浙江）有限公司 Gallium nitride-based light emitting diode epitaxial wafer and preparation method thereof
KR102284880B1 (en) * 2019-03-31 2021-08-03 경기대학교 산학협력단 Single Crystal Layer Structure and Micro LED and Micro LED Module having the Same and Manufacturing Method of them
CN117497681B (en) * 2023-12-29 2024-04-05 南昌凯捷半导体科技有限公司 Mini-LED chip and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101375145B1 (en) * 2013-04-17 2014-03-21 국립대학법인 울산과학기술대학교 산학협력단 Graphene conductive layer having carbon member, method of manufacturing the same, and optoelectric device, solar cell, and electronic device having the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101375145B1 (en) * 2013-04-17 2014-03-21 국립대학법인 울산과학기술대학교 산학협력단 Graphene conductive layer having carbon member, method of manufacturing the same, and optoelectric device, solar cell, and electronic device having the same

Also Published As

Publication number Publication date
KR20160016586A (en) 2016-02-15

Similar Documents

Publication Publication Date Title
US8916850B2 (en) Light-emitting element and method for manufacturing same
US9048389B2 (en) Light emitting diode
TWI649895B (en) High-efficiency ultraviolet light-emitting diode with variable structure position
TWI359506B (en) Light-emitting device and manufacturing method the
TWI436424B (en) Semiconductor device and fabrication method thereof
TW201013987A (en) Group III nitride semiconductor light emitting device, process for producing the same, and lamp
US9166101B2 (en) Light-emitting element and method for manufacturing same
CN106415860B (en) Nitride semiconductor light emitting device
TW201010139A (en) Light-emitting diode with non-metallic reflector
KR101731862B1 (en) Optoelectronic semiconductor device and method for manufacturing same
US8598605B2 (en) Semiconductor light-emitting device
TWI607582B (en) Semiconductor device and the manufacturing method thereof
KR101481593B1 (en) Non-polar nitride-based light emitting device and method for the same
JP2005072310A (en) Method for manufacturing group iii nitride compound semiconductor
TWI567877B (en) Manufacturing method of nitride semiconductor device
JP2008066591A (en) Compound semiconductor light emitting device, illumination apparatus employing the same and manufacturing method of compound semiconductor device
KR102070209B1 (en) A growth substrate and a light emitting device
Hayashi et al. Thermally engineered flip-chip InGaN/GaN well-ordered nanocolumn array LEDs
JP2010010444A (en) Semiconductor light emitting element, lamp and method of manufacturing semiconductor light emitting element
JP2018022814A (en) Nitride semiconductor device and method of manufacturing the same
JP2010056459A (en) Method of producing light-emitting device
Yan et al. High-efficiency GaN-based blue LEDs grown on nano-patterned sapphire substrates for solid-state lighting
JP6482388B2 (en) Nitride semiconductor light emitting device
JP2014120666A (en) Nitride semiconductor solar cell, nitride photoelectric transducer, method of manufacturing nitride semiconductor solar cell
KR101349550B1 (en) Method of fabricating light emitting diode

Legal Events

Date Code Title Description
A201 Request for examination
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant