KR101689972B1 - A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for single-phase full-wave application - Google Patents

Abstract

There is no constitution of another ordinary transformer circuit and a structure of a zener diode element in a voltage converter for converting a high voltage of AC and DC power to a DC power of low voltage and the voltage between negative gate sources (NMOS) field-effect transistor (FET), that is, a negative threshold voltage 5-terminal NMOS transistor (negative threshold 5-terminal NMOS FET). Therefore, the circuit area of the transformer circuit 101 and the zener diode 104 is usually removed to remove the area occupied by the circuit area of the transformer circuit 101 and the zener diode 104, It is possible to implement a cost circuit and realize a circuit without power consumption in standby and operation power supply state by blocking standby and operation power loss and to realize free voltage operation up to high voltage supply region As shown in FIG.
In addition, it is a power supply device featuring negative power amplification that enables negative voltage generation and supply using a negative DC / DC converter circuit.

Description

TECHNICAL FIELD [0001] The present invention relates to a power supply circuit device using a 5-terminal NMOS transistor device, and a power supply circuit device using the NMOS FET device with a single step connection for a single step, phase full-wave application}

(EN) A voltage converting apparatus for converting a high voltage alternating current and a direct current (DC) power source to a low voltage direct current power source, characterized in that the constitution of the circuit region of the transformer circuit (101) and the zener diode ) And zener diode (104) circuit area, thereby realizing a low-cost circuit and preventing standby and operation power loss, thereby realizing a circuit without power consumption in standby and operation power supply state And a power supply circuit device capable of implementing a free voltage operation using a negative threshold voltage emmos transistor element.

In a voltage converting apparatus for converting a high voltage AC power source to a low voltage DC power source, the normal voltage transforming circuit 101 is a circuit region causing a large area and cost in the circuit structure.

Therefore, it becomes an obstacle factor in constructing a low cost circuit. On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

At this time, a constant current is allowed to flow through the Zener diode 104 in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

In order to solve such a problem, it is necessary to construct a circuit without power loss in standby and operation power supply states. Particularly, in terms of energy saving, a circuit configuration without power loss in a standby state is desperately needed.

In addition, a circuit having the same characteristics as described above is also required when converting the voltage of the DC power source such as the automobile power supply to a low voltage.

In recent years, the role of surge protection to protect the system from system transients and lightning-induced transients in the field of communication and ESD (electrostatic discharge) protection to protect circuits against static electricity in mobile communication terminals, notebook PCs, A PN varistor is required.

It is used as a surge absorbing element to prevent a sudden change in voltage (surge) to appliances such as various information devices and control devices. It is used in various parts ranging from power devices such as power plants, substations, and power stations to the core devices of lightning arresters for safeguarding equipment from lightning strikes.

Accordingly, there is a strong demand for protecting the system from power surges, ridiculous surges, and the like that occur in these devices.

A surge protection device (SPD, VTMS, or Transient Voltage Surge Suppressor: TVSS) is used in order to prevent surges from destroying or malfunctioning electronic equipment installed in the power system from such transient external surges. Should be installed.

The embodiment of the present invention has the following features.

First, the circuit area of the normal transformer circuit 101 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 101 and the zener diode 104, Which makes it possible to implement a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 101 and the zener diode 104, it is possible to implement a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss .

Third, a negative threshold Vt depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) critical high voltage (about 1000V or higher) A free voltage operation can be realized.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, effect transistors, i.e., elements of a negative threshold 5-terminal NMOS FET, to enable stable operation in the operational characteristics of the circuit. .

Fifth, even when the voltage of the DC power source such as the automobile power source is converted into the DC voltage of the low voltage, the same circuit can be used to implement it.

Sixth, it is possible to realize the function of PN varistor as the role of power surge, Brain Brain surge, and electrostatic discharge (ESD) protection.

Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. . ≪ / RTI >

Eighth, N times of voltage is used as the power source of the control circuit to control the gate voltage of the negative threshold 5-terminal NMOS FET at a high voltage to amplify the power Amplification) is possible.

Ninth, Negative DC / DC Converter circuit is used to make negative voltage generation and supply possible.

A voltage converting apparatus for converting a high-voltage alternating current and a direct-current power source into a low-voltage direct-current power source, the configuration of the ordinary transformer circuit 101 is removed to save a large area and power consumption in the constitution of the transformer circuit 101 So that a low-cost circuit can be constituted. In addition, the structure of the Zener diode 104 circuit area is removed to reduce the area occupied in the circuit area of the Zener diode 104, and the standby and operation power consumption, And to realize a circuit without power loss in standby and operation power supply states.

In addition, since the input voltage of the high voltage AC and DC power supplies must operate over a wide voltage range, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. And a free voltage operation characteristic.

A depletion NMOS transistor having a negative threshold voltage, that is, a voltage between negative gate sources (negative Vgs), in a voltage converter for converting AC and DC power to a voltage of a DC power source, Includes a configuration of a field effect transistor (FET), that is, a configuration of a negative threshold 5-terminal NMOS FET. The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, an isolated body, B) and a P-substrate (P-substrate: P-Sub). The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, . The gate is connected to the ground terminal of the P-substrate and the drain D is connected to the terminal to which power is supplied before the voltage conversion. -1 power supply terminal, respectively.

As described above, the embodiment of the present invention has the following effects.

First, the circuit area of the normal transformer circuit 101 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 101 and the zener diode 104, Thereby enabling implementation of a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 101 and the zener diode 104, it is possible to implement a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss do.

Third, the input voltage of AC and DC power supplies of high voltage must operate over a wide voltage range. Therefore, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. (About 1000 V or more) power supply voltage range.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, transistor, or a negative threshold 5-terminal NMOS FET), so that a stable operation can be realized in the operational characteristics of the circuit. Effect.

Fifth, the same circuit can be used to convert a voltage of a DC power source such as a vehicle power source into a DC voltage of a low voltage.

Sixth, it is possible to implement a PN varistor function as a role of power surge, rational brace, and electrostatic discharge (ESD) protection.

Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. The present invention provides an effect that is feasible.

Eighth, N times of voltage is used as the power source of the control circuit to control the gate voltage of the negative threshold 5-terminal NMOS FET at a high voltage to amplify the power Amplification can be realized.

Ninth, the negative DC / DC converter circuit can be used to generate and supply negative voltage.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode; Fig.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
FIG. 5 is a schematic diagram of a power supply terminal synthesis configuration of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention. FIG.
6 is an operational waveform diagram of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode.

A rectifying circuit 102 and a zener diode 104 in a voltage converting apparatus for converting an AC input power supply 100 into a low voltage DC power supply voltage do. The transformer circuit 101 is a circuit region for converting a high voltage input power supply to a low voltage.

The rectifying circuit 102 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source to a DC power source. The transformer circuit 101 is usually a circuit area that causes a large area and cost in the construction of the circuit.

Therefore, it becomes an obstacle factor in constructing a low cost circuit.

On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal 103 of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

The output terminal 103 of the rectifying circuit 102 is used as the final output Step-1 power supply terminal 105. [

At this time, a constant current flows to the Zener diode in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A configuration of a depletion NMOS field effect transistor (FET) having a negative threshold voltage Vt, that is, a voltage between negative gate sources (negative Vgs) And a configuration of a threshold voltage 5-terminal NMOS FET.

The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, an isolated body, B) and a P-substrate (P-substrate).

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, .

The P-type isolated body (B) terminal has an isolated element structure and is connected to a common ground terminal for supplying a 0V ground voltage according to a design selection method as follows The first connection method and the second connection method, which is connected to the source (S) terminal and used as an output terminal, are possible.

More specifically,

As a first method, the gate (G) terminal, the isolated body (B) terminal, and the P-substrate (P-sub) Respectively.

In another alternative method, the gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V, An isolated body (B) terminal is connected to the source (S) terminal and is used as an output terminal.

And the gate (G) terminal may be supplied with a separate control voltage.

The drain (D) terminal is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

In addition, the drain (D) terminal region may surround the isolated body (B) terminal and the source (S) terminal region and may be included in the drain (D) terminal region .

The drain (D) terminal region is directly contacted with a P-substrate (P-sub) terminal to form a PN varistor structure.

The PN varistor is connected in parallel to the drain (D) terminal region to be protected. The PN varistor acts as a nonconductor at a constant voltage or lower, but it does not affect the circuit. However, when a certain voltage or more is applied, the PN varistor connected in parallel becomes a conductor, - P-substrate (P-sub) terminal to protect the device from surge.

Additional operating characteristics of the PN varistor structure are as follows.

Varistors are short for variable resistors, sometimes called VDRs (Voltage-Dependent Resistors). The role of the PN varistor is a semiconductor device whose resistance varies according to the input voltage, as can be expected from the above name.

A typical PN varistor is characterized by a nonlinear I-V plot, which acts as an insulator for electricity until a certain breakdown voltage, but after the breakdown voltage it exhibits the nature of the conductor.

When a low voltage microprocessor is used in a system or device, a surge that occurs when a lightning strike or switch is opened can cause system stoppage, equipment burnout or deterioration, data transmission error, communication error, The failure of the system, such as inoperability, can occur momentarily. This is a big weakness of the system using the semiconductor. To protect this weak point, a PN varistor is needed.

The source S terminal is a semiconductor doping region having an n-type semiconductor characteristic and is used as an output terminal for obtaining a target output power supply voltage. The source S terminal may be connected to the isolated body B terminal as an output terminal or may be used as an output terminal using only the source S terminal. Specification characteristics.

3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A negative threshold voltage at the Vds between the gate (G) terminal and the source (S) terminal, Vgs, and the current between the drain (D) terminal and the source (S) A threshold voltage value of a voltage 5-terminal NMOS FET is characterized by having a negative value (VT).

4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The rectification and power supply circuit of the present invention is a circuit region for converting AC input power to DC output power. It is also characterized in that it can be used for converting DC input power to DC output power.

That is, the present invention is also applicable to a case where a DC power source is connected to a DC power source regardless of the polarity of the DC power source.

The rectification and power supply circuit of the present invention includes an input power source 400 for inputting power, a first half-wave rectification power generator 460 and a second half-wave rectification power generator 470 circuit corresponding to two half- .

A first input terminal 401 which is two input terminals of the single phase input power supply 400 is connected to an input terminal of the first half wave rectification power generator 460 and a second input terminal 402 is connected to the second half wave rectification power generator 460. [ (470).

The circuit configurations of the first half-wave rectification power generator 460 and the second half-wave rectification power generator 470 in the respective circuit areas are the same.

Wave rectification power generator 460 and the second half-wave rectification power generator 460 are the same as those in the circuit areas of the first half-wave rectification power generator 460 and the second half-wave rectification power generator 460. Therefore, 470), the detailed circuit configuration will be described as follows.

The first input terminal 401 or the second input terminal 402 which are the two input terminals of the single phase input power supply 400 are connected to the first half wave rectification power generator 460 or the second half wave rectification power generator 460, A drain (D) terminal (404; 410; 416; 426) of a plurality of N negative threshold 5-terminal NMOS FETs (403; 409, 415; 421) 422, respectively.

The connection configuration of the first negative threshold voltage 5-terminal NMOS FET 403 is as follows.

The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics doping region connected to the P-type terminal of the output PN diode D1. The N-type terminal of the output PN diode D1 is used as a Step-1 power supply terminal 408 which is an output terminal for obtaining a target output power supply voltage.

The source (S) terminal 407 is connected to the P-type isolated body (B) terminal 403 of the negative threshold 5-terminal NMOS FET 403 And may be used as an output terminal by using only the source (S) terminal 407. In addition,

The drain (D) terminal 404 is connected to the first input terminal 401 or the second input terminal 401 of the single-phase input power supply 400 as a semiconductor doping region having n-type semiconductor characteristics 402, respectively. The drain (D) terminal 404 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The connection configuration of the second negative threshold voltage 5-terminal NMOS FET 409 is as follows.

The source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 is a semiconductor doping having an n-type semiconductor characteristic doping region connected to the P-type terminal of the output PN diode D2. The N-type terminal of the output PN diode D2 is used as a Step-2 power supply terminal 414 which is an output terminal for obtaining a target output power supply voltage.

The source (S) terminal 413 is common to the isolated body (B) terminal of the negative threshold 5-terminal NMOS FET 409 And may be used as an output terminal, or may be used as an output terminal using only the source (S) terminal 413.

The drain (D) terminal 410 is a semiconductor doping region having an n-type semiconductor characteristic and is connected to the first input terminal 401 or the second input terminal 401 of the single- 402, respectively. The drain (D) terminal 410 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 409 may be, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 411 of the negative threshold 5-terminal NMOS FET 409 is connected to the negative threshold voltage 5-terminal NMOS transistor (negative) (S) terminal 407 of the threshold 5-terminal NMOS FET 403 or the Step-1 power supply terminal 408 serving as an output terminal. The P-substrate (P-sub) terminal 412 is connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The connection configuration of the Nth negative threshold voltage 5-terminal NMOS FET 415 is as follows.

The source terminal 419 of the negative threshold 5-terminal NMOS FET 415 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics doping region connected to the P-type terminal of D3, the output PN diode. The N-type terminal of the output PN diode D3 is used as a Step-N power supply terminal 420 which is an output terminal for obtaining a target output power supply voltage.

The source (S) terminal 420 is common to the isolated body (B) terminal of the negative threshold 5-terminal NMOS FET 415 Or may be used as an output terminal by using only the source (S) terminal 420. In addition,

The drain (D) terminal 416 is a semiconductor doping region having an n-type semiconductor characteristic. The first input terminal 401 or the second input terminal 416 of the single- 402, respectively. The drain (D) terminal 416 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 415 is set to a value of, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 417 of the negative threshold 5-terminal NMOS FET 415 is connected to the negative threshold voltage 5-terminal NMOS transistor 415 (S) terminal 413 of the threshold 5-terminal NMOS FET 409 or the Step-2 power supply terminal 414 which is an output terminal.

The P-substrate (P-sub) terminal 418 is connected to a common ground terminal for supplying a ground voltage of 0V.

Multiple N means one or more natural numbers. The source terminal S (N-1) or the output terminal Step- (N-1) of the negative threshold 5-terminal NMOS FET The next step is to connect the gate to the gate (G) terminal of the threshold voltage 5-terminal NMOS FET.

The control circuit is constituted by using the N-folded Step-N power supply terminal voltage generated as the power source.

The control circuit is composed mainly of an amplifier (OP amplifier) 430.

The reference voltage REF 441 is input to one terminal of the control circuit amplifier (OP amplifier) 430, and the other terminal is directly connected to the power amplifier terminal 426, which is a final power output terminal, One sensing voltage Vs 429 is input.

The reference voltage REF 441 is the voltage of the intermediate connection line in the serial connection configuration of the resistor element R 442 and the Zener diode 440.

The other terminal of the resistor element R1 442 is connected to the Step-N power supply terminal and to the other ground terminal of the Zener diode 440.

Meanwhile, the other terminal of the resistor R1 442 is connected to any one of the Step-1 power supply terminal, the Step-2 power supply terminal, or the Step-N power supply terminal.

The control output voltage of the Zener diode 440 is equal to the reference voltage REF 441.

The resistance element R1 442 serves as a control resistance element for supplying a minimum bias voltage for generating the control output voltage of the Zener diode 440. [

The voltage of the output terminal 431 of the control circuit amplifier (OP amplifier) 430 is a negative threshold 5-terminal NMOS FET 421, which is a power amplifier element. To the gate (G) terminal 423 of the flip-flop.

The drain (D) terminal 422 of the negative threshold 5-terminal NMOS FET 421 is connected to the first input terminal 401 of the single- Or the second input terminal (402).

The source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 is a semiconductor doping having an n-type semiconductor characteristic amp; power supply terminal 426, which is an output terminal for obtaining a target output power supply voltage in a " doping " region.

The source S terminal 425 is connected in common with the isolated body B terminal of the negative threshold 5-terminal NMOS FET 421 And may be used as an output terminal or may be used as the Power Amp power supply terminal 426 by using only the source (S) terminal 425.

The Power Amp power supply terminal 426 is applied to a high current supply capability and a high power consumption load. Accordingly, the negative threshold 5-terminal NMOS FET 421 becomes a device of a power amplifier having a high power driving capability.

The P-substrate (P-sub) terminal 424 of the negative threshold 5-terminal NMOS FET 421 is connected to a ground terminal Respectively, to a common ground terminal.

The input power of the negative DC / DC converter 450 circuit is input to the Power Amp power supply terminal 426. The negative DC / DC converter 450 generates a negative voltage and supplies a negative voltage to the negative voltage power supply terminal 451, which is an output terminal.

5 is a diagram illustrating a power supply terminal synthesis configuration of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.

The rectification and power supply circuit of the present invention includes an input power source 400 for inputting power, a first half-wave rectification power generator 460 and a first half-wave rectification power generator 460 corresponding to two half- .

A first input terminal 401 which is two input terminals of the single phase input power supply 400 is connected to an input terminal of the first half wave rectification power generator 460 and a second input terminal 402 is connected to the second half wave rectification power generator 460. [ (470).

The circuit configurations of the first half-wave rectification power generator 460 and the second half-wave rectification power generator 470 in the respective circuit areas are the same.

Step-1 power supply terminals 408 and Step-2 power supply terminals 414, which are the output power supply terminals of the first half-wave rectification power generator 460 or the second half-wave rectification power generator 470, The Step-N power supply terminal 420, the Power Amp power supply terminal 426, and the negative voltage power supply terminal 451 have the same circuit configuration in the circuit area.

Therefore, the Step-1 power supply terminal 408, which is the output power supply terminal of the first half-wave rectification power generator 460, and the Step-1 power supply terminal 408, which is the output power supply terminal of the second half-wave rectification power generator 470, ) Are connected to each other to constitute a combined Step-1 power supply terminal 508. The synthetic Step-2 power supply terminal 414, the composite Step-N power supply terminal 520, the composite Power Amp power supply terminal 526, and the composite negative voltage power supply terminal 551 Respectively.

6 is an operation waveform diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The input power source 500 includes an AC waveform of a first half wave and a second half wave and has a negative threshold voltage 5-terminal in a circuit region of the first half wave rectification power generator 460 or the first half wave rectification power generator 460 And is input to the drain (D) terminal of a negative threshold 5-terminal NMOS FET.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The voltage of the Step-1 power supply terminal 508 of the source S terminal 407 is lower than the threshold voltage Vt of the negative threshold 5-terminal NMOS FET : + 1V, + 2V, + 3V, + 4V, and the like, respectively, corresponding to the output voltage Vgs.

Further, the voltage is increased by the threshold voltage (Vgs) of the negative threshold voltage 5-terminal NMOS FET for each step.

Therefore, when N negative threshold voltage 5-terminal NMOS FETs are constructed in this way, voltages of N times of Vgs and voltages of N times Vgs can be obtained at the final stage .

Power Amp power supply terminal 526 is applied to high current supply capability and high power consumption load. Therefore, by designing to have the Power Amp power supply terminal 526 that is lower than the voltage of Step-N power supply terminal 520 which is N times the voltage, it is designed to be a device of Power Amplifier having high power driving capability under high Vgs voltage driving condition .

The Negative Voltage power supply terminal 551, which is the negative output terminal signal of the Negative DC / DC Converter 450 circuit, is a power supply characterized by a negative voltage implementation.

100 input power
101 transformer circuit
102 rectifier circuit
104 Zener diode
105 Step-1 Power supply terminal
400 input power
401 first input terminal
402 second input terminal
403 negative threshold voltage 5-terminal NMOS FET with negative threshold
404 drain (D) terminal
405 gate (G) terminal
406 P-substrate (P-sub) terminal
407 source (S) terminal
408 Step-1 power supply terminal
414 Step-2 power supply terminal
420 Step-N power supply terminal
426 Power Amp power supply terminal

Claims (3)

1. A power supply apparatus for converting a high-voltage AC or DC input power supply to an output voltage of low voltage,
A first input terminal 401 of the input power supply 400; And
A second input terminal 402 of the input power supply 400; And
In the first half-wave rectification power generation circuit region,
A negative threshold 5-terminal NMOS FET 421 as a power amplifier; And
A drain (D) terminal 422 of the negative threshold 5-terminal NMOS FET 421 coupled to the first input terminal 401; And
A P-type terminal of D4, which is an output PN diode connected to the source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421; And
A Power Amp power supply terminal 426 connected to the N-type terminal of the output PN diode D4 to supply the output power; And
The gate of the negative threshold 5-terminal NMOS FET 421 connected to the voltage of the output terminal 431 of the control circuit amplifier (OP amplifier) ) Terminal 423; And
A common ground terminal connected to a P-substrate (P-sub) terminal 424 to supply a ground voltage; And
An isolated body (B) terminal connected to the source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421; And
A Negative DC / DC Converter 450 circuit having an input terminal connected to the Power Amp power supply terminal 426 to generate a negative voltage; And
And a negative voltage power supply terminal (451) connected to an output terminal of the negative DC / DC converter (450) circuit. delete delete

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