KR101660653B1 - Scannig drive circuit and display device including the same - Google Patents

Abstract

A display control line, a data line extending in a second direction different from the first direction, and a display having a scan driving circuit, the display device comprising: a display element arranged in a two-dimensional matrix form; Device is provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display device having a scan driving circuit and a scan driving circuit,

The present invention relates to a display device provided with a scan driving circuit and a scan driving circuit. More specifically, the present invention relates to a scan driving circuit capable of easily adjusting the ratio of the display period to the non-display period in each display element constituting the display device, and a display device provided with the scan driving circuit .

A liquid crystal display device comprising a voltage-driven liquid crystal cell, a display device including a display element arranged in a two-dimensional matrix, and a light emitting portion (for example, an organic electroluminescence light emitting portion) And a display device comprising a driving circuit for driving the display device.

The luminance of the display element having the light emitting portion that emits light by flowing the current is controlled by the current value flowing through the light emitting portion. Also, in a display device (such as an organic electroluminescence display device) provided with such a display device such as a liquid crystal display device, a simple matrix method and an active matrix method are given as a driving method. The active matrix method has a drawback in that the structure is complicated as compared with the simple matrix method, but there are various advantages such that the luminance of the image can be increased.

As the circuit for driving the light emitting portion by the active matrix method, various driving circuits composed of a transistor and a capacitor portion are given. For example, Japanese Unexamined Patent Application Publication No. 2005-31630 discloses a display device using a display element comprising an organic electroluminescence light emitting portion and a driving circuit, and a driving method thereof. This driving circuit is a driving circuit composed of six transistors and one capacitor (hereinafter referred to as a 6Tr / 1C driving circuit). Fig. 19 shows an equivalent circuit diagram of a driving circuit (6Tr / 1C driving circuit) constituting the display elements of the m-th row and the n-th column in a display device in which display elements are arranged in a two-dimensional matrix. In this case, the display elements are sequentially scanned line by line.

The 6Tr / 1C driving circuit further includes a first transistor TR1, a second transistor TR2, a third transistor TR3, and a fourth transistor TR4, which are provided with a write transistor TRW, a drive transistor TRD, and a capacitor C1 have.

In the writing transistor TRW, one of the source / drain regions is connected to the data line DTLn, and the gate electrode is connected to the scanning line SCLm. In the driving transistor TRD, one of the source / drain regions is connected to the other one of the source / drain regions of the writing transistor TRW and constitutes the first node ND1. One end of the capacitor C1 is connected to the feeder line PS1. In the capacitor C1, a predetermined reference voltage (voltage VCC described later in the example shown in Fig. 19) is applied to one end, and the gate electrode of the other transistor and the driving transistor TRD is connected to constitute the second node ND2. The scanning line SCLm is connected to a scanning circuit (not shown), and the data line DTLn is connected to the signal output circuit 100.

In the first transistor TR1, one of the source / drain regions is connected to the second node ND2, and the other of the source / drain regions is connected to the other of the source / drain regions of the driving transistor TRD. The first transistor TR1 constitutes a switch circuit portion connected between the second node ND2 and the other one of the source / drain regions of the driving transistor TRD.

In the second transistor TR2, one of the source / drain regions is connected to the feeder line PS3 to which a predetermined initializing voltage VIni (for example, -4 volts) for initializing the potential of the second node ND2 is applied, Is connected to the second node ND2. The second transistor TR2 constitutes a switch circuit portion connected between the second node ND2 and the feeder line PS3 to which a predetermined initialization voltage VIni is applied.

In the third transistor TR3, one of the source / drain regions is connected to the power supply line PS1 to which a predetermined driving voltage VCC (for example, 10 volts) is applied, and the other of the source / drain regions is connected to the first node ND1 Respectively. The third transistor TR3 constitutes a switch circuit portion connected between the first node ND1 and the feeder line PS1 to which the drive voltage VCC is applied.

In the fourth transistor TR4, one of the source / drain regions is connected to the other one of the source / drain regions of the driving transistor TRD, and the other of the source / drain regions is connected to one end (more specifically, And the anode electrode of the light emitting portion ELP). The fourth transistor TR4 constitutes a switch circuit portion connected between the other one of the source / drain regions of the driving transistor TRD and one end of the light emitting portion ELP.

The gate electrode of the writing transistor TRW and the gate electrode of the first transistor TR1 are connected to the scanning line SCLm. The gate electrode of the second transistor TR2 is connected to the initialization control line A Zm. A scanning signal supplied to a scanning line SCLm-1 (not shown) which is scanned immediately before the scanning line SCLm is also supplied to the initialization control line AZm. The gate electrode of the third transistor TR3 and the gate electrode of the fourth transistor TR4 are connected to a display control line CLm for controlling the display state / non-display state of the display element.

For example, each transistor is formed of a p-channel thin film transistor (TFT), and the light emitting portion ELP is provided on an interlayer insulating layer or the like formed to cover the driving circuit. In the light-emitting portion ELP, the anode electrode is connected to the other of the source / drain regions of the fourth transistor TR4, and the cathode electrode is connected to the feeder line PS2. A voltage VCat (for example, -10 volts) is applied to the cathode electrode of the light emitting portion ELP. And reference character CEL denotes the parasitic capacitance of the light emitting portion ELP.

When the transistor is composed of a TFT, fluctuation of the threshold voltage to some extent can not be avoided. If the amount of current flowing in the light emitting portion ELP fluctuates in accordance with the deviation of the threshold voltage of the driving transistor TRD, the uniformity of the luminance in the display device is deteriorated. Therefore, even if the threshold voltage of the driving transistor TRD fluctuates, it is necessary to prevent the amount of current flowing in the light emitting portion ELP from being influenced. As described later, the light emitting portion ELP is driven so as not to be influenced by the deviation of the threshold voltage of the driving transistor T RD.

Referring to Fig. 20, a method of driving the m < th > row and the n < th > column display elements in a display device in which N x M display elements are arranged in a two-dimensional matrix form will be described. 20A is a schematic timing chart of signals in the initialization control line AZm, the scanning line SCLm, and the display control line CLm. 20B, 20C, and 20D schematically show on / off states of each transistor of the 6Tr / 1C drive circuit. For convenience of explanation, the period in which the initialization control line AZm is scanned is referred to as the (m-1) -th horizontal scanning period, and the period in which the scanning line SCLm is scanned is referred to as the m-th horizontal scanning period.

As shown in Fig. 20A, an initialization step is performed in the (m-1) th horizontal scanning period. Will be described in detail with reference to FIG. 20B. In the (m-1) -th horizontal scanning period, the initialization control line AZm goes from the high level to the low level, and the display control line CLm goes from the low level to the high level. On the other hand, the scanning line SCLm is at a high level. Therefore, in the (m-1) -th horizontal scanning period, the writing transistor TRW, the first transistor TR1, the third transistor TR3, and the fourth transistor TR4 are off. On the other hand, the second transistor TR2 is on.

A predetermined initializing voltage VIni for initializing the potential of the second node ND2 is applied to the second node ND2 through the second transistor TR2 in the ON state. Thus, the potential of the second node ND2 is initialized.

Next, as shown in Fig. 20A, the video signal VSig is recorded in the m-th horizontal scanning period. At this time, the threshold voltage canceling process of the driving transistor TRD is performed together. More specifically, the second node ND2 is electrically connected to the other one of the source / drain regions of the driving transistor TRD, and the video signal VSig is supplied from the data line DTLn through the writing transistor TRW turned on by the signal from the scanning line SCLm To the first node ND1. Thereby, the potential of the second node ND2 is changed from the video signal VSig toward the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD.

Will be described in detail with reference to Figs. 20A and 20C. In the m-th horizontal scanning period, the initialization control line AZm goes from the low level to the high level, and the scanning line SCLm goes from the high level to the low level. At this time, the display control line CLm is at a high level. Therefore, in the m-th horizontal scanning period, the writing transistor TRW and the first transistor TR1 are on. On the other hand, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 are off.

The other of the source / drain regions of the second node ND2 and the driving transistor TRD is electrically connected through the first transistor TR1 in the ON state, and the data line The video signal VSig is applied to the first node ND1 from the DTLn. As a result, the potential of the second node ND2 changes from the video signal VSig toward the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD.

That is, when the potential of the second node ND2 is initialized such that the driving transistor TRD is turned on in the period of the m-th horizontal scanning period by the above-described initialization process, the potential of the second node ND2 is To the potential of the video signal VSig applied to the node ND1. However, when the potential difference between the gate electrode of the driving transistor TRD and one of the source / drain regions reaches Vth, the driving transistor TRD is turned off. In this state, the potential of the second node ND2 is approximately (VSig-Vth).

Subsequently, a current flows through the driving transistor TRD to the light emitting portion ELP, thereby driving the light emitting portion ELP.

Will be described in detail with reference to Figs. 20A and 20D. In the end of the m-th horizontal scanning period, the scanning line SCLm goes from the low level to the high level. Further, the display control line CLm is changed from the high level to the low level. On the other hand, the initialization control line AZm maintains a high level. The third transistor TR3, and the fourth transistor TR4 are on. The write transistor TRW, the first transistor TR1, and the second transistor TR2 are off.

The driving voltage VCC is applied to the source / drain region of one of the driving transistors TRD through the third transistor TR3 in the ON state. Further, the other of the source / drain regions of the driving transistor TRD and the one end of the light emitting portion ELP are connected through the fourth transistor TR4 in the ON state.

Since the current flowing through the light emitting portion ELP is the drain current Ids flowing from the source region to the drain region of the driving transistor TRD, if the driving transistor TRD operates ideally in the saturation region, it can be expressed by the following Expression (1).

Ids = k 占 占 (Vgs-Vth) ² (1)

In this case, μ is an effective mobility, Vth is a threshold voltage, Vgs is a voltage between the source region and the gate electrode of the driving transistor TRD, and k is a constant.

Here, the constant k is given by equation (2).

k? (1/2) (W / L) Cox (2)

In this case, L is the channel length, W is the channel width, and Cox is the (dielectric constant of the gate insulating layer) x (dielectric constant of vacuum) / (thickness of the gate insulating layer).

Therefore, as shown in Fig. 20D, the drain current Ids flows in the light emitting portion ELP, and the light emitting portion ELP emits light with the luminance corresponding to the value of the drain current Ids.

The voltage Vgs is also given by equation (3).

Vgs? VCC- (VSig-Vth) (3)

Therefore, equation (1) can be transformed into equation (4).

Ids = k 占 占 (VCC- (VSig-Vth) -Vth) ²

= k · μ · (VCC-VSig) ²

As is clear from the equation (4), the threshold voltage Vth of the driving transistor TRD is independent of the value of the drain current Ids. In other words, the drain current Ids corresponding to the video signal VSig can be caused to flow in the light emitting portion ELP without being influenced by the value of the threshold voltage Vth of the driving transistor TRD. According to the driving method described above, it is possible to prevent the deviation of the threshold voltage Vth of the driving transistor TRD from affecting the brightness of the display element.

In order to operate the display device having the above-described display element, a circuit for supplying signals to the scanning line, the initialization control line, and the display control line is required. From the viewpoints of reducing the layout area occupied by these circuits and reducing the circuit cost, it is preferable that the circuit for supplying these signals is a circuit of an integrated structure. It is also possible to easily change the setting of the width of the pulse to be supplied to the display control line without affecting the signal supplied to the scanning line or the initialization control line. By increasing the ratio of the non-display period, It is preferable from the viewpoint of improvement.

In order to solve such a problem, an object of the present invention is to provide a plasma display apparatus capable of supplying a signal to a scanning line, an initialization control line, and a display control line, And a display device including the scan driving circuit.

In order to achieve the above object, according to an embodiment of the present invention,

(1) a display element arranged in a two-dimensional matrix,

(2) a scanning line extending in the first direction, an initialization control line, a display control line,

(3) a data line extending in a second direction different from the first direction, and

(4) A display device provided with a scan driving circuit is provided,

The scan driving circuit comprising:

(A) a shift register unit comprising a plurality of shift registers, sequentially shifting input start pulses and outputting an output signal from the plurality of shift registers,

(B) a logic circuit section which is composed of a plurality of logic circuits and which operates based on an output signal outputted from the shift register section and two or more kinds of enable signals,

Each of the plurality of logic circuits includes:

(a) an input signal input to a corresponding one of the shift registers,

(b) an output signal output from a corresponding one of the shift registers,

(c) at least one enable signal

And outputs a signal based on the signal,

A signal based on one of the output signals output from the corresponding one of the shift registers of the shift register section is supplied to the m-th display element through the m-th display control line,

A signal based on one of the output signals output from the corresponding one of the logic circuits is supplied to the m-th display element via the m-th scan line,

the signal supplied to the (m-1) th scanning line is supplied to the m-th display element through the m-th initialization control line.

In the display device of the embodiment of the present invention including the scan driving circuit according to an embodiment of the present invention, signals necessary for the scanning line, the initialization control line, and the display control line are supplied based on the signal from the scan driving circuit. As a result, the layout area occupied by the signal supplying circuit can be reduced and the circuit cost can be reduced. The value of P or Q may be suitably set in accordance with the specifications of the scan driving circuit and the display device.

In the display device of the present invention, a signal based on an output signal from a shift register constituting a scan driving circuit is supplied to the display control line. In the scan driving circuit of the present invention, the position of the end of the start pulse sequentially shifted by the shift register does not particularly affect the operation of the NAND circuit section. Therefore, the setting of the width of the pulse to be supplied to the display control line can be easily changed without affecting the signal supplied to the scanning line and the initialization control line by an easy means for changing the start pulse inputted to the first- .

At this time, depending on the polarity of the transistor constituting the display element, the scanning signal to the NAND circuit and the output signal from the shift register may be appropriately inverted and supplied. The " signal based on the scanning signal " may be a scanning signal itself or a signal in which the polarity is inverted. Similarly, the " signal based on the output signal from the shift register " may be the output signal itself from the shift register, or may be a signal in which the polarity is inverted.

The scan driving circuit of the present invention can be manufactured by a well-known semiconductor device manufacturing technique. The shift registers constituting the shift register section, the NOR circuit constituting the logic circuit section, and the negative logic circuit may be widely known. The scan driving circuit may be configured as a single circuit or integrated with a display device. For example, when the display element constituting the display device includes a transistor, a scan driving circuit may be formed at the same time in the manufacturing process of the display element.

In the display device of the present invention including the various preferred embodiments described above, a display element having a configuration in which an initialization step is performed based on a signal from the initialization control line, which is scanned by one of the scanning lines, A display element having a configuration in which a display period and a non-display period are switched by a signal on a display control line can be widely used.

In the display device according to the embodiment of the present invention, preferably,

(1-1) a driving circuit including a writing transistor, a driving transistor, and a capacitor,

(1-2) A light emitting portion in which a current flows through the driving transistor.

As the light emitting portion, a light emitting portion that emits light by flowing a current can be widely employed. Examples of the light emitting portion include an organic electroluminescent light emitting portion, an inorganic electroluminescent light emitting portion, an LED light emitting portion, and a semiconductor laser light emitting portion. From the viewpoint of constructing a color display flat panel display device, it is preferable that the light emitting portion is composed of the organic electroluminescence light emitting portion. In the driving circuit (hereinafter, simply referred to as a driving circuit constituting the display element of the present invention) constituting the above-described display element,

In the write transistor,

(a-1) one of the source / drain regions is connected to one of the data lines,

(a-2) the gate electrode is connected to a corresponding one of the scanning lines,

In the driving transistor,

(b-1) one of the source / drain regions is connected to the other one of the source / drain regions of the write transistor to constitute a first node,

In the capacitor portion,

(c-1) a predetermined reference voltage is applied to one end,

(c-2) the gate electrode of the other transistor and the driving transistor are connected to constitute the second node,

The write transistor is controlled by a signal from one of the scan lines.

In the driving circuit constituting the display device according to the embodiment of the present invention,

(d) a first switch circuit portion connected between the second node and the other of the source / drain regions of the driving transistor,

The first switch circuit portion is controlled by a signal from one of the scan lines.

Further, in the driving circuit constituting the display element of the present invention including the above-described preferable configuration,

(e) a second switch circuit portion connected between the second node and a feeder line to which a predetermined initialization voltage is applied,

The second switch circuit portion is controlled by a signal from one of the initialization control lines.

Further, in the driving circuit constituting the display element of the present invention including the above-described preferable configuration,

(f) a third switch circuit part connected between the first node and a feeder line to which a driving voltage is applied,

The third switch circuit portion is controlled by a signal from one of the display control lines.

Further, in the driving circuit constituting the display device of the present invention including the above-described preferred configuration,

(g) a fourth switch circuit portion connected between the other of the source / drain regions of the driving transistor and one end of the light emitting portion,

The fourth switch circuit portion is controlled by a signal from one of the display control lines.

According to another embodiment of the present invention,

(A) a shift register unit comprising a plurality of shift registers, sequentially shifting input start pulses and outputting an output signal from the plurality of shift registers,

(B) a scan driving circuit including a plurality of logic circuits and including a logic circuit portion that operates based on an output signal output from the shift register portion and two or more kinds of enable signals,

Each of the plurality of logic circuits includes:

(a) an input signal input to a corresponding one of the shift registers,

(b) an output signal output from a corresponding one of the shift registers,

(c) at least one enable signal

And outputs a signal based on the signal,

A signal based on one of the output signals output from the corresponding one of the shift registers of the shift register section is supplied to the m-th display element through the m-th display control line,

A signal based on one of the output signals output from the corresponding one of the logic circuits is supplied to the m-th display element via the m-th scan line,

the signal supplied to the (m-1) th scanning line is supplied to the m-th display element through the m-th initialization control line.

In the display device having the above-described drive circuit having the first switch circuit portion to the fourth switch circuit portion,

(a) a predetermined initialization voltage is applied to the second node from the feed line through the second switch circuit section turned on, and then the second switch circuit section is turned off, thereby setting the potential of the second node to a predetermined reference potential Is performed.

(b) Next, by the first switch circuit section in which the second switch circuit section, the third switch circuit section, and the fourth switch circuit section are kept in the off state and the first switch circuit section is in the on state, By applying a video signal to the first node in the data line through the write transistor which is turned on by the corresponding one of the scan lines while electrically connecting the other source / drain region of the drive transistor , And a writing step for changing the potential of the second node from the video signal toward the potential obtained by subtracting the threshold voltage of the driving transistor is performed.

(c) Thereafter, the corresponding one of the scanning lines turns off the writing transistor.

(d) Then, the first switch circuit portion and the second switch circuit portion are maintained in the off state, and the other one of the source / drain regions of the drive transistor and one end of the light emitting portion are electrically connected through the fourth switch circuit portion turned on , And a predetermined drive voltage is applied to the first node from the feed line through the third switch circuit portion turned on to cause current to flow through the drive transistor to the light emitting portion.

As described above, the light emitting portion can be driven.

In the driving circuit constituting the display device according to the embodiment of the present invention, a predetermined reference voltage is applied to one end of the capacitor portion. Thus, the potential at one end of the capacitor portion is maintained during operation of the display device. The value of the predetermined reference voltage is not particularly limited. For example, one end of the capacitance portion may be connected to a power supply line for applying a predetermined voltage to the other end of the light emitting portion, and a predetermined voltage may be applied as a reference voltage.

In the display device according to the embodiment of the present invention including the various preferred embodiments described above, the structure and structure of various wirings such as a scanning line, an initialization control line, a display control line, a data line, a power supply line, . Further, the structure, the structure, the well-known structure, and the structure of the light-emitting portion can be adopted. Specifically, when the light emitting portion is an organic electroluminescent light emitting portion, it can be composed of, for example, an anode electrode, a hole transporting layer, a light emitting layer, an electron transporting layer, a cathode electrode and the like. A signal output circuit connected to the data line, and the like, a structure, a well-known structure, and a structure.

The display device of the present invention may have a configuration of so-called monochrome display, and a configuration in which one pixel is composed of a plurality of sub-pixels, specifically, one pixel includes a red light emitting subpixel, a green light emitting subpixel, And three sub-pixels of the sub-pixel. Further, a set of one or more kinds of subpixels added to these three kinds of subpixels (for example, one set of subpixels emitting white light for luminance enhancement), and a complementary color subpixel One set of light emitting sub-pixels added, one set of light emitting sub-pixels to increase the color reproduction range, and one set of yellow and cyan light emitting sub-pixels to increase the color reproduction range) It is possible.

VGAs 640 and 480, S-VGAs 800 and 600, XGAs 1024 and 768, APRCs 1152 and 900, S-XGAs 1280 and 1024, and U-XGA 1620, and 1200), HD-TVs 1920 and 1080, and Q-XGAs 2048 and 1536, and (1920,1035), (720,480), and (1280,960) But it is not limited to these values. In the case of a monochrome display device, basically, the same number of display elements as the number of pixels are formed in a matrix. In the case of a color display device, basically three times as many display elements as the number of pixels are formed in a matrix. The display elements may be arranged in a stripe pattern or in a delta pattern, for example. The arrangement of the display elements may be suitably set in accordance with the design of the display device.

In the driving circuit constituting the display element of the present invention, the writing transistor and the driving transistor can be constituted by, for example, a p-channel thin film transistor (TFT). At this time, the write transistor may be of n-channel type. The first switch circuit section, the second switch circuit section, the third switch circuit section, and the fourth switch circuit section may be constituted by well-known switching elements such as TFTs. For example, it may be constituted by a p-channel type TFT or an n-channel type TFT.

In the driving circuit constituting the display element of the present invention, the capacitance portion constituting the driving circuit can be composed of, for example, one electrode, the other electrode, and a dielectric layer (insulating layer) sandwiched between these electrodes . The transistor and the capacitor constituting the driving circuit are formed in a certain plane, for example, on a support. When the light-emitting portion is an organic electroluminescence light-emitting portion, the light-emitting portion is formed above the transistor and the capacitor portion constituting the drive circuit through, for example, an interlayer insulating layer. Further, the other one of the source / drain regions of the driving transistor is connected to one end (an anode electrode or the like provided in the light emitting portion) of the light emitting portion through, for example, another transistor or the like. On the other hand, a transistor may be formed on a semiconductor substrate or the like.

The term " one source / drain region " may be used as the source / drain region on the side connected to the power source side in the two source / drain regions of one transistor. The fact that the transistor is in an ON state means a state in which a channel is formed between the source / drain regions. It does not matter whether or not a current flows in the other one of the source / drain regions of one of the transistors. On the other hand, the fact that the transistor is in the OFF state means that no channel is formed between the source / drain regions. The fact that a source / drain region of a transistor is connected to a source / drain region of another transistor includes a form in which a source / drain region of one transistor and a source / drain region of another transistor occupy the same region. In addition, the source / drain region can be formed of an electrically conductive material such as poly silicon or amorphous silicon containing an impurity, but also a metal, an alloy, an electrically conductive particle, a laminated structure thereof, an organic material (electrically conductive polymer) As shown in FIG. In the timing chart used in the following description, the length of the horizontal axis (time length) representing each period is a schematic one and does not indicate the ratio of the time length of each period.

In the display device of the present invention, signals necessary for the scanning line, the initialization control line, and the display control line are supplied based on the signal to the scan driving circuit. As a result, the layout area occupied by the circuit for supplying the signal can be reduced and the circuit cost can be reduced.

In the display device of the present invention, a signal based on an output signal from a shift register constituting a scan driving circuit is supplied to the display control line. In the scan driving circuit of the present invention, the position of the end of the start pulse sequentially shifted by the shift register does not particularly affect the operation of the NAND circuit section. Therefore, the setting of the width of the pulse to be supplied to the display control line can be easily changed without affecting the signal supplied to the scanning line and the initialization control line by an easy means for changing the start pulse inputted to the first- . Thus, according to the design of the display device, the non-display period in the display element can be set appropriately.

1 is a circuit diagram of a scan driving circuit according to a first embodiment of the present invention.
2 is a conceptual block diagram of a display device according to the first embodiment of the present invention including the scan driving circuit shown in Fig.
3 is a schematic timing chart of the scan driving circuit shown in Fig.
Fig. 4 is an equivalent circuit diagram of a driving circuit constituting the display elements of the m-th row and the n-th column in the display device shown in Fig. 2;
5 is a schematic partial cross-sectional view of a part of a display element constituting the display device shown in Fig.
Fig. 6 is a timing chart of the schematic driving of the display elements of the m-th row and the n-th column.
Fig. 7 is an equivalent circuit diagrammatically showing the on / off state of each transistor in the driving circuit constituting the display elements of the m-th row and the n-th column.
8 is a schematic timing chart for explaining the operation of the scan driving circuit of the first embodiment when the timing of the fall of the start pulse is changed.
9 is a timing chart of the schematic driving of the display elements of the m-th row and the n-th column when it is assumed that the start pulse rises between the period of the period T9 and the end of the period T9.
10 is a circuit diagram showing a configuration of a scan driving circuit according to a comparative example of the first embodiment.
11 is a schematic timing chart for explaining the operation of the scan driving circuit shown in Fig. 101 when the start pulse rises between the period T1 and the end and falls between the period T5 and the end.
12 is a schematic timing chart for explaining the operation of the scan driving circuit of the comparative example shown in Fig. 10 when the start pulse falls between the period of the period T9 and the end of the period T9.
13 is a circuit diagram showing the configuration of the scan driving circuit according to the second embodiment of the present invention.
14 is a schematic timing chart showing the configuration of the scan driving circuit of the second embodiment shown in Fig.
15 is a schematic timing chart for explaining the operation of the scan driving circuit of the second embodiment when the timing at which the start pulse falls is changed.
16 is a circuit diagram showing the configuration of a scan driving circuit according to a comparative example of the second embodiment.
Fig. 17 is a schematic timing chart for explaining the operation of the scan driving circuit of the comparative example shown in Fig. 16 when the start pulse rises between the period T1 and the end and falls between the period T9 and the end.
Fig. 18 is a schematic timing chart for explaining the operation of the scan driving circuit of the comparative example shown in Fig. 16 when the start pulse falls between the period of the period T17 and the end of the period T17.
19 is an equivalent circuit diagram of a driving circuit constituting display elements of the m-th row and the n-th column in a display device in which display elements are arranged in a two-dimensional matrix.
20 is an equivalent circuit diagram schematically showing the timing chart of the initialization control line, the scanning line, the signal on the display control line, and the on / off state of the six transistors constituting the driving circuit.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[Example 1]

A scan driver circuit and a display device having the scan driver circuit according to the present invention will be described on the basis of the first embodiment. The display device of the first embodiment is a display device using a display element having a light emitting portion and a drive circuit thereof.

1 is a circuit diagram of the scan driving circuit 110 of the first embodiment. Fig. 2 is a conceptual diagram of the display device 1 of the first embodiment having the scan driving circuit 110 shown in Fig. 3 is a schematic timing chart of the scan driving circuit 110 shown in Fig. 2, 3,..., M), the n-th column (where n = 1, ..., N) of the driving circuit 11 constituting the display element 10. First, the outline of the display device 1 will be described.

As shown in Fig. 2, in the display device 1,

(1) a display element 10 arranged in a two-dimensional matrix,

(2) a scanning line SCL extending in the first direction, an initialization control line AZ for initializing the display element 10, and a display control line CL for controlling the display state / non-display state of the display element 10,

(3) a data line DTL extending in a second direction different from the first direction,

(4) a scan driving circuit 110.

The scan line SCL, the initialization control line AZ, and the display control line CL are connected to the scan driving circuit 110. The data line DTL is connected to the signal output circuit 100. In this case, in Fig. 2, the 3x3 display elements 10 with the display element 10 of the m-th row and the n-th column as the center are shown, but this is merely an example. In Fig. 2, the illustration of the feed lines PS1, PS2, and PS3 shown in Fig. 4 is omitted.

M display elements 10 are arranged in the first direction and N in the second direction different from the first direction. The display device 1 is composed of pixels arranged in (N / 3) x M two-dimensional matrix form. One pixel is composed of three sub-pixels (a red light-emitting sub-pixel emitting red light, a green light emitting sub-pixel emitting green light, and a blue light emitting sub-pixel emitting blue light). The display element 10 constituting each pixel is driven in a line-sequential manner, and the display frame rate is FR (times / second). In other words, the display elements 10 constituting each (N / 3) pixels (N sub-pixels) arranged in the m-th row are simultaneously driven. In other words, in each display element 10 constituting one row, the timings of the light emission / non-light emission are controlled on the row to which they belong.

As shown in Fig. 4, each display element 10 includes a driving circuit 11 having a recording transistor TRW, a driving transistor TRD, and a capacitor C1, and a light emitting portion ELP through which a current flows through the driving transistor TRD Consists of. The light emitting portion ELP is composed of an organic electroluminescence light emitting portion. The display element 10 has a structure in which the driving circuit 11 and the light emitting portion ELP are laminated. The driving circuit 11 further includes the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4, and these transistors will be described later.

In the display element 10 of the m-th row and the n-th column, in the recording transistor TRW, one of the source / drain regions is connected to the data line DTLn, and the gate electrode thereof is connected to the scanning line SCLm. In the driving transistor TRD, one of the source / drain regions is connected to the other one of the source / drain regions of the writing transistor TRW to constitute the first node ND1. One end of the capacitor C1 is connected to the feeder line PS1. In the capacitor C1, a predetermined reference voltage (predetermined drive voltage VCC described later) is applied to one end and the gate electrode of the drive transistor TRD is connected to the other end to constitute a second node ND2 . The write transistor TRW is controlled by a signal from the scan line SCLm.

To the data line DTLn, a video signal (driving signal, luminance signal) VSig for controlling the luminance in the light emitting portion ELP is applied from the signal output circuit 100. Details will be described later.

The driving circuit 11 further includes a first switch circuit portion SW1 connected between the second node ND2 and the other one of the source / drain regions of the driving transistor TRD. The first switch circuit portion SW1 is composed of a first transistor TR1. In the first transistor TR1, one of the source / drain regions is connected to the second node ND2, and the other of the source / drain regions is connected to the other of the source / drain regions of the driving transistor TRD. The gate electrode of the first transistor TR1 is connected to the scanning line SCLm, and the first transistor TR1 is controlled by a signal from the scanning line SCLm.

The driving circuit 11 further includes a second switch circuit portion SW2 connected between the second node ND2 and a feeder line PS3 to which a predetermined initialization voltage VIni to be described later is applied. And the second switch circuit portion SW2 is composed of the second transistor TR2. In the second transistor TR2, one of the source / drain regions is connected to the power supply line PS3, and the other of the source / drain regions is connected to the second node ND2. The gate electrode of the second transistor TR2 is connected to the initialization control line AZm. The second transistor TR2 is controlled by a signal from the initialization control line AZm.

The driving circuit 11 further includes a third switching circuit portion SW3 connected between the first node ND1 and the feeder line PS1 to which the driving voltage VCC is applied. And the third switch circuit portion SW3 is composed of the third transistor TR3. In the third transistor TR3, one of the source / drain regions is connected to the power supply line PS1, and the other of the source / drain regions is connected to the first node ND1. The gate electrode of the third transistor TR3 is connected to the display control line CLm. The third transistor TR3 is controlled by a signal from the display control line CLm.

The driving circuit 11 further includes a fourth switch circuit portion SW4 connected between the other one of the source / drain regions of the driving transistor TRD and one end of the light emitting portion ELP. And the fourth switch circuit portion SW4 is composed of the fourth transistor TR4. In the fourth transistor TR4, one source / drain region is connected to the other one of the source / drain regions of the driving transistor TRD, and the other one of the source / drain regions is connected to one end of the light emitting portion ELP. The gate electrode of the fourth transistor TR4 is connected to the display control line CLm. The fourth transistor TR4 is controlled by a signal from the display control line CLm. The other end (cathode electrode) of the light emitting portion ELP is connected to the power supply line PS2, and a voltage VCat described later is applied. And reference character CEL denotes the parasitic capacitance of the light emitting portion ELP.

The driving transistor TRD is formed of a p-channel type TFT, and the writing transistor TRW is also formed of a p-channel type TFT. Also, the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 are also made of a p-channel TFT. At this time, the write transistor TRW or the like may be of n-channel type. Each of the transistors is described as a depression type, but the present invention is not limited thereto.

The structure and structure of the signal output circuit 100, the scanning line SCL, the initialization control line AZ, the display control line CL, and the data line DTL can be of a well-known structure and structure.

The feed lines PS1, PS2, and PS3 extending in the first direction, such as the scan line SCL, are connected to a power supply unit (not shown). A driving voltage VCC is applied to the feeder line PS1, a voltage VCat is applied to the feeder line PS2, and an initializing voltage VIni is applied to the feeder line PS3. The constitution of the feed lines PS1, PS2, and PS3, the structure thereof, and the well-known structure and structure.

5 is a schematic partial cross-sectional view of a part of the display element 10 constituting the display device 1 shown in Fig. Each transistor and the capacitor C1 constituting the driving circuit 11 of the display element 10 are formed on the support 20 and the light emitting portion ELP is formed by, for example, an interlayer insulating layer 40, And is formed above each of the transistors and the capacitor C1 constituting the driving circuit 11 through the capacitor C1. The light-emitting portion ELP has well-known structures and structures such as, for example, an anode electrode, a hole transporting layer, a light emitting layer, an electron transporting layer, and a cathode electrode. At this time, in Fig. 5, only the driving transistor TRD is shown. Other transistors are hidden from view. The other of the source / drain regions of the driving transistor TRD is connected to the anode electrode provided in the light-emitting portion ELP via the fourth transistor TR4 (not shown), but the fourth transistor TR4 and the anode electrode of the light- The connection is also hidden and invisible.

The driving transistor TRD is composed of a gate electrode 31, a gate insulating layer 32, and a semiconductor layer 33. More specifically, the driving transistor TRD includes one source / drain region 35 and the other source / drain region 36 provided in the semiconductor layer 33, and one source / drain region 35 and one source / And the portion of the semiconductor layer 33 between the other of the source / drain regions 36 is provided with the corresponding channel forming region 34. Other transistors TR1 to TR4 and TRW, not shown, have the same configuration as the driving transistor TRD.

The capacitor portion C1 is composed of an electrode 37, a dielectric layer composed of an extension of the gate insulating layer 32, and an electrode 38. At this time, the connection between the electrode 37 and the gate electrode 31 of the driving transistor TRD and the connection between the electrode 38 and the feeder line PS1 are obscured.

The gate electrode 31, a part of the gate insulating layer 32 and the electrode 37 constituting the capacitor C1 are formed on the support 20. [ The driving transistor TRD and the capacitor portion C1 are covered with the interlayer insulating layer 40 and the anode electrode 51, the hole transporting layer, the light emitting layer, the electron transporting layer, and the cathode electrode 53 are formed on the interlayer insulating layer 40 Emitting portion ELP is provided. Here, in FIG. 5, the hole transporting layer, the light emitting layer, and the electron transporting layer are shown as one layer (52). A second interlayer insulating layer 54 is provided on a portion of the interlayer insulating layer 40 not provided with the light emitting portion ELP and a transparent substrate 21 is formed on the second interlayer insulating layer 54 and the cathode electrode 53. [ And the light emitted from the light emitting layer passes through the substrate 21 and is emitted to the outside. The wiring 39 constituting the cathode electrode 53 and the feed line PS2 are connected through the contact holes 56 and 55 provided in the second interlayer insulating layer 54 and the interlayer insulating layer 40. [

Hereinafter, a manufacturing method of the display device shown in Fig. 5 will be described. First, various wirings such as scanning lines, electrodes constituting capacitors, transistors composed of semiconductor layers, interlayer insulating layers, contact holes and the like are appropriately formed on the support 20 by well-known methods. Then, film formation and patterning are performed by a well-known method to form a light emitting portion ELP arranged in a matrix. Then, the support 21 and the substrate 21 which have undergone the above-described processes are opposed to seal the periphery. Then, the signal output circuit 100 and the scan driving circuit 110 are connected to complete the display device.

Next, the scan driving circuit 110 will be described. At this time, in the description of the operation of the scan driving circuit 110, it is assumed that the scanning signals to be supplied to the scanning lines SCL1 to SCL31 are sequentially generated for the sake of convenience. This also applies to other embodiments.

As shown in Fig. 1, the scan driving circuit 110,

(A) a shift register unit 111,

(B) a logic circuit unit 112. [

In this case, the shift register unit 111 is composed of shift registers SR1 to SRp of P stages (where P is a natural number equal to or larger than 3, and so forth). Sequentially shifts the start pulse STP input to the shift register unit 111, and outputs the output signal ST from each of the stages. The logic circuit unit 112 is based on the output signal ST from the shift register unit 111 and the enable signal (the first enable signal EN1 and the second enable signal EN2 described later in the first embodiment) .

When the output signal of the shift register SRp of the p-th stage (where p = 1, 2, 3, ..., P-1, etc.) is denoted as STp, as shown in Fig. 3, The timing of the start pulse in the output signal STp + 1 of the (p + 1) -th shift register SRp + 1 is located between the start pulse and the end pulse of the (p + 1) -th stage. The shift register unit 111 operates on the basis of the clock signal CK and the start pulse STP so as to satisfy the above condition.

Specifically, the start pulse STP input to the first-stage shift register SR1 is a pulse that rises between the period T1 and the end of the period T1 shown in FIG. 3, and falls between the period of the period T29 and the end. Each period of T1 shown in Fig. 3 or other drawings described later corresponds to one horizontal scanning period (so-called " 1H "). The clock signal CK is a square wave signal whose polarity is inverted every two horizontal scanning periods (2H). The start pulse in the output signal ST1 of the shift register SR1 rises in the period of the period T3 and falls in the end of the period T30. The start pulse in the output signals ST2 and ST3 after the shift register SR2 is a pulse shifted by two horizontal scanning periods in succession.

In addition, between the timing of the start pulse in the output signal STp and the timing of the start pulse in the output signal STp + 1, the first enable signal to the Q-enable signal (Q is a natural number of 2 or more) The same applies to the following). In the first embodiment, Q = 2, and there are sequentially one first enable signal EN1 and one second enable signal EN2. In other words, the first enable signal EN1 and the second enable signal EN2 are signals generated so as to satisfy the above-described conditions, and basically, they are signals on a rectangular wave having the same period, and are signals having different phases.

More specifically, the first enable signal EN1 and the second enable signal EN2 are rectangular-wave signals having two horizontal scanning periods as one cycle. In the first embodiment, these signals are inverted in polarity every one horizontal scanning period, and the first enable signal EN1 and the second enable signal EN2 are out of phase with each other. In this case, in FIG. 3, the high level of the enable signals EN1 and EN2 is shown to be continuous for one horizontal scanning period, but the present invention is not limited to this. A high level signal may be a rectangular wave signal having a period shorter than one horizontal scanning period.

For example, between the timing of the start pulse in the output signal ST1 (i.e., the timing of the period T3) and the timing of the start pulse in the output signal ST2 (i.e., the timing of the period T5) And the second enable signal EN2 in the period T4 are sequentially present. Also between the timing of the start pulse in the output signal ST2 and the timing of the start pulse in the output signal S T3, the first enable signal EN1 and the second enable signal EN2 are respectively 1, do. The same is true after the output signal ST4.

As shown in Fig. 1, the logic circuit unit 112 includes (P-2) x Q number of N logic circuits 113. [ More specifically, the (1, 1) th to (P-2, 2) th NOR circuits 113 are provided.

When the q q enable signal (where q is a natural number arbitrary from 1 to Q, and so forth) is denoted by ENq, as shown in Figs. 1 and 3, the (p ' The product circuit 113 (p 'is an arbitrary natural number from 1 to (P-2), and so on as well) is a signal obtained by inverting the output signal STp' and the output signal STp '+ 1, And generates a scan signal based on the enable signal ENq. More specifically, the output signal STp '+ 1 is inverted and transmitted to the input side of the (p', q) th negative logic AND circuit 113 by the negative logic circuit 114 shown in FIG. The output signal STp 'and the q-enable signal ENq are directly transmitted to the input side of the (p', q) th negative logic product circuit 113.

As shown in Fig. 1, the signal of the (1, 2) th NOR circuit 113 is supplied to the scanning line SCL1 connected to the display element 10 in the first row, The signal of the negative logical product circuit 113 of the second row is supplied to the scanning line SCL2 connected to the display element 10 of the second row. The same applies to other scanning lines SCL. In other words, the signal of the (p ', q) -th NAND circuit 113 (except for the case of p' = 1 and q = 1) is supplied to the scanning line SCLm connected to the display element 10 of the (p'-1) + q-1.

In the display device 10 in which a signal based on the scan signal from the (p ', q) th negative logic product circuit 113 is supplied via the scan line SCLm, (Q '' is a natural number of any one of 1 to Q, hereinafter also referred to as " q '") in the case of q = 1 from the control line AZm (Q '' = 1 to (q-1)) is supplied to the (p ', q') th negative logic product circuit 113 , The same applies to the following).

More specifically, in the first embodiment, in the display device 10 in which a signal based on the scanning signal from the (p ', q) th negative logic circuit 113 is supplied through the scanning line SCLm, A signal based on the scanning signal from the (p'-1, Q) th negative logic AND circuit 113 is supplied from the initialization control line AZm connected to the display element 10 when q = 1 and q > 1, a signal based on the scanning signal from the (p ', q-1) -th N AND circuit 113 is supplied.

A signal based on the output signal STp '+ 1 from the shift register SRp' + 1 at the (p '+ 1) -th stage is supplied to the display control line CLm connected to the display element 10, And a signal based on the output signal STp '+ 2 from the (p' + 2) -th shift register SRp '+ 2 in the case of q> 1 is supplied. At this time, since the third transistor TR3 and the fourth transistor TR4 shown in Fig. 4 are p-channel type, a signal is supplied to the display control line CLm through the negative logic circuit 115. [

Will be described in more detail with reference to Fig. For example, when a signal based on the scanning signal from the (5, 1) -th NOR circuit 113 is paid attention to the display element 10 supplied through the scanning line SCL8, the signal connected to the display element 10 A signal based on the scanning signal from the (4, 2) -th N AND circuit 113 is supplied to the initialization control line AZ8. The display control line CL8 connected to the display element 10 is supplied with a signal based on the output signal ST6 from the sixth-stage shift register SR6. When the signal based on the scanning signal from the (5, 2) -th NOR circuit 113 is paid attention to the display element 10 supplied through the scanning line SCL9, the initialization A signal based on the scanning signal from the (5, 1) -th NAND circuit 113 is supplied to the control line AZ9. The display control line CL9 connected to the display element 10 is supplied with a signal based on the output signal ST7 from the seventh shift register SR7.

Subsequently, the signal of the (p ', q) th negative logic product circuit 113 is supplied to the display device 1 with respect to the operation of the m < th > row and the n & Will be described. The display element 10 is hereinafter referred to as the (n, m) th display element 10 or the (n, m) th sub-pixel. The horizontal scanning period (more specifically, the m-th horizontal scanning period in the current display frame) of each display element 10 arranged in the m-th row is hereinafter referred to as the m-th horizontal scanning Term. The same applies to the other embodiments described later.

Fig. 6 is a timing chart of schematically driving the display device 10 of the m-th row and the n-th column. 7 is an equivalent circuit diagrammatically showing on / off states of each transistor in the driving circuit 11 constituting the display device 10 of the m-th row and the n-th column.

6, for example, assuming that p '= 5 and q = 1 and m = 8, it is assumed that AZ8, SCL8 and CL8 shown in Fig. 3 Referring to the timing chart of Fig.

In the light emitting state of the display element 10, the driving transistor TRD is driven to flow the drain current Ids in accordance with the following equation (5).

Ids = k 占 占 (Vgs-Vth) ² (5)

At this time, mu is an effective mobility, Vgs is a potential difference between the gate electrode and the source region of the driving transistor TRD, and k is a constant.

Here, the constant k is given by equation (6).

k = (1/2) (W / L) Cox (6)

In this case, L is the channel length, W is the channel width, and Cox is (dielectric constant of the gate insulating layer) x (dielectric constant of vacuum) / (thickness of the gate insulating layer).

In the light emitting state of the display element 10, one of the source / drain regions of the driving transistor TRD functions as a source region and the other of the source / drain regions functions as a drain region. For convenience of explanation, in the following description, one of the source / drain regions of the driving transistor TRD is simply referred to as a source region and the other of the source / drain regions is referred to simply as a drain region.

In the description of Embodiment 1 and Embodiment 2 described later, the values of the voltage or potential are as follows. However, this is merely a value for explanation, and is not limited to these values.

VSig: a video signal for controlling the luminance in the light emitting portion ELP

... 0 volts (highest luminance) to 8 volts (lowest luminance)

VCC: drive voltage

... 10 volts

VIni: initialization voltage for initializing the potential of the second node ND2

... -4 volts

Vth: threshold voltage of the driving transistor TRD

... 2 volts

VCat: Voltage applied to the feeder line PS2

... -10 volts

[Period-TP (1) -2] (see Figs. 6 and 7a)

[Period TP (1) -2] is a period in which the (n, m) -th display element 10 is in a light emitting state corresponding to the previously recorded video signal VSig. For example, in the case of m = 8, this period TP (1) -2 corresponds to a period up to the end of the period T8 shown in Fig. The initialization control line AZ8 and the scanning line SCL8 are at a high level, and the light emission control line CL8 is at a low level.

Therefore, the writing transistor TRW, the first transistor TR1, and the second transistor TR2 are off. The third transistor TR3 and the fourth transistor TR4 are on. The drain current I'ds based on the formula (5) described below flows in the light emitting portion ELP of the display element 10 constituting the (n, m) th sub-pixel, The luminance of the display element 10 constituting the sub-pixel of the pixel is a value corresponding to the drain current I'ds.

[Period-TP (1) -1] (see Figs. 6 and 7b)

The (n, m) -th display element 10 is in a non-light emitting state from [period-TP (1) -1] to [period-TP (1) 2] described later. The end of [period-TP (1) -1] is the end of the (m-2) -th horizontal scanning period in the current display frame. For example, in the case of m = 8, this [period-TP (1) -1] corresponds to the period T9 shown in Fig. The initialization control line AZ8 and the scanning line SCL8 maintain the high level, and the light emission control line CL8 becomes the high level.

Therefore, the writing transistor TRW, the first transistor TR1, and the second transistor TR2 are maintained in the off state. The third transistor TR3 and the fourth transistor TR4 are turned off from the on state. As a result, the first node ND1 is disconnected from the power supply line PS1, and the light emitting portion ELP and the driving transistor TRD are separated from each other. Therefore, the current does not flow in the light emitting portion ELP and is in a non-light emitting state.

[Period-TP (1) 0] (see Figs. 6 and 7c)

[Period-TP (1) 0] is the (m-1) -th horizontal scanning period in the current display frame. For example, in the case of m = 8, this [period-TP (1) 0] corresponds to the period T10 shown in Fig. The scan line SCL8 and the emission control line CL8 maintain the high level. The initialization control line AZ8 becomes a high level at the end of the period T10 after becoming low level.

The first switch circuit portion SW1, the third switch circuit portion SW3, and the fourth switch circuit portion SW4 are kept in the OFF state and the second switch circuit portion SW2 is turned on in the [period-TP (1) 0] The initialization voltage VIni is applied to the second node ND2, and then the second switch circuit SW2 is turned off. In this manner, an initialization step of setting the potential of the second node ND2 to a predetermined reference potential is performed.

That is, the write transistor TRW, the first transistor TR1, the third transistor TR3, and the fourth transistor TR4 maintain the off state. The second transistor TR2 is turned on from the off state and a predetermined initializing voltage VIni is applied from the feeder line PS3 through the second transistor TR2 turned on to the second node ND2. Then, at the end of [period-TP (1) 0], the second transistor TR2 is turned off. The drive voltage VCC is applied to one end of the capacitor C1 and the potential of the second node ND2 is set to a predetermined reference potential (-4 volts) by the initialization voltage VIni in a state where the potential of one end of the capacitor C1 is maintained .

[Period-TP (1) 1] (see Figs. 6 and 7d)

[Period-TP (1) 1] is the m-th horizontal scanning period in the current display frame. For example, in the case of m = 8, this period TP (1) 1 corresponds to the period T11 shown in Fig. The initialization control line AZ8 and the emission control line CL8 are at the high level, and the scanning line SCL8 is at the low level.

The OFF state of the second switch circuit portion SW2, the third switch circuit portion SW3, and the fourth switch circuit portion SW4 is maintained in the [period-TP (1) 1], the first switch circuit portion SW1 is turned on, In the state where the second node ND2 and the other one of the source / drain regions of the driving transistor TRD are electrically connected by the first switching circuit portion SW1, the writing transistor TRW turned on by the signal from the scanning line SC Lm, A video signal VSig is applied from the data line DTLn to the first node ND1 to change the potential of the second node ND2 from the video signal VSig toward the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD from the video signal VSig.

That is, the OFF state of the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 is maintained. The recording transistor TRW and the first transistor TR1 are turned on by the signal from the scanning line SCLm. Then, the second node ND2 is electrically connected to the other one of the source / drain regions of the driving transistor TRD through the first transistor TR1 turned on. In addition, the video signal VSig is applied from the data line DTLn to the first node ND1 through the write transistor TRW turned on by the signal from the scan line SCLm. As a result, the potential of the second node ND2 changes from the video signal VSig toward the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD.

That is, since the potential of the second node ND2 is initialized so that the driving transistor TRD is turned on in the period of [period-TP (1) 1] by the above-described initialization process, The potential of the video signal VSig applied to the node ND1 is changed. However, when the potential difference between the gate electrode of the driving transistor TRD and one of the source / drain regions reaches Vth, the driving transistor TRD is turned off. In this state, the potential of the second node ND2 is approximately (VSig-Vth). The potential VND2 of the second node ND2 is expressed by equation (7).

Vth2? VSig-Vth?

Before the (m + 1) -th horizontal scanning period starts, the writing transistor TRW and the first transistor TR1 are turned off by a signal from the scanning line SCLm.

[Period-TP (1) 2] (see Figs. 6 and 7E)

[Period TP (1) 2] is a period until the light emitting period starts after the writing process, and the (n, m) th display element 10 is in a non-light emitting state. For example, in the case of m = 8, this [period-TP (1) 2] corresponds to the period T12 shown in Fig. The scanning line SCL8 is at the high level, and the initialization control line AZ8 and the emission control line CL8 are maintained at the high level.

That is, the writing transistor TRW and the first transistor TR1 are turned off, and the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 are kept off. The first node ND1 is kept separated from the power supply line PS1 and the light emitting portion ELP and the driving transistor TRD are maintained in a separated state. The potential VND2 of the second node N D2 satisfies the equation (7).

[Period-TP (1) 3] (see Figs. 6 and 7f)

In the [period-TP (1) 3], the first switch circuit portion SW1 and the second switch circuit portion SW2 are maintained in the OFF state, and the other source / The drain region and one end of the light emitting portion ELP are electrically connected and a predetermined drive voltage VCC is applied from the feed line PS1 to the first node ND1 through the third switch circuit portion SW3 turned on to emit a current through the drive transistor TRD And the light emitting portion ELP is driven by flowing the light to the sub-ELP.

For example, in the case of m = 8, this period TP (1) 3 corresponds to the period from the period T13 shown in FIG. 3 to the end of the period T8 in the next frame. The initializing control line AZ8 and the scanning line SCL8 maintain the high level, and the display control line CL8 becomes the low level.

That is, the off state of the first transistor TR1 and the second transistor TR2 is maintained, and the third transistor TR3 and the fourth transistor TR4 are turned on from the off state by the signal from the display control line CLm. A predetermined driving voltage VCC is applied to the first node ND1 through the third transistor TR3 turned on. Further, the other of the source / drain regions of the driving transistor TRD and the one end of the light emitting portion ELP are electrically connected through the fourth transistor TR4 turned on. Therefore, the light emitting portion ELP is driven by flowing a current through the driving transistor TRD to the light emitting portion ELP.

From the equation (7), the following equation (8) is obtained.

Vgs? VCC- (VSig-Vth) (8)

Therefore, equation (5) can be transformed into equation (9).

Ids = k 占 占 (Vgs-Vth) ²

= k · μ · (VCC-VSig) ² (9)

Therefore, the current Ids flowing in the light emitting portion ELP is proportional to the square of the potential difference between VCC and VSig. In other words, the current Ids flowing through the light emitting portion ELP does not depend on the threshold voltage Vth of the driving transistor TRD. In other words, the amount of emitted light (luminance) of the light emitting portion ELP is not affected by the threshold voltage Vth of the driving transistor TRD. The luminance of the (n, m) th display element 10 is a value corresponding to the current Ids.

The light emission state of the light emitting portion ELP is continued until a period corresponding to the end of [period-TP (1) -2] in the next frame.

Thus, the operation of light emission of the display element 10 constituting the (n, m) -th sub-pixel is completed.

The length of the non-emission period is the same regardless of the value of m. However, the ratio of [period-TP (1) -1] and [period-TP (1) 2] in the non-emission period is changed by the value of m. The same applies to the other embodiments described later. For example, in the timing chart of the scanning line SCL7 or the like in Fig. 3, [period-TP (1) -1] does not exist. At this time, even if there is no [period-TP (1) -1], there is no particular problem in the operation of the display device.

The scan driving circuit 110 of the first embodiment is an integrated circuit that supplies signals to the scanning line SCL, the initialization control line AZ, and the display control line CL. As a result, the layout area occupied by the circuit can be reduced and the circuit cost can be reduced.

In the display device 1 having the scan driving circuit 110 of the first embodiment, even if the start pulse STP shown in Fig. 3 is changed, the signals applied to the initialization control line AZ and the scan line SCL are not affected. This will be described below with reference to Figs. 3, 8, and 9. Fig.

In Fig. 3, the start pulse STP rises between the period T1 and the end, and falls between the period T29 and the end. 8 is a schematic timing chart of the scan driving circuit 110 when the timing at which the start pulse STP falls is changed. Concretely, for example, it is assumed that the start pulse STP falls between the period of the period T9 and the end of the period T9.

As described above, in the scan driving circuit 110, the (p ', q) th NOR circuit outputs the signal obtained by inverting the output signal STp' and the output signal STp '+ 1, The scan signal is generated based on the enable signal ENq. Therefore, even if the fall of the start pulse STP is changed, the signals applied to the initialization control line AZ and the scan line SCL are as shown in Fig. In Fig. 10, only the waveform supplied to the display control line CL is changed, as is clear from comparison between Fig. 3 and Fig.

Fig. 9 corresponds to Fig. 6, and is a timing chart of the schematic driving of the display device 10 of the m-th row and the n-th column when the start pulse STP falls between the period of the period T9 and the end of the period T9. In the display device 1, the period during which the display control line CL is at the high level is the non-emission period shown in Fig. 6 or Fig. For example, when m = 8, the non-emission period in FIG. 6 was the period T9 to the period T12. On the other hand, in FIG. 9, the non-emission period is the period T'21 to the period T12. In this way, the setting of the width of the pulse supplied to the display control line CL can be easily changed without affecting the signal supplied to the scanning line SCL or the initialization control line AZ by an easy method of changing the width of the start pulse STP have.

This will be further described in comparison with the comparative example. 10 is a circuit diagram of the scan driving circuit 120 of the comparative example. In the scan driving circuit 120, the configuration of the logic circuit portion 122 is different from the logic circuit portion 112 of the scan driving circuit 110 of the first embodiment. The configuration of the shift register unit 121 of the scan driving circuit 120 is the same as that of the shift register unit 111 of the scan driving circuit 110. [

More specifically, in the scan driving circuit 120 of the comparative example, the negation logic circuits 114 and 115 shown in Fig. 1 are omitted. In the display element 10 in which a signal based on the scan signal from the (p ', q) th negative logic product circuit 123 is supplied via the scan line SCL, the display connected to the display element 10 The signal based on the output signal STp 'from the p'th-stage shift register SRp' is supplied from the control line CL in the case of q = 1, and in the case of q> 1, the (p '+ 1) A signal based on the output signal STp '+ 1 from SRp' + 1 is supplied.

In the scan driving circuit 120 having the above-described configuration, the (p ', q) th NOR circuit 123 outputs the output signal STp', the output signal STp '+ 1, and the q- The scan signal is generated based on ENq. Therefore, when there are a plurality of q enable signals ENq in the overlap period of the start pulse of the output signal STp 'and the start pulse of the output signal STp' + 1, a plurality of scan signals are generated in the overlap period. Therefore, when the start pulse STP rises between the period T1 and the end, it is necessary to set the start pulse STP to fall between the period of the period T5 and the end of the period T5.

11 is a timing chart of the scan driving circuit 120 shown in Fig. 10 when the start pulse STP rises between the period T1 and the end and falls between the period T5 and the end. 3, signals as shown in Fig. 3 are supplied to the initialization control line AZ, the scanning line SCL, and the display control line CL although there is a difference in phase.

12 shows a timing chart of the scan driving circuit 120 when, for example, the start pulse STP falls between the period of the period T9 and the end of the period T9. In this case, a plurality of scan signals are generated in the overlapping period of the start pulse of the output signal STp 'and the start pulse of the output signal STp' + 1. In this way, in the scan driving circuit 120 of the comparative example, if the width of the start pulse STP is changed, the signal supplied to the scanning line SCL and the initialization control line AZ affects the operation of the display device.

Thus, in the scan driving circuit 120 of the comparative example, the width of the pulse supplied to the display control line CL can not be changed by changing the width of the start pulse STP. The scan driving circuit 110 of the first embodiment has no such limitation.

[Example 2]

Embodiment 2 also relates to a scan driver circuit of the present invention and a display device having the same. As shown in Fig. 2, the display device 2 of the second embodiment has the same configuration as the display device 1 of the first embodiment except that the scan driving circuit 210 is different. Therefore, in the second embodiment, the description of the display device 2 is omitted for the sake of simplicity.

13 is a circuit diagram of the scan driving circuit 210 of the second embodiment. Fig. 14 is a schematic timing chart of the scan driving circuit 210 shown in Fig.

In the scan driving circuit 110 of the first embodiment, the first enable signal EN1 and the second enable signal EN2 are used. In the scan driving circuit 210 of the second embodiment, the third enable signal EN3 and the fourth enable signal EN4 are used in addition to these. As a result, the number of constituent stages of the shift register section constituting the scan driving circuit can be reduced as compared with the scan driving circuit 110 of the second embodiment.

As shown in Fig. 13, the scan driving circuit 210,

(A) a shift register unit 211,

(B) a logic circuit unit 212. [

In this case, the shift register unit 211 is composed of a shift register SR in the P stage. Sequentially shifts the start pulse STP input to the shift register unit 211, and outputs the output signal ST from each of the stages. The logic circuit unit 212 outputs the output signal ST from the shift register unit 211 and the enable signal (in the second embodiment, the first enable signal EN1, the second enable signal EN2, the third The enable signal EN3, and the fourth enable signal EN4).

When the output signal of the p-th stage shift register SRp is represented by STp, as shown in Fig. 14, the output signal of the (p + 1) -th shift register SRp + 1, the timing of the start pulse in the output signal STp + 1 is located. The shift register unit 211 operates on the basis of the clock signal CK and the start pulse S TP so as to satisfy the above condition.

The start pulse STP is a pulse that rises between the period T1 and the end of the period T1 shown in Fig. 14, for example, falls between the period of the period T24 and the end of the period T24.

In Embodiment 1, the clock signal CK was a square wave signal whose polarity was inverted every two horizontal scanning periods. On the other hand, in the second embodiment, the clock signal CK is a square wave signal whose polarity is inverted every four horizontal scanning periods. The start pulse in the output signal ST1 of the shift register SR1 rises in the period T3 and descends in the end of the period T25. The start pulse in the output signals ST2, ST3 and the like subsequent to the shift register SR2 becomes a pulse shifted sequentially by four horizontal scanning periods.

In addition, between the timing of the start pulse in the output signal STp and the timing of the start pulse in the output signal STp + 1, there exist one each of the first enable signal to the Q-enable signal in succession . In the second embodiment, Q = 4, and the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, and the fourth enable signal EN4 are sequentially present. In other words, the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, and the fourth enable signal EN4 are signals generated so as to satisfy the above conditions, and basically the same It is a square wave signal of a period and a signal of a different phase.

Specifically, the first enable signal EN1 is a square wave signal having four horizontal scanning periods as one cycle. The second enable signal EN2 is a signal whose phase is delayed by one horizontal scanning period with respect to the first enable signal EN1. The third enable signal EN3 is a signal whose phase is delayed by two horizontal scanning periods with respect to the first enable signal EN1. The fourth enable signal EN4 is a signal whose phase is delayed by three horizontal scanning periods with respect to the first enable signal EN1. At this time, also in Fig. 14, the high level of the enable signals EN1, EN2, EN3, and EN4 is shown to be continued for one horizontal scanning period, but the present invention is not limited to this. A high-level signal may be a rectangular-wave signal having a period shorter than one horizontal scanning period.

For example, between the timing of the start pulse in the output signal ST1 (i.e., the timing of the period T2) and the timing of the start pulse in the output signal ST2 (i.e., the timing of the period T7) The second enable signal EN2 in the period T4, the third enable signal EN3 in the period T5, and the fourth enable signal EN4 in the period T6 are each 1, exist. Similarly, in the period between the timing of the start pulse in the output signal ST2 and the timing of the start pulse in the output signal ST3, the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, And one enable signal EN4 are sequentially present. The same is true after the output signal ST4.

As shown in Fig. 13, the logic circuit unit 212 includes (P-2) x Q number of N logic circuits 213. [ More specifically, the (1, 1) th to (P-2, 4) th NOR circuits 213 are provided.

13 and 14, the (p ', q) th NOR circuit 213 outputs the output signal STp' and the output signal STp '+ 1 And a scan enable signal ENq based on the enable signal ENq. More specifically, the output signal STp '+ 1 is inverted and transmitted to the input side of the (p', q) th negative logic circuit 213 by the negative logic circuit 214 shown in Fig. The output signal STp 'and the q-enable signal ENq are directly transmitted to the input side of the (p', q) th NOR circuit 213.

The signal of the (1, 2) th NOR circuit 213 is supplied to the scanning line SCL1 connected to the display element 10 of the first row, Th negative logic product circuit 213 is supplied to the scanning line SCL2 connected to the display element 10 of the second row. The same applies to other scanning lines SCL. In other words, as described in the first embodiment, the signal of the (p ', q) th NAND circuit 213 (except for the case of p' = 1 and q = 1) is supplied to the scanning line SCLm connected to the display element 10 of the m-th row (where m = Q x (p'-1) + q-1).

In the display device 10 in which a signal based on the scanning signal from the (p ', q) th negative logic product circuit 213 is supplied via the scanning line SCLm, the initialization A signal based on the scan signal from the (p'- 1, q ') N AND circuit 213 is supplied from the control line AZm when q = 1, Quot ;, q ") < / RTI > negative logic product circuit 213 is supplied.

More specifically, in the display element 10 in which a signal based on the scanning signal from the (p ', q) th negative logic circuit 213 is supplied through the scanning line SCLm, A signal based on the scanning signal from the (p'-1, Q) th negative logic circuit 213 is supplied from the connected initialization control line AZm when q = 1, and when q> 1 a signal based on the scanning signal from the (p ', q-1) -th NAND circuit 213 is supplied.

A signal based on the output signal STp '+ 1 from the shift register SRp' + 1 at the (p '+ 1) -th stage is supplied to the display control line CLm connected to the display element 10, And a signal based on the output signal STp '+ 2 from the (p' + 2) -th shift register SRp '+ 2 in the case of q> 1 is supplied. Since the third transistor TR3 and the fourth transistor TR4 shown in Fig. 4 are p-channel type, the signal is supplied to the display control line CLm through the negative logic circuit 215, as described in the first embodiment.

This will be described more specifically with reference to FIG. For example, if a signal based on the scanning signal from the (3, 1) -th NOR circuit 213 is paid attention to the display element 10 supplied through the scanning line SCL8, A signal based on the scanning signal from the (2,4) th negative logic circuit 213 is supplied to the initialization control line AZ8. The display control line CL8 connected to the display element 10 is supplied with a signal based on the output signal ST4 from the fourth-stage shift register SR4. When a signal based on the scanning signal from the (3, 2) -th NOR circuit 213 is focused on the display element 10 supplied through the scanning line SCL9, the initialization A signal based on the scanning signal from the (3, 1) -th negative AND circuit 213 is supplied to the control line AZ9. A signal based on the output signal ST5 from the fifth-stage shift register SR5 is supplied to the display control line CL9 connected to the display element 10. [

As described in the first embodiment, in the scan driving circuit 210 of the second embodiment, even if the start pulse STP shown in Fig. 14 is changed, the signals applied to the initialization control line AZ and the scanning line SCL are not affected . 15 is a schematic timing chart of the scan driving circuit 210 when the timing at which the start pulse STP falls is changed. Concretely, for example, it is assumed that the start pulse STP falls between the period of the period T9 and the end of the period T9. As apparent from comparison between Fig. 14 and Fig. 15, in Fig. 15, only the waveform supplied to the display control line CL is changed.

16 is a circuit diagram of the scan driving circuit 220 of the comparative example. The scan driving circuit 220 corresponds to the scanning driving circuit 120 of the comparative example described in the first embodiment. In the scan driving circuit 220, the configuration of the logic circuit portion 222 is different from that of the logic circuit portion 212 of the scan driving circuit 210 of the second embodiment. The configuration of the shift register unit 221 of the scan driving circuit 220 is the same as that of the shift register unit 211 of the scan driving circuit 210. [

As described in the first embodiment, in the scan driving circuit 220 of the comparative example, the negation logic circuits 214 and 215 shown in Fig. 13 are omitted. In the display device 10 in which a signal based on the scan signal from the (p ', q) th negative logic product circuit 223 is supplied via the scan line SCL, the display connected to the display device 10 The signal based on the output signal STp 'from the p'th-stage shift register SRp' is supplied from the control line CL in the case of q = 1, and in the case of q> 1, the (p '+ 1) A signal based on the output signal STp '+ 1 from SRp' + 1 is supplied.

As described in the first embodiment, in the scan driving circuit 220 having the above-described configuration, the (p ', q) th NOR circuit 223 outputs the output signal STp' and the output signal STp '+ 1 , And the enable signal ENq. Therefore, when there are a plurality of q enable signals ENq in the overlap period of the start pulse of the output signal STp 'and the start pulse of the output signal STp' + 1, a plurality of scan signals are generated in the overlap period. Therefore, when the start pulse STP rises between the period T1 and the end, it is necessary to set the start pulse STP to fall between the period of the period T9 and the end of the period T9.

Fig. 17 is a timing chart of the scan driving circuit 220 shown in Fig. 16 when the start pulse STP rises between the period T1 and the end and falls between the period T9 and the end. As is clear from the timing chart of Fig. 14, signals similar to those in Fig. 3 are supplied to the initialization control line AZ, the scanning line SCL, and the display control line CL although there is a difference in phase.

18 shows a timing chart of the scan driving circuit 220 when, for example, the start pulse STP falls between the period of the period T17 and the end of the period T17. In this case, a plurality of scan signals are generated in the overlapping period of the start pulse of the output signal STp 'and the start pulse of the output signal STp' + 1. In this way, in the scan driving circuit 220 of the comparative example, if the width of the start pulse STP is changed, the signal supplied to the scanning line SCL and the initialization control line AZ affects the operation of the display device.

The present invention has been described based on the preferred embodiments. However, the present invention is not limited to these embodiments. The steps in the configuration, structure, and operation of the display device of the scan driving circuit, the display device, and the various elements constituting the display device described in the embodiment are illustrative and can be changed appropriately.

For example, when the third transistor TR3 and the fourth transistor TR4 are of n-channel type in the driving circuit 11 constituting the display device 10 shown in Fig. 4, the negative logic circuit 115) and the negative logic circuit 215 shown in FIG. 13 are not necessary. In this way, the polarity of the signal to the scan driving circuit can be suitably set in accordance with the configuration of the display element and supplied to the scanning line, initialization control line, and display control line.

The present invention includes the subject matter of Japanese Patent JP 2008-149171 filed with the Japanese Patent Office on June 6, 2008, the entire contents of which are incorporated herein by reference.

It will be understood by those skilled in the art that various changes, combinations, subcombinations, and alterations may be made depending on design requirements or other elements, as long as they are within the scope of the appended claims or their equivalents.

110: scan driving circuit
111:
112:

Claims (3)

As a display device,
A plurality of pixel circuits each including a writing transistor, a driving transistor, a first switching transistor, a capacitor, and a light emitting portion; And
A peripheral circuit configured to receive an input pulse and output a first scan signal and a second scan signal,
/ RTI >
The peripheral circuit is disposed on the first side of the plurality of pixel circuits,
Wherein the write transistor is configured to supply a data potential to the capacitor through the write transistor and the drive transistor,
Wherein the driving transistor is configured to supply a driving current from a voltage line to the light emitting portion via the driving transistor and the first switching transistor, the magnitude of the driving current corresponds to the data potential,
Wherein the first switching transistor is configured to switch between a display state and a non-display state in accordance with the second scan signal,
The writing transistor is configured to be controlled by the first scanning signal supplied from the first side of the plurality of pixel circuits,
The first switching transistor is configured to be controlled by the second scanning signal supplied from the first side of the plurality of pixel circuits,
The duration of the display state is variably controlled by changing the width of the input pulse,
And the second scanning signal is applied to the first row of the plurality of pixel circuits and the second row of the plurality of pixel circuits. The method according to claim 1,
Wherein the light emitting portion is provided on a first insulating layer that has an anode electrode, a light emitting layer, and a cathode electrode and covers the plurality of pixel circuits,
Wherein the cathode electrode is provided on a second insulating layer disposed on the first insulating layer and is connected to a second power supply line through a first contact and a second contact. The method according to claim 1,
Wherein the width change of the input pulse does not affect the first scanning signal.

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