KR101654323B1 - Liquid Crystal Display device and Method for Repairing the same - Google Patents

Abstract

A liquid crystal display device and a compensation method thereof are disclosed.

A liquid crystal display according to the present invention includes a liquid crystal display panel in which a plurality of gate lines and a plurality of data lines cross each other, a data driver for driving the plurality of data lines, A gate driver having a plurality of circuit sections for sequentially supplying an output signal to the plurality of gate lines; and a plurality of circuit sections each including a clock signal input line to which a clock signal is inputted, And a plurality of transistors driven by the clock signal and the start pulse, wherein one of the clock signal input line and the start pulse input line is connected to the first And has a parallel structure.

A start signal Vst input line Vst_Line, a clock signal input line CLK_line,

Description

[0001] The present invention relates to a liquid crystal display device and a compensation method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and more particularly to a liquid crystal display device in which a GIP circuit portion in which a short failure occurs due to static electricity generated during a process (TFT process and cell process) To a liquid crystal display device capable of preventing defects and a compensation method therefor.

2. Description of the Related Art In general, devices for displaying an image by driving pixels arranged in an active matrix form, such as a liquid crystal display or an organic electroluminescent device, have been actively studied.

Particularly, a liquid crystal display device is a display device which can display a desired image by individually supplying data signals according to image information to pixels arranged in an active matrix form and adjusting the light transmittance of the liquid crystal layer. Such a liquid crystal display device includes a liquid crystal display panel in which pixels are arranged in a matrix form and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, gate lines and data lines are arranged to cross each other, and pixel regions are located at the intersections of the gate lines and the data lines. In such a pixel region, a thin film transistor (TFT) as a switching element and a pixel electrode connected to the thin film transistor (TFT) are provided. At this time, the gate electrode of the thin film transistor (TFT) is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to the pixel electrode.

The driving circuit includes a gate driver for sequentially supplying a scan signal to the gate lines, and a data driver for supplying a data signal to the data lines. The gate driver sequentially supplies a scan signal to the gate lines so that the pixels are selected one by one on the liquid crystal display panel. The data driver supplies a data signal to the data lines each time gate lines are sequentially selected. Accordingly, the liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal layer by an electric field applied between the pixel electrode and the common electrode according to a video signal applied to each pixel.

Recently, a built-in liquid crystal display device in which the gate driver and the data driver are built on the liquid crystal display panel has been developed to lower the manufacturing cost. In such a built-in liquid crystal display device, when the thin film transistor is manufactured, the gate driver is manufactured at the same time. At this time, the data driver may or may not be embedded.

The gate driver built in the liquid crystal display panel includes a plurality of circuit parts corresponding one-to-one with the gate lines. The plurality of circuit portions include a plurality of transistors TR formed in the same process as a thin film transistor (TFT) formed on the liquid crystal display panel. The plurality of circuit units are electrically connected to the input lines to which the clock signal CLK, the start signal Vst, and the gate voltages VGH and VGL are input.

On the other hand, the plurality of circuit sections are designed such that the output signal of the (n-2) th circuit section becomes the start signal (Vst) of the nth circuit section. Thus, the input line to which the start signal Vst of each circuit section is inputted and the input line to which the clock signal CLK is input are formed in the circuit section in an overlapping manner. At this time, the input line to which the start signal Vst is input and the input line to which the clock signal CLK is input are formed of different metals.

Static electricity is generated during the manufacturing process of the liquid crystal display panel (TFT process or Cell process), and the static electricity is short-circuited at the overlapping start signal (Vst) input line and the clock signal (CLK) cause. If a short phenomenon occurs in the overlapping portion of the start signal (Vst) input line and the clock signal (CLK) input line, the short circuit phenomenon is caused by the short circuit phenomenon If it does not occur, it will lead to leakage and lead to quality deterioration.

In the present invention, a start signal (Vst) input line having a parallel structure is formed in each of a plurality of circuit portions in a gate driver, and a start signal (Vst) input line and a clock signal (CLK) And it is an object of the present invention to provide a liquid crystal display device capable of performing repair even if the overlapped portion is shorted due to static electricity generated, and a compensation method thereof.

A liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel in which a plurality of gate lines and a plurality of data lines cross each other, a data driver for driving the plurality of data lines, And a gate driver having a plurality of circuit units which are sequentially shifted to the plurality of gate lines and supply an output signal to the plurality of gate lines sequentially, and each of the circuit units includes a clock signal input line to which a clock signal is inputted, A start pulse input line partially overlapped with a signal input line and a plurality of transistors driven by the clock signal and a start pulse, wherein one of the clock signal input line and the start pulse input line is overlapped And a parallel structure is formed in the region.

A method of compensating a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel in which a gate line and a data line are arranged and a liquid crystal display panel that is built in the liquid crystal display panel and sequentially shifts the start pulse to supply an output signal to the gate line A clock signal input line to which a clock signal is input and a parallel structure in a region where the start pulse is input and which is partially parallel to the clock signal input line and partially overlapped with the clock signal input line in an area not overlapped with the clock signal input line, And a gate driver having a plurality of circuit portions including a start pulse input line divided into first and second start pulse input lines electrically connected to the first and second start pulse input lines, A start pulse input line of any one of the pulse input lines and the clock signal input Disconnecting the first and second start pulse input lines by cutting off the left and right sides of the start pulse input line when a line break occurs in an area where the lines overlap and electrically disconnecting the disconnected clock signal input line with a laser .

The liquid crystal display device according to the present invention is provided in each of a plurality of circuit parts in the built-in gate driver so that any one of a clock signal (CLK) input line and a start signal (Vst) It is possible to repair even if a short occurs in the overlapping portion due to static electricity generated during the operation.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, A gate driver 110 for supplying a scan signal to the gate lines GL1 to GLn and a data line DL1 to DLm for supplying a scan signal to the gate lines GL1 to GLn, A data driver 120 for supplying data and a timing controller 130 for controlling the gate driver 110 and the data driver 120.

The liquid crystal display panel 100 is formed such that a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm cross each other. The thin film transistors TFT formed at the intersections of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm are connected to the data lines DL1 to DLn in response to scan signals from the gate lines GL1 to GLn, DLm to the liquid crystal cell Clc. To this end, the gate electrode of the thin film transistor TFT is connected to the gate lines GL1 to GLn, and the source electrode thereof is connected to the data lines DL1 to DLm. The drain electrode of the thin film transistor TFT is connected to the pixel electrode of the liquid crystal cell Clc.

A storage capacitor Cst for holding the voltage of the liquid crystal cell Clc is formed on the liquid crystal display panel 100. The storage capacitor Cst may be formed between the liquid crystal cell Clc and a separate common line.

The gate driver 110 correspondingly supplies scan signals to a plurality of gate lines GL1 to GLn in response to a gate control signal GCS from the timing controller 130. [ The plurality of scan signals cause the plurality of gate lines GL1 to GLn to be sequentially enabled for one horizontal synchronous signal period.

The data driver 120 generates a plurality of pixel data voltages each time one of the plurality of gate lines GL1 to GLn is enabled in response to a data control signal DCS from the timing controller 130 And supplies them to the plurality of data lines DL1 to DLm on the liquid crystal display panel 100, respectively.

The timing controller 130 receives synchronization signals (Vsync, Hsync) supplied from an external system (for example, a graphics module of a computer system or a video demodulation module of a television receiving system, not shown) A gate control signal GSC for controlling the gate driver 110 and a data control signal DCS for controlling the data driver 120 are generated using a clock signal DE and a clock signal CLK. In addition, the timing controller 130 arranges the image data (V-data) input from the external system and supplies the aligned data to the data driver 120.

FIG. 2 is a diagram schematically showing an integrated circuit constituting a gate driver and a data driver incorporated in the liquid crystal display panel of FIG. 1;

1 and 2, the liquid crystal display panel 100 includes data composed of first to third data driver integrated circuits 120a to 120c mounted on the upper non-display area of the thin film transistor array substrate 101 A driver 120 and a gate driver 110 embedded in the left end non-display region of the TFT array substrate 101.

A plurality of data lines DL and a plurality of gate lines GL are formed on the thin film transistor array substrate 101 such that the plurality of data lines DL and the gate lines GL are orthogonal to each other. The cells Clc are arranged in a matrix form.

The liquid crystal display panel 100 includes a color filter substrate 103 facing the thin film transistor array substrate 101. The color filter substrate 103 includes a black matrix formed between neighboring liquid crystal cells to define a cell region, and R, G, and B color filters for implementing color.

The first to third data driver ICs 120a to 120c are connected to a data control signal DCS from a timing controller 130 of FIG. 1 via a flexible printed circuit (FPC) Converts the input data Data into an analog data voltage and supplies the analog data voltage to the corresponding data line DL.

The gate driver 110 includes a plurality of circuit units built on the liquid crystal display panel 100 and corresponding to the gate lines GL1 to GLn in one-to-one correspondence. As shown in FIG. 3, each of the plurality of circuit units includes a plurality of transistors T1 to T9.

At this time, the configuration of each of the plurality of circuit portions is not limited to the configuration shown in FIG. 3, but can be modified into various forms.

Specifically, the start pulse SP, the clock signal CLK, the gate high voltage VGH, and the gate low voltage VGL are input to the first circuit portion among a plurality of circuit portions included in the gate driver 110. The output signal of the previous stage is input to the remaining circuit portion as the start signal Vst instead of the start pulse SP. That is, the output signal of the (n-2) th circuit section is input to the nth circuit section as the start signal Vst.

The first circuit unit includes a control unit including first through seventh transistors T1 through T7 and an output unit including eighth and ninth transistors T8 and T9.

The control unit of the first circuit unit includes a first transistor T1 responsive to a start pulse SP and connected between a gate high voltage VGH input line and a first node Q, A second transistor (T2) coupled between the first node (Q) and an input line of a gate low voltage (VGL); a second transistor And a third transistor T3 connected between the electrode and the input line of the gate-low voltage VGL.

The control unit of the first circuit unit may further include a fourth transistor coupled in response to the output signal of the second stage and connected between the gate high voltage (VGH) input line and a node to which a voltage provided to the second node (QB) And a fifth transistor (T5) connected between a node to which a voltage provided to the second node (QB) is applied and a gate-low voltage (VGL) input line in response to a voltage on the first node (Q) .

The fourth transistor T4 is turned on to an output signal provided from the second stage to apply a gate high voltage VGH from the gate high voltage VGH input line to the second node QB ). The ninth transistor T9 is turned on by a gate high voltage VGH provided to the second node QB to turn the output voltage Vgout into a low logic state.

The fifth transistor T5 serves the same function as the fourth transistor T4 but the fourth transistor T4 is turned on to the output signal provided from the second stage, (T5) differs only in that it is turned on by the voltage provided to the first node (Q).

The control unit of the first circuit unit may further include a sixth transistor T6 responsive to the gate high voltage VGH and connected between the gate high voltage VGH input line and the second node QB, And a seventh transistor (T7) responsive to the first node (SP) and connected between the second node (QB) and a gate-low voltage (VGL) input line.

The sixth and seventh transistors T6 and T7 serve as a bias resistor for removing a noise component that may occur in the output portion.

The output of the first circuit part includes an eighth transistor T8 for selecting the clock signal CLK according to the voltage on the first node Q and supplying the clock signal CLK to the first gate line GL1 corresponding to the first stage, And a ninth transistor T9 for discharging the output signal of the eighth transistor T8 according to the voltage on the second node QB.

Figure 4 is an enlarged view of a portion of the circuitry of Figure 3;

3 and 4, the first circuit unit includes a clock signal (CLK) input line (CLK_line) to which the clock signal (CLK) is input and a first and second start signal (Vst) And Vst_line_2 are electrically connected to form a start signal (Vst) input line (Vst_line) having a parallel structure and a plurality of transistors (TR).

The start signal Vst input line Vst_Line includes first and second start signal Vst input lines Vst_line_1 and Vst_line_2 and the first and second start signal input lines Vst_line_1 and Vst_line_2 are connected in parallel And are electrically connected to each other.

More specifically, the start signal (Vst) input line (Vst_line) is formed on the substrate in parallel with the clock signal (CLK) input line (CLK_line), and is overlapped with the clock signal (CLK) 1 and a second start signal (Vst) input line (Vst_line_1, Vst_line_2).

At this time, the start signal (Vst) input line (Vst_line) is formed of the same material as the gate line (GL) of the liquid crystal display panel (100 of FIG. 1) through the same process, and the clock signal Is formed through the same process with the same material as the data line DL.

Since this circuit portion is embedded in a limited area of the liquid crystal display panel 100 of Fig. 1 and the output signal of the (n-2) th circuit portion is input as the start signal Vst of the nth circuit portion, A start signal (Vst) input line (Vst_line) formed of a metal and a part of a clock signal (CLK) input line are overlapped.

A method of repairing a short when an overlapping start signal Vst input line Vst_line and a clock signal CLK input line CLK_line occur is described in detail with reference to an example shown in FIGS. 5A and 5B I will explain.

When the static electricity is generated during the manufacturing process of the liquid crystal display panel (100 of FIG. 1) having the above-described circuitry, the start signal (Vst) input line (Vst_line) and the clock signal (CLK) input line A short is generated in the overlapped portion.

The clock signal CLK input line CLK_line is also superimposed on the start signal Vst input line Vst_line having a parallel structure for the sake of convenience. And the first and second clock signal (CLK) input lines of the parallel structure. At this time, the start signal (Vst) input line (Vst_line) does not have a parallel structure.

5A, the first start signal (Vst) input line (Vst_line_1) and the clock signal (CLK) input line (CLK_line) of the start signal (Vst) input line (Vstl_line) The signal supplied to the first start signal Vst input line Vst_line_l can not flow in the shorted region and the transistor TR to which the start signal Vst is to be input is short- It is impossible to sufficiently transmit the information. As a result, since the normal start signal Vst is not applied to the circuit portion, the signal for driving the gate line (GL in FIG. 1) is not applied or the signal is unstably applied.

Similarly, the signal supplied to the clock signal (CLK) input line can not flow in the shorted region, and the clock signal (CLK) is not sufficiently transferred to the inputted transistor (TR) It is impossible to apply a signal to the signal or the signal is unstably applied.

Therefore, when a short occurs in a region where the first start signal Vst input line Vst_line_1 and the clock signal CLK input line CLK_line overlap, the first start signal Vst input line Vst_line_1 are cut by using a laser and the first and second start signal Vst input lines Vst_line_1 and Vst_line_2 are separated.

The start signal Vst is sufficiently transmitted to the transistor TR of the circuit section through the second start signal Vst input line Vst_line_2 electrically isolated from the first start signal Vst input line Vst_line_1. .

5B, in a portion where the second start signal Vst input line Vst_line_2 and the clock signal CLK input line CLK_line of the start signal Vst input line Vstl_line are overlapped with each other, When a short occurs, the left and right sides of the second start signal Vst input line Vst_line_2 are cut using a laser, and the first and second start signal Vst input lines Vst_line_1, Vst_line_2).

The start signal Vst is sufficiently transmitted to the transistor TR of the circuit part through the first start signal Vst input line Vst_line_ 1 electrically isolated from the second start signal Vst input line Vst_line_ 2 . Also, the clock signal (CLK) input line (CLK_line) can sufficiently transfer the clock signal (CLK) to the transistor (TR) of the circuit part through repair using a laser.

As described above, in the liquid crystal display according to the present invention, the start signal (Vst) input line overlapping the clock signal (CLK) input line in the plurality of circuit portions of the built- A start signal Vst input line can be used to facilitate laser repair even if a short occurs due to static electricity generated during the process in a region where the two input lines overlap.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention. FIG.

Fig. 2 is a schematic view of an integrated circuit constituting a gate driver and a data driver incorporated in the liquid crystal display panel of Fig. 1; Fig.

FIG. 3 is a detailed circuit diagram of a first circuit portion of the circuit portion of the gate driver of FIG. 2; FIG.

Figure 4 is an enlarged view of a portion of the circuitry of Figure 3;

5A and 5B are diagrams illustrating a method of repairing a short when a start signal input line and a clock signal input line of FIG. 4 occur.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

100: liquid crystal display panel 101: thin film transistor substrate

103: Color filter substrate 110: Gate driver

120: Data driver 130: Timing controller

120a to 120c: first to third data driver ICs

122: Flexible Printed Circuit (FPC)

Claims (15)

A liquid crystal display panel in which a plurality of gate lines and a plurality of data lines cross each other; A data driver for driving the plurality of data lines; A gate driver which is built in the liquid crystal display panel and has a plurality of circuit portions shifted to a start pulse to sequentially supply an output signal to the plurality of gate lines; Each of the circuit portions including the first to third regions, A clock signal input line to which a clock signal is input; a start pulse input line to which the start pulse is inputted and partially overlap the clock signal input line; and a plurality of transistors driven by the clock signal and the start pulse, Wherein the clock signal input line and the start pulse input line are parallel in the first and third regions and vertically overlap in the second region, The start pulse input line in the second area of the circuit part is divided into first and second start pulse input lines having a parallel structure and electrically connected, When a start pulse input line of any one of the first and second start pulse input lines and the clock signal input line is short-circuited in the second region, the left and right sides of the start pulse input line are cut, 1 and the second start pulse input line are separated from each other and then a shorted clock signal input line is electrically connected. The method according to claim 1, And the shorted clock signal input lines are electrically connected by using a laser. The method according to claim 1, Wherein the clock signal input line is formed of the same material as the data line through the same process, and the start pulse input line is formed through the same process with the same material as the gate line. The method according to claim 1, Wherein the first and second start pulse input lines partially overlap the clock signal input line, respectively. delete delete delete A liquid crystal display panel in which a gate line and a data line are arranged; a clock signal input line which is built in the liquid crystal display panel and shifts to a start pulse to sequentially supply an output signal to the gate line and to which a clock signal is input; Wherein the clock signal input line and the start pulse input line are connected to a first and a second input terminal of the circuit part, respectively, and a gate driver having a plurality of circuit parts including a start pulse input line partially overlapped with the clock signal input line, And the start pulse input line is parallel-structured in the second region of the circuit portion and is divided into first and second start pulse input lines electrically connected to each other in the second region of the liquid crystal display device In the compensation method, When a start pulse input line of any one of the first and second start pulse input lines and the clock signal input line is short-circuited in the second region, the left and right sides of the start pulse input line are cut, 1 and a second start pulse input line; And And electrically connecting the short clock signal input line to the liquid crystal display device. 9. The method of claim 8, Wherein the clock signal input line is formed of the same material as the data line through the same process and the start pulse input line is formed through the same process with the same material as the gate line. 9. The method of claim 8, The step of electrically connecting the shorted clock signal input line electrically connects the shortened clock signal input line using a laser. A liquid crystal display panel in which a plurality of gate lines and a plurality of data lines cross each other; A data driver for driving the plurality of data lines; A gate driver which is built in the liquid crystal display panel and has a plurality of circuit portions shifted to a start pulse to sequentially supply an output signal to the plurality of gate lines; Each of the circuit portions including the first to third regions, A clock signal input line to which a clock signal is input; a start pulse input line to which the start pulse is inputted and partially overlap the clock signal input line; and a plurality of transistors driven by the clock signal and the start pulse, Wherein the clock signal input line and the start pulse input line are parallel in the first and third regions and vertically overlap in the second region, The clock signal input line in the second region of the circuit portion is divided into first and second clock signal input lines having a parallel structure and electrically connected, When the clock signal input line and the start pulse input line of the first and second clock signal input lines are short-circuited in the second region, the left and right sides of the clock signal input line are cut, 1 and the second clock signal input line are separated from each other and then shorted start pulse input lines are electrically connected to each other. 12. The method of claim 11, And the shorted clock signal input lines are electrically connected by using a laser. 12. The method of claim 11, Wherein the clock signal input line is formed of the same material as the data line through the same process, and the start pulse input line is formed through the same process with the same material as the gate line. 12. The method of claim 11, Wherein the first and second clock signal input lines are partially overlapped with the start pulse input line, respectively. The method according to any one of claims 1 to 11, Wherein the first circuit portion of the plurality of circuit portions of the gate driver includes a control portion and an output portion, The control circuit of the first circuit part being responsive to a start pulse and being connected between a gate high voltage input line and a first node and a second transistor coupled in response to an output signal of the second circuit part, A third transistor connected between the source electrode of the first transistor and an input line of the gate low voltage in response to a voltage on the second node and a third transistor connected between the source line of the first transistor and an input line of the gate low voltage, A fourth transistor coupled between the gate high voltage input line and a node to which a voltage provided to the second node is applied; a node coupled to the gate of the second transistor, the node being supplied with a voltage supplied to the second node in response to a voltage on the first node; A fifth transistor coupled between a voltage input line and a second transistor coupled between the gate high voltage input line and a second And a seventh transistor coupled between the second node and the gate low voltage input line in response to the start pulse, Wherein the output of the first circuit part comprises an eighth transistor for selecting the clock signal according to a voltage on the first node and supplying the selected clock signal to a first gate line corresponding to the first circuit part, And a ninth transistor for discharging an output signal of the eighth transistor.

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