KR101643497B1 - A multiplying delay locked loop circuit using time registers and a method for synthesizing a frequency - Google Patents

Abstract

A multiplying delay locked loop circuit according to an embodiment of the present invention comprises: a ring oscillator including one or more delay lines through which an input reference clock signal passes and outputting frequency-multiplied pulse signals according to the operation of the delay lines; a first time register for receiving a first pulse signal from the output of the ring oscillator and outputting a first voltage corresponding to the pulse time width of the first pulse signal; a second time register for receiving a second pulse signal from the output of the ring oscillator and outputting a second voltage corresponding to the pulse time width of the second pulse signal; and a frequency correction unit for correcting the oscillation frequency of the ring oscillator according to the comparison result of the first voltage and the second voltage. The multiplying delay locked loop circuit of the present invention can reduce static phase offset.

Description

TECHNICAL FIELD [0001] The present invention relates to a multiply delay locked loop circuit and a frequency synthesizing method using a time storage device,

The present invention relates to a multiply delay locked loop circuit and a frequency synthesizing method using a time storage.

A delay locked loop (DLL) may be used to generate an internal clock in an electronic device. A general delay locked loop generates an internal clock synchronized with an external clock by delaying the received external clock by a predetermined time using a delay line. The delay locked loop based clock generation device has less phase noise due to the absence of jitter accumulation as compared with the phase locked loop based clock generation device and the local oscillator, and the structure of the loop filter is simple. In particular, in the case of a semiconductor memory device, the data transfer rate can be increased by using an internal clock having a frequency multiplied by the frequency of the external clock, and by using clocks having an accurate phase delay and duty ratio for data transfer, Errors can be reduced.

1 and 2 show a general delay locked loop circuit and a multiplying delay locked loop circuit.

A general delay locked loop is a circuit for injecting a reference signal into a delay line and outputting a signal delayed by one period of the reference signal from the input reference signal, and its structure is as shown in FIG. In addition, such a delay locked loop can be applied to frequency synthesis through not only one period delay of an input reference signal but also an arbitrary period delay.

In recent years, studies have been actively made on a multiplying delay locked loop (MDLL) in which the delay line of the conventional delay locked loop shown in FIG. 2 is replaced with a ring structure. The frequency synthesizer using such a multiply-delayed synchronous loop has a better phase noise performance than the frequency synthesizer using a conventional phase-locked loop because the jitter accumulated in the oscillator is cleared by the input reference signal have.

3 is a diagram showing a frequency output waveform of a ring oscillator of a general multiplication delay locked loop.

However, as shown in FIG. 3, if the frequency of the ring oscillator is not exactly equal to the intended frequency, it can be confirmed that a static phase offset occurs for each reference signal.

Such a static phase offset has a problem of generating a frequency tone (reference spur) of a certain size in the frequency synthesizer output spectrum.

This problem is generally caused by the up-current and down-current mismatch of the charge pump of the multiply-delayed synchronous loop of FIG. 2 and the output signal of the ring oscillator from the phase detector ) And a mismatch in the length of the input signal to the input multiplexer of the ring oscillator. This size is assumed to be about 30 GHz for each input of each reference signal, assuming that the frequency of the multiplication delay locked loop output signal is 1.5 GHz. Resulting in an offset of 40 picoseconds. Therefore, research to reduce the static phase offset of the multiply-delay synchronous loop is a reality.

KR 10-2001-006635 A

 A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance (Apr.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a multiplication delay synchronous loop circuit capable of reducing a static phase offset, which is a key problem of the multiplication delay synchronization loop, and a frequency synthesis method using the same.

According to an aspect of the present invention, there is provided a multiplying delay locked loop circuit including at least one delay line through which an input reference clock signal passes, and a multiplying delayed pulse signal according to an operation of the delay line, A ring oscillator for outputting; A first time storage unit receiving a first pulse signal from the ring oscillator output and outputting a first voltage corresponding to a pulse time width of the first pulse signal; A second time storage unit receiving a second pulse signal from the ring oscillator output and outputting a second voltage corresponding to a pulse time width of the second pulse signal; And a frequency correction unit for controlling the ring oscillator according to a comparison result of the first voltage and the second voltage.

According to another aspect of the present invention, there is provided a method of synthesizing a multiplication delay locked loop, the method comprising the steps of: when an input reference clock signal is applied to an operation of one or more delay lines included in a ring oscillator, Generating a delayed pulse signal; Synthesizing and outputting a clock signal multiplied by a predetermined multiple of the reference clock signal according to the delay pulse signal; Receiving a first pulse signal from the multiplied delayed pulse signal by the first time storage and obtaining a first voltage corresponding to a pulse time width of the first pulse signal; Receiving a second pulse signal from the pulse signal multiplied by the second delay time and acquiring a second voltage corresponding to a pulse time width of the second pulse signal; And correcting the ring oscillator according to a result of comparison between the first voltage and the second voltage.

According to another aspect of the present invention, there is provided a method of reproducing a program recorded on a computer-readable recording medium.

According to an embodiment of the present invention, by accurately measuring the static phase offset by comparing the pulse width of the pulse signal delayed in the ring oscillator using one or more time storage, and thereby performing frequency correction of the ring oscillator, It is possible to eliminate various problems caused by the offset.

Particularly, as the static phase offset is reduced, a frequency synthesizer with low noise performance using a multiply delay locked loop with a very low reference signal tone (Reference Spur) can be implemented.

1 and 2 show a general delay locked loop circuit and a multiplying delay locked loop circuit.
3 is a diagram showing a frequency output waveform of a ring oscillator of a general multiplication delay locked loop.
4 is a block diagram for explaining a multiply-accumulation synchronizing loop circuit according to an embodiment of the present invention.
5 illustrates the configuration and output waveforms of a first time store and a second time store according to an embodiment of the present invention.
6 shows a configuration of a first time storage device or a second time storage device according to another embodiment of the present invention.
7 is a flowchart illustrating a frequency synthesis method according to an embodiment of the present invention.

The following merely illustrates the principles of the invention. Thus, those skilled in the art will be able to devise various apparatuses which, although not explicitly described or shown herein, embody the principles of the invention and are included in the concept and scope of the invention. Furthermore, all of the conditional terms and embodiments listed herein are, in principle, only intended for the purpose of enabling understanding of the concepts of the present invention, and are not to be construed as limited to such specifically recited embodiments and conditions do.

It is also to be understood that the detailed description, as well as the principles, aspects and embodiments of the invention, as well as specific embodiments thereof, are intended to cover structural and functional equivalents thereof. It is also to be understood that such equivalents include all elements contemplated to perform the same function irrespective of the currently known equivalents as well as the equivalents to be developed in the future, i.e., the structure.

Thus, for example, it should be understood that the block diagrams herein illustrate conceptual aspects of exemplary circuits embodying the principles of the invention. Similarly, all flowcharts, state transition diagrams, pseudo code, and the like are representative of various processes that may be substantially represented on a computer-readable medium and executed by a computer or processor, whether or not the computer or processor is explicitly shown .

The functions of the various elements shown in the drawings, including the functional blocks shown in a processor or similar concept, may be provided by use of dedicated hardware as well as hardware capable of executing software in connection with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, a single shared processor, or a plurality of individual processors, some of which may be shared.

Also, the explicit use of terms such as processor, control, or similar concepts should not be interpreted exclusively as hardware capable of running software, and may be used without limitation as a digital signal processor (DSP) (ROM), random access memory (RAM), and non-volatile memory. Other hardware may also be included.

In the claims hereof, the elements represented as means for performing the functions described in the detailed description include all types of software including, for example, a combination of circuit elements performing the function or firmware / microcode etc. , And is coupled with appropriate circuitry to execute the software to perform the function. It is to be understood that the invention defined by the appended claims is not to be construed as encompassing any means capable of providing such functionality, as the functions provided by the various listed means are combined and combined with the manner in which the claims require .

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which: There will be. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

4 is a block diagram for explaining a multiply-accumulation synchronizing loop circuit according to an embodiment of the present invention.

4, a multiplying delay locked loop circuit 100 according to an embodiment of the present invention includes an input unit 105, a ring oscillator 150, a first time storage 111, a second time storage 112, A frequency divider 140, a frequency divider 130, a frequency divider 130, a frequency divider 140, a frequency divider 140, a frequency divider 140, a frequency divider 140, ) Includes a first digital accumulator 141 and a D / A converter 142.

The input unit 105 receives the reference clock signal and transmits the reference clock signal to the ring oscillator 150. The input unit 105 can be controlled by a controller and implemented with an input multiplexer.

The reference clock signal input to the input unit 105 may be a signal generated from a pulse generator. The pulse generator may generate a reference clock signal for generating a multiplied clock signal and periodically input the reference clock signal through the input unit 105 according to a predetermined period. Accordingly, each component of the multiplying delay locked loop circuit 100 can operate according to the input period of the reference clock signal.

The ring oscillator 150 includes at least one delay line through which the input reference clock signal passes, and outputs a delay pulse signal according to the operation of the delay line. The delay pulse signal may be synthesized as a frequency-multiplied clock signal in accordance with the operations of the drain determination unit 165 and the selection logic circuit 160.

In addition, each delay line of the ring oscillator 150 may include a plurality of delay blocks. Each of the delay blocks is configured to delay the reference clock signal by a predetermined phase in response to the mode control signal and the initial delay value during the synchronization operation from the time when power is supplied to the multiplying delay lock loop circuit 100 to a specific point Can be performed.

At this time, each of the delay blocks independently performs an operation for delaying the reference clock signal ref by a predetermined phase in response to the mode control signal and the initial delay value.

In each of the delay blocks, in synchronous operation with respect to the output clock after a certain point in time has elapsed since the power supply to the multiplying delay lock loop circuit 100 started, the reference clock or the front end And a phase delay line for controlling the phase of the signal output from the delay block of FIG.

The delay pulse signal delayed through the ring oscillator 150 is output through the drain determiner 165 and the selection logic circuit 160 to the output having a frequency multiplied by a predetermined multiple of the frequency of the reference clock signal ref It can be synthesized as a clock and output to the outside.

The first time storage unit 111 receives the first pulse signal from the output of the ring oscillator 150 and outputs a first voltage corresponding to the pulse time width of the first pulse signal.

The second time storage unit 112 receives the second pulse signal from the ring oscillator output and outputs a second voltage corresponding to the pulse time width of the second pulse signal.

The first time storage unit 111 and the second time storage unit 112 may include a time register circuit for outputting a voltage level corresponding to a pulse width when a pulse is input.

Therefore, the time corresponding to the pulse widths of the first pulse signal and the second pulse signal can be measured according to the operation of the time registers of the first time storage unit 111 and the second time storage unit 112. In addition, the first time storage unit 111 and the second time storage unit 112 may accumulate and store the measured time information, respectively. For example, the first time storage unit 111 and the second time storage unit 112 may start time measurement of the pulse width as the rising edge of the pulse is detected, and time measurement may be performed as the falling edge of the pulse is detected And outputs the voltage levels (the first voltage and the second voltage) according to the accumulated time information to the comparator 120, respectively.

The comparator 120 compares the first voltage and the second voltage, and outputs the comparison result to the distributor 130.

The comparator 120 may determine which one of the first voltage and the second voltage is high, determine which voltage is low, and output the comparison result as the digital signal (VDD or GND).

Accordingly, the comparator 120 can determine which of the first pulse signal and the second pulse signal has a longer pulse width. If any one of the pulse widths is greater than or equal to a predetermined value or smaller than the predetermined value, the comparator 120 determines whether the output frequency of the multiplying delay locked loop 100 is slower or faster than the ideal state, It can be judged whether or not it is. The static phase offset information, which is measured as the occurrence of the static phase offset accumulates, results in the necessity of frequency correction of the multiplying delay locked loop circuit 100.

After the pulse width comparison in the comparator 120 is completed, the first time storage unit 111 and the second time storage unit 112 are reset to prepare the next first pulse signal and the second pulse signal again can do. For example, the controller of the multiplying delay locked loop circuit 100 periodically sets the SET of the first time storage 111 and the second time storage 112 to GND to reset Vout1 and Vout2 to VDD, It is possible to determine again whether the delay clock signal frequency is slow or fast with respect to the reference value of the delay clock signal frequency generated in the current delay synchronizing line each time the signal is input.

Meanwhile, the distributor 130 may transmit the comparison result to the first digital accumulator 141 or the second digital accumulator 170 according to the mode setting. The distributor 130 delivers the comparison result to the first digital accumulator 141 of the frequency corrector 140 in the normal operation mode of the multiply delay synchronous loop circuit 100 and in the calibration mode the second digital accumulator 170 ). ≪ / RTI >

The operation of each component in the embodiment of the present invention describes operation for the normal operation mode and can be described as another embodiment of the first time storage 111 and the second time storage 112 in the case of the calibration mode This will be described later.

The frequency corrector 140 controls the ring oscillator 150 according to the comparison result of the first voltage and the second voltage to correct the oscillation frequency.

The frequency corrector 140 includes a first digital accumulator 141 for accumulating digital code values corresponding to the comparison result of the first voltage and the second voltage according to the input period of the reference clock signal .

The first digital accumulator 141 can generate the first digital code value by receiving and accumulating the digital signal corresponding to the comparison result. The first digital code may be used as a control code for controlling the ring oscillator 150.

The D / A converter 142 may convert the first digital code value accumulated in the first digital accumulator into an analog control signal and apply the analog control signal to the ring oscillator 150 as a control signal.

More specifically, for example, when the output frequency of the doubled delay locked loop circuit 100 increases by a predetermined value or more, the frequency of the current doubled delay locked loop 100 is faster than the ideal state when the comparison result value is accumulated . Accordingly, the first digital code accumulated in the first digital accumulator 141 can be generated in a direction to lower the frequency of the multiply-accumulation synchronizing loop 100. [

Also, for example, when it is determined that the frequency of the multiply-accumulation synchronizing loop 100 is slower than the ideal situation due to accumulation of comparison results, the first digital accumulator 141 accumulates the accumulated first digital code Can be generated in a direction to reduce the frequency of the doubling delay synchronizing loop 100. [

The first digital code value thus generated may be converted into an analog control signal through the D / A converter 142. [ The D / A converter 142 may transmit a control signal for controlling the delay blocks included in the respective delay lines of the ring oscillator 150 to the respective delay blocks of the ring oscillator 150.

Thus, the operation timing of the delay blocks included in the delay line of the ring oscillator 150 can be controlled, and accordingly, the oscillation frequency of the ring oscillator 150 can be readjusted, resulting in the multiply- 100 can be performed.

On the other hand, in response to the delay pulse signal output from the ring oscillator 150, the drain determining unit 165 and the selection logic circuit 160 have a frequency whose duty ratio is constant and multiplied by a multiple of the frequency of the reference clock signal ref The output clock can be synthesized and output to the outside.

The operation of the multiplying delay locked loop circuit 100 can be performed every time a reference signal is input, and the frequency correction is repeatedly performed, so that the static phase offset according to the frequency difference can be made zero. Further, this solution of the present invention can be explained as applying the principle of continuously detecting the error and continuously accumulating the error in the accumulator so as to change the control signal in the direction in which the error becomes zero.

Meanwhile, according to another embodiment of the present invention, the multiplying delay locked loop circuit 100 can operate in the calibration mode.

Designing the multiply delayed synchronous loop circuit 100 according to the embodiment of the present invention is essentially required to correct the distortion due to the inconsistency between the PVT (Process, Voltage, Temparature) Variations and the respective circuit elements and the offset of the comparator It becomes impossible. In order to solve this problem, the multiplying delay locked loop circuit 100 according to the embodiment of the present invention can correct this PVT variation and mismatch problem in the calibration mode.

In particular, even if the first and second time storage devices 111 and 112 actually receive the same pulse due to PVT Variation and mismatch, the output voltage may be different. To correct this again, the multiplying delay locked loop circuit 100 may operate in the calibration mode.

In this case, the same pulse for calibration may be input to the first time storage unit 111 and the second time storage unit 112. The pulse can be referred to as a calibration pulse.

Accordingly, the first time storage unit 111 outputs a first calibration voltage when a calibration pulse is input, and the second time storage unit 112 outputs a second calibration voltage when the calibration pulse is input have.

The comparator 120 compares the first calibration voltage and the second calibration voltage and outputs the comparison result to the divider 130. The divider 130 outputs the output of the comparator 120 to the second digital accumulator 170 ). ≪ / RTI >

Thereafter, the second digital accumulator 170 may accumulate the error detection value according to the comparator output. The second digital accumulator 170 may generate a calibration code corresponding to the error detection value and output it to the first time storage 111 or the second time storage 112. [

Accordingly, the first time storage 111 or the second time storage 112 can be calibrated so that the same output is output for the same input, by varying the value of the capacitor in the direction in which the error detection value is zero . As the element for changing the capacitor value, one or more variable capacitors such as a varactor may be included.

5 illustrates the configuration and output waveforms of a first time store and a second time store according to an embodiment of the present invention.

As shown in the example of the output waveform of the general multiplying delay locked loop (MDLL) in FIG. 3, the output of the multiplying delay locked loop synchronized to the rising edge of Ref (reference signal) As the waveform of Too high, the rising edges of the multiplication delay locked loop output are constantly output, and the interval is changed once as the reference signal is input.

Likewise, if the frequency of the multiplication delay synchronous loop is too slow, Freq. As shown in waveform of Too low, the rising edges of the multiplication delay locked loop output are constantly output, and the interval is reduced once when the reference signal is input.

3 (b) -1, (b) -2, where the difference of each pulse represents the static phase offset as described above, and the embodiment of the present invention uses this static phase offset And a multiplication delay locked loop circuit (100) for measuring through the first time storage (111) and the second time storage (112) and performing compensation corresponding thereto.

When a static phase offset occurs as shown in FIG. 3, the first time store 111 and the second time store 112 may exhibit respective output waveforms as shown in FIG.

When the first pulse signal is Ta and the second pulse signal is Tb, the first time storage unit 111 and the second time storage unit 112 output the voltage levels of Vout1 and Vout2 corresponding to the time width of the pulse can do. The first time storage 111 and the second time storage 112 may continuously output the voltage level during the generation of the pulse.

For example, the first time storage unit 111 and the second time storage unit 112 can lower the voltage level of Vout as the input pulse width is thicker. As shown in FIG. 5, since the pulse time widths of Ta and Tb are different from each other, the level of the output voltage may also be different. In addition, since the pulse time width of Tb is larger, an output waveform in which Vout1 becomes higher than Vout2 in the case of FIG. 5 can be seen.

The comparator 120 receives these Vout1 and Vout2, compares them, and outputs a comparison result as a digital signal (VDD or GND).

Then, the frequency corrector 140 can adjust the widths of the pulses Ta and Tb by controlling the ring oscillator 150 according to the comparison result. Accordingly, an object of the present invention to eliminate the static phase offset can be achieved.

6 shows a configuration of a first time storage device or a second time storage device according to another embodiment of the present invention.

6, the first time storage unit 111 or the second time storage unit 112 according to another embodiment of the present invention includes one or more variable capacitor units 111 (a) or 112 (b) ). The variable capacitor unit 111 (a) or 112 (b) may include at least one variable capacitor that varies in accordance with the error detection value accumulated in the second digital accumulator 170. The variable capacitor may include, for example, a varactor. In the calibration mode, an output error for the same input according to the PVT Variation of the first time storage 111 and the second time storage 112 / RTI >

7 is a flowchart illustrating a frequency synthesis method according to an embodiment of the present invention.

Referring to FIG. 7, in a frequency synthesizing method according to an embodiment of the present invention, a power supply and a reference clock signal are applied to a multiplying delay locked loop circuit 100 (S101).

The reference clock signal input to the input unit 105 may be transmitted to the ring oscillator 150.

Thereafter, the multiplying delay lock loop circuit 100 generates a delay pulse signal (S103).

The ring oscillator 150 may operate each delay line based on the reference clock signal to generate and output a delay pulse signal delayed in phase through each delay block.

Then, the generated delay pulse signal is synthesized as a frequency multiplied by the operation of the selection logic circuit 160 and outputted (S104).

The selection logic circuit 160 may synthesize and output a clock signal multiplied by a predetermined multiple of the reference clock signal according to the delay pulse signal according to the multiple determined by the drain determination unit 165. [

On the other hand, the multiplying delay locked loop circuit 100 acquires a first voltage corresponding to the pulse time width of the first pulse signal (S105) and acquires a second voltage corresponding to the pulse time width of the second pulse signal ( S105).

As described above, the first time store 111 may obtain a first voltage corresponding to the pulse time width of the first pulse signal from the ring oscillator 150 output, and the second time store 112 may obtain A second voltage corresponding to the pulse time width of the second pulse signal can be obtained from the ring oscillator 150 output.

Then, the multiplying delay locked loop circuit 100 accumulates a digital value corresponding to the static phase offset measured according to the first voltage and the second voltage comparison (S109).

The first digital accumulator 141 may accumulate the first digital code value based on the comparison result between the first voltage and the second voltage compared in the comparator 120. [ The first digital code value may correspond to a static phase offset and the D / A converter 142 may convert the first digital code value into a control signal that reduces the static phase offset.

Then, the multiplying delay locked loop circuit 100 controls the frequency of the ring oscillator 150 in a direction of reducing the accumulated static phase offset (S111).

As described above, the first digital code converted by the D / A converter 142 can be used as the control voltage of the ring oscillator 150. [ According to the control of the ring oscillator 150, frequency correction can be performed in a direction in which the static phase offset of the multiply-accumulation synchronizing loop is reduced.

Accordingly, the multiplying delay locked loop circuit 100 can provide a low noise frequency synthesizer and a method of synthesizing by reducing the error caused by the static phase offset to zero so that the output signal spectrum has a very low reference signal tone. Further, the multiplying delay locked loop circuit 100 can be used as a clock generator circuit of various digital circuits.

Meanwhile, the method according to various embodiments of the present invention described above may be implemented in program code and provided to each server or devices in a state stored in various non-transitory computer readable media.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, the various applications or programs described above may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It should be understood that various modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.

100: Multiplication delay synchronous loop circuit
111: first time storage
112: second time storage
120: comparator
130: distributor
140:
141: first digital accumulator
142: D / A converter
150: ring oscillator
160: selection logic circuit
170: second digital accumulator

Claims (13)

In the multiplying delay locked loop circuit,
A ring oscillator including at least one delay line through which the input reference clock signal passes, and outputting a pulse signal multiplied by the operation of the delay line;
A first time storage unit receiving a first pulse signal from the ring oscillator output and outputting a first voltage corresponding to a pulse time width of the first pulse signal;
A second time storage unit receiving a second pulse signal from the ring oscillator output and outputting a second voltage corresponding to a pulse time width of the second pulse signal;
A frequency corrector for controlling the ring oscillator according to a comparison result of the first voltage and the second voltage;
A comparator for comparing the first voltage and the second voltage and outputting the comparison result; And
And a divider for delivering the comparator output to the frequency corrector according to an operating mode. The method according to claim 1,
The frequency correction unit
A first digital accumulator for accumulating a digital code value corresponding to a comparison result of the first voltage and the second voltage according to an input period of the reference clock signal; And
And a D / A converter for converting a first digital code value accumulated in the first digital accumulator into an analog control signal and applying the same to a control signal of the ring oscillator
Multiplication delay synchronous loop circuit. delete The method according to claim 1,
The first time storage or the second time storage may comprise:
Wherein the reference clock signal is reset every time the reference clock signal is input to re-input the first pulse signal or the second pulse signal. The method according to claim 1,
Wherein the first time storage outputs a first calibration voltage when a calibration pulse is input,
Wherein the second time storage outputs a second calibration voltage when the calibration pulse is input,
Wherein the comparator compares the first calibration voltage and the second calibration voltage,
And a second digital accumulator for accumulating the error detection value according to the comparator output. 6. The method of claim 5,
The first time storage or the second time storage
And at least one variable capacitor varying in accordance with the error detection value. In the frequency synthesizing method of the multiplying delay locked loop,
Generating a delay pulse signal according to the operation of one or more delay lines included in the ring oscillator when the input reference clock signal is applied;
Synthesizing and outputting a clock signal multiplied by a predetermined multiple of the reference clock signal according to the delay pulse signal;
Receiving a first pulse signal from the multiplied delayed pulse signal by the first time storage and obtaining a first voltage corresponding to a pulse time width of the first pulse signal;
Receiving a second pulse signal from the pulse signal multiplied by the second delay time and acquiring a second voltage corresponding to a pulse time width of the second pulse signal; And
Correcting the ring oscillator according to a result of comparison between the first voltage and the second voltage,
Wherein the step of controlling the correction includes:
Comparing the first voltage and the second voltage, and outputting the comparison result; And
And transmitting an output of the comparison result to a frequency corrector according to an operation mode. 8. The method of claim 7,
Wherein the step of correcting and controlling the ring oscillator comprises:
Accumulating a first digital code value corresponding to a comparison result of the first voltage and the second voltage according to an input period of the reference clock signal; And
Converting the first digital code value into an analog control signal and applying the analog control signal as a control signal of the ring oscillator. 8. The method of claim 7,
And generating a control signal for reducing the static phase offset of the multiply delayed pulse signal according to the result of the comparison. 8. The method of claim 7,
Wherein the step of outputting the first voltage comprises:
And resetting the reference clock signal every time the reference clock signal is input to re-input the first pulse signal. 8. The method of claim 7,
Outputting a first calibration voltage when a calibration pulse is input to the first time storage;
Outputting a second calibration voltage when the calibration pulse is input to the second time storage;
Comparing the first calibration voltage and the second calibration voltage; And
And accumulating error detection values according to the comparison result. 12. The method of claim 11,
And varying a capacitance of the first time store or the second time store according to the error detection value. 13. A recording medium on which a program for causing a computer to execute the method according to any one of claims 7 to 12 is recorded.

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