KR101623729B1 - Flip Flop Circuit with Low Power and High Speed - Google Patents

Abstract

A flip-flop circuit capable of low-power high-speed processing is disclosed. The flip-flop circuit of the present invention uses only one inverted clock (CKB) as an internal clock, thereby enabling a high-speed latch operation by minimizing the internal gate delay during data processing. In addition, the current consumed can be reduced. On the other hand, the flip-flop circuit of the present invention can simultaneously drive the inverted output (QB) together with the output (Q) irrespective of the input data without a time delay.

Description

[0001] Flip Flop Circuit with Low Power and High Speed Processing [0002]

The present invention relates to a flip-flop circuit capable of high-speed processing and reducing current consumption by using only one internal clock to reduce gate delay.

In a variety of digital chip designs including a microprocessor, a flip-flop is widely used in various parts such as a pipeline structure, and it is necessary to realize low power and high performance.

FIG. 1 is a circuit diagram of a conventional conventional flip-flop, and FIG. 2 is a timing diagram for explaining its operation. The flip-flop of Fig. 1 latches the input data D to the output Q at the positive edge of the clock CK.

1, the flip-flop 100 includes an 101st inverter 101 for outputting an inverted input DB in which the phase of the input D is inverted, an inverter 101 for turning on and off according to the phase of the clock CK A first latch 103 and a second latch 105 for performing a latch operation and a second latch 105 and Keeper 2 for performing a latch operation, An output driver 107 and two clock buffers 109 and 111 for converting the clock CK into internal clocks CK1 and CK1B. If the positions of the two transmission gates T1 and T2 change, the corresponding flip-flop operates as a negative edge trigger.

Referring to FIG. 2, when the clock CK transits to a logic low, the first transfer gate T1 and the first latch 103 operate. When the clock CK is again high (High) , The second transfer gate T2 and the second latch 105 (Keeper 2) operate.

When the clock CK becomes a logic low, the internal clocks CK1B and CK1 become logic high and low, respectively, so that the first transfer gate T1 is turned on and the inverted input DB Is transmitted to the node a (na). On the other hand, the transistors M-1, M-2, M-3 and M-4 are clocked-inverted structures, and the internal clocks CK1B and CK1 cause the transistors M- ) Is turned off. Therefore, since the voltage of the b-node nb is not fed back to the node n during the transfer of the inverted input DB to the node a, the signal battle between the 101st inverter 101 and the first latch Signal Fighting does not occur, thus facilitating signal transmission and preventing unnecessary current consumption. The transistors M-6 and M-7 are turned on while the second node nc turns on the data of the previous cycle while the second transfer gate T2 is turned off while the clock CK is logic low. do. This state continues until the phase of the clock CK is changed again and the phase of the internal clocks CK1 and CK1B is changed again.

In order to sufficiently turn on the first transfer gate T1 with the logic low clock CK and the inverted input DB as the logic high to the second node nb, as in the first cycle of FIG. 2, → Time required for four gate delays by passing through PMOS → 103 of T1.

When the clock CK again transitions to logic high, the first transfer gate T1 is turned off and the transistors M-2 and M-3 are turned on, so that the first latch latches the inverting input DB . At the same time, the second transfer gate T2 is turned on and the transistors M-6 and M-7 of the second latch are turned off. In order to sufficiently transfer the voltage of the b-th node nb, which is a logical low, to the output Q through this process after the clock CK becomes logic high again, the NMOS 105 → 107 of 109 → 111 → T2 is passed Five gate delay times are required.

On the other hand, when the input data D is logic high as in the second cycle, the delay in the first transfer gate T1 and the second transfer gate T2 becomes somewhat shorter. Three gate delays are sufficient to pass the inverted input (DB), which is a logic low while the clock (CK) is logic low, to the second node (n-b) through 109 → NMOS → T1 of T1. In order to transfer the voltage of the b-th node (n-b) to the output Q while the clock CK is logic high, it takes four gate delays by passing through 109 → T2 → PMOS → 105 → 107.

The conventional flip-flop 100 shown in Fig. 1 not only requires two internal clocks CK1B and CK1 for the operation of the first transmission gate T1 but also has a maximum Since the time required for the five gate delay is required, an operation delay for the clock occurs. Further, as the clock CK operates, the clock buffers 109 and 111 continue to operate, which increases power consumption of the clock circuit.

The time until the output Q is latched depends on the input D as described above. Also, when a complementary output such as Q and QB is required at the same time, it is necessary to use a separate inverter for the inverting output (QB), so that an error occurs between the output Q and the QB as much as a time delay of one inverter. Therefore, the conventional flip-flop circuit as shown in Fig. 1 can not be used in a circuit in which the outputs Q and QB are simultaneously required, such as an exclusive-OR or an exclusive-NOR circuit.

An object of the present invention is to provide a flip-flop circuit capable of high-speed processing and reducing current consumption by using only one internal clock to reduce gate delay.

In order to achieve the above object, according to the present invention, a flipflop uses only one internal clock (clock) unlike the conventional method.

A flip-flop circuit according to the present invention comprises a first inverter for outputting an inverted input (DB) obtained by inverting an input (D), a second inverter for outputting a delayed input (DD) A first stage which operates when the inverted clock is at a logical high and a second stage which operates when the inverted clock is at a logical low; Respectively.

Wherein the first stage includes a first transistor and a second transistor for transferring the delayed input and the inverted input to a first node and a second node respectively when the inverted clock is logic high, A fourth transistor pulling up said first node; a sixth transistor pulling up said second node when said first node voltage is logic low; and a sixth transistor pulling said first node voltage when said inverse clock is logic low A first latch and a second latch for latching the second node voltage when the inverted clock is logic low.

The second stage includes a thirteenth transistor and a fourteenth transistor for transferring the first node and the second node voltage to a third node and a fourth node respectively when the inverted clock is logic low, A seventeenth transistor for pulling down the third node when the third node voltage is logic high; a seventeenth transistor for pulling down the fourth node when the third node voltage is logic high; And a fourth latch for latching the fourth node voltage when the inverted clock is logic high.

When the first transistor and the second transistor are an NMOS transistor according to the embodiment, the flip-flop of the present invention is provided between the first node and the first power supply voltage (Vdd) together with the fourth transistor, And a fifth transistor which is provided between the second node and the first power supply voltage together with the sixth transistor and is turned off when the delay input is logic high can do.

Further, when the thirteenth transistor and the fourteenth transistor are a PMOS transistor, the flip-flop of the present invention is provided between the third node and the second power supply voltage (Vss) together with the fifteenth transistor, A seventeenth transistor that is turned off when the first node voltage is a logic low, and a seventeenth transistor that is provided between the fourth node and the second power source voltage together with the seventeenth transistor and is turned off when the first node voltage is logic low. As shown in FIG.

The first latch may include a seventh transistor, an eighth transistor, and a ninth transistor disposed between the first power supply voltage and the second power supply voltage. Wherein the seventh transistor is a pull-up transistor that is turned on when the inverted clock is logic low, and wherein the eighth transistor and the ninth transistor are connected such that each gate terminal is connected to the second node, Lt; / RTI >

The second latch may include a tenth transistor, an eleventh transistor and a twelfth transistor arranged between the first power supply voltage and the second power supply voltage, and the tenth transistor may be configured such that when the inversion clock is logic low Wherein the gate terminal of each of the eleventh transistor and the twelfth transistor is connected to the first node and the interconnection node is connected to the second node.

The third latch may include a nineteenth transistor, a twentieth transistor, and a twenty-first transistor disposed between the first power supply voltage and the second power supply voltage, and the nineteenth transistor and the twentieth transistor may include a gate terminal The fourth node is connected to the third node, and the twenty-first transistor is a pull-down transistor that is turned on when the inverted clock is logic high.

The fourth latch may include a twenty-second transistor, a twenty-third transistor, and a twenty-fourth transistor disposed between the first power supply voltage and the second power supply voltage, and the twenty-second transistor and the twenty- The third node is connected to the fourth node and the twenty-fourth transistor is a pull-down transistor that is turned on when the inverted clock is logic high.

The flip-flop circuit of the present invention further includes a fourth inverter for inverting the fourth node voltage to drive a final output (Q), and inverting the third node voltage to drive the inverted output (QB) The inverter may further comprise a separate inverter.

The flip-flop according to another embodiment of the present invention can be triggered on the negative edge of the clock by changing the positions of the first and second stages. Accordingly, the flip-flop has a tenth tenth stage, which operates when the inverted clock is logic low, and a twentieth stage, which operates when the inverted clock is logic high, instead of the first stage and the second stage. .

The tenth stage includes a thirteenth transistor and a fourteenth transistor for transferring the delayed input and the inverted input to the third node and the fourth node respectively when the inverted clock is logic low, A seventeenth transistor for pulling down the third node when the third node voltage is logic high; and a seventeenth transistor for pulling down the fourth node when the third node voltage is logic high, And a fourth latch for latching the fourth node voltage when the inverted clock is logic high.

Wherein the twentieth stage comprises: a first transistor and a second transistor for transferring the third and fourth node voltages to a first node and a second node, respectively, when the inverted clock is logic high; A sixth transistor pulling up said second node when said first node voltage is logic low; and a fifth transistor pulling said second node when said inverted clock is logic low, And a second latch for latching the second node voltage when the inverted clock is logic low.

Further, the flip-flop here has a fourth inverter connected to the second node for driving the final output Q, and a separate inverter for driving the inverted output QB is connected to the first node.

The flip-flop according to the present invention has a significantly improved gate delay in the internal flip-flop compared with the conventional flip-flop. Also, since the flip-flop of the present invention uses only one of its internal clocks, this improvement effect is independent of whether the input D is logic low or logic high.

Another feature of the flip-flop of the present invention is that it is capable of outputting an inverted output (QB) with an output (Q), and further there is no delay between the inverted output (QB) and the output (Q).

In addition, each stage of the flip-flop of the present invention has a structure for blocking unnecessary current consumption through the pull-up part and the pull-down part in the process of disposing the pull-up part or the pull-down part in order to eliminate errors in data transmission through the transmission gate , The power consumption of the entire flip-flop is relatively small.

1 is a circuit diagram of a conventional conventional flip-
FIG. 2 is a timing diagram for explaining the operation of FIG. 1,
3 is a circuit diagram of a flip-flop according to an embodiment of the present invention.
4 is a timing chart provided in the operation description of Fig. 3, and Fig.
5 is a circuit diagram of a flip-flop according to another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the drawings.

The flip-flop 300 of the present invention, which is illustratively shown in FIG. 3, is triggered at a positive edge. Further, although FIG. 3 shows only one output (Q) terminal, it is possible to obtain an output Q and an inverted output QB without a delay by further providing an inverter for inverting the third node voltage described below. The flip-flop 300 of the present invention uses only one inverted clock (CKB) inverted from the clock (CK) in the circuit.

3 includes a first inverter I1 provided between an input D and a fifth node n5 and outputting an inverted input DB and a fifth inverter n5, A second inverter I2 which is provided between the sixth node n6 and outputs a delay input DD which inverts the inverting input DB again and a second inverter I2 which is provided between the sixth node n6 and a logic high A second stage 330 which operates in a logic low (low or zero) interval of the inverted clock CKB and a second stage 330 which operates in a clock (CKB) inverting the clock CK to an inverted clock (CKB) A buffer I3 and a fourth inverter I4 connected to the second stage 330 and finally driving the output Q. [

The first stage 310 includes a first transistor M1 that is turned on when the inverted clock CKB is at logic high and transfers the delayed input DD to the first node n1, A second transistor M2 for turning on when the first power supply voltage Vdd is high and transferring the inverted input DB to the second node n2; and a second transistor M2 connected in series between the first power supply voltage Vdd and the first node n1, A third transistor M3 and a fourth transistor M4 which are pull-up transistors controlled by an input DB and a second node voltage; A fifth transistor M5 and a sixth transistor M6 which are serially connected to each other and are controlled by a delay input DD and a first node voltage and a fifth transistor M5 and a sixth transistor M6 which are operated when the inverted clock CKB is logic low, And a first latch 311 and a second latch 313 for latching the one-node voltage and the second node voltage, respectively.

The first latch 311 and the second latch 313 are connected to each other by using the first node voltage and the second node voltage having complementary values, , The clock is at logic high).

The first latch 311 includes a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9 arranged between the first power supply voltage Vdd and the second power supply voltage Vss, Thereby forming a control inverter (clocked inverter) structure. The seventh transistor M7 is a pull-up transistor that is turned on when the inverted clock signal CKB is at a logic low level. The eighth transistor M8 and the ninth transistor M9 are connected in series, And the interconnect node is connected to the first node n1 to form an inverter.

The second latch 313 includes a tenth transistor M10, an eleventh transistor M11 and a twelfth transistor M12, which are arranged between the first power supply voltage Vdd and the second power supply voltage Vss. Thereby forming a control inverter structure. The tenth transistor M10 is a pull-up transistor that is turned on when the inverted clock CKB is logic low. The eleventh transistor M11 and the twelfth transistor M12 have their gate terminals connected to the first node n1, And the interconnect node is connected to the second node n2 to form an inverter.

In the example of FIG. 3, the first, second, ninth, and twelfth transistors M1, M2, M9, and M12 are implemented as N-MOS transistors, M4, M5, M6, M7, M8, M10, and M11 are implemented as P-MOS transistors.

The second stage 330 includes a thirteenth transistor M13 provided between the first node n1 and the third node n3 and turned on when the inverted clock CKB is logic low, A fourth transistor M14 provided between the third node n3 and the fourth node n4 and turned on when the inverted clock signal CKB is at a logic low level and a fourth transistor M14 provided between the third node n3 and the second power source voltage Vss, A fifteenth transistor M15 and a sixteenth transistor M16 which are pull-down transistors connected to each other and controlled by a fourth node voltage and a second node voltage, respectively, and a fourth node n4 and a second power supply voltage A seventeenth transistor M17 and an eighteenth transistor M18 which are serially connected between the third node voltage Vss and the first node voltage and controlled by the third node voltage and the first node voltage, And a third latch 331 and a fourth latch 333 for latching the voltage and the fourth node voltage, respectively.

In order to operate when the third latch 331 and the fourth latch 333 and the first latch 311 and the second latch 313 are operated in the same manner or when the inverted clock CKB is logic high, Transistor.

The third latch 331 includes a nineteenth transistor M19 and a twentieth transistor M20 constituting the inverter and a twenty-first transistor M21 which is a pull-down transistor turned on when the inverted clock CKB is at a logical high . The gate terminals of the nineteenth transistor M19 and the twentieth transistor M20 are connected to the fourth node n4 and the interconnect node thereof is connected to the third node n3.

The fourth latch 333 includes a twenty-second transistor M22 and a twenty-third transistor M23 which form an inverter and a twenty-fourth transistor M24 which is a pull-down transistor which is turned on when the inverted clock CKB is at a logic high . The gate terminals of the twenty-second transistor M22 and the twenty-third transistor M23 are connected to the third node n3 and the interconnection node thereof is connected to the fourth node n4.

And a fourth inverter (I4) is connected to the fourth node (n4) for inverting the fourth node voltage to finally drive the output (Q). If an inverted output QB is required, another inverter (not shown) for inverting the third node voltage to the third node n3 and finally driving the inverted output QB may be connected.

Hereinafter, the operation of the flip-flop circuit 300 of the present invention will be described with reference to FIGS. 3 and 4. First, the operation of the first stage 310 will be described first. The first stage 310 operates on a logic low interval of the clock CK with respect to the clock CK which makes the logic low and the logic high as one cycle.

<Clock logic low>

The transfer transistor turn-on of the first stage &lt; RTI ID = 0.0 &gt; 310 &lt; / RTI &

The first transistor M1 and the second transistor M2 which are the transfer transistors of the first stage 310 are turned on and the first transistor M1 and the second transistor M2 of the first stage 310 are turned on when the clock CK transits to a logical low and the inverted clock CKB becomes a logic high, The input DD and the inverted input DB are transferred to the first node n1 and the second node n2, respectively. As in the first cycle of FIG. 4, if the input (D) is logic low, the inverting input (DB) and the delay input (DD) are both logic high and logic low.

At this time, since the thirteenth transistor M13 and the fourteenth transistor M14 which are the transfer transistors of the second stage 330 are turned off by the inverted clock CKB, the second stage 330 is in the first stage 310).

Pull-up of the first node and the second node voltage

The first transistor M1 and the second transistor M2 which are the NMOS transistors are turned on to transfer the delay input DD and the inverted input DB to the first node n1 and the second node n2, There can be some problems in the process.

The NMOS transistor has a characteristic to transfer a logic low value sufficiently, while in the case of a logic high, it transfers Vdd-Vtn to a logic high value by a threshold voltage. Here, Vdd is the first power supply voltage, i.e., the operating voltage, and Vtn is the NMOS threshold voltage. Therefore, as the first transistor M1 and the second transistor M2, which are the NMOS transistors, are turned on, the first node n1 is sufficiently discharged to the second power source voltage Vss, while the second node n2 is discharged to the first Vdd -Vtn value. Conversely, when the input D is logic high, the first node n1 has the initial value of Vdd-Vtn and the second node n2 is sufficiently discharged to the second power supply voltage Vss.

To solve this problem, the first stage 310 includes a fourth transistor M4 and a sixth transistor M6, which are pull-up transistors. The fourth transistor M4 or the sixth transistor M6 generates a sufficient logic high by pulling up the first node n1 or the second node n2 charged with Vdd-Vtn to the first power supply voltage Vdd .

On the other hand, when the first node voltage is discharged to the second power supply voltage Vss, the fourth transistor M4 must be completely turned off, and when the second node voltage controlling the fourth transistor M4 is in the initial Vdd-Vtn state The fourth transistor M4 may not be turned off sufficiently so that the discharge path from the first power supply voltage Vdd to the emitter of the second inverter I2 through the first transistor M1 is Can occur. This amounts to unnecessary current consumption, which depends on how fast the second node n2 is pulled up to the first power supply voltage Vdd by the sixth transistor M6. Similarly, when the second node voltage is discharged to the second power supply voltage Vss, the sixth transistor M6 must be completely turned off, and the first node voltage controlling the sixth transistor M6 is in the Vdd-Vtn state The sixth transistor M6 may not be turned off sufficiently until the first power source voltage Vdd is pulled up.

In order to prevent such a problem, the third transistor (M3) and the fifth transistor (M5) controlled by the inverting input (DB) and the delay input (DD) In this way, a first pull-up unit having a third transistor M3 and a fourth transistor M4 is arranged in the first node n1, and a fifth pull-up unit having a fifth transistor M5 and a sixth transistor M5 are provided in the second node n2. And a second pull-up section having a transistor M6 is arranged.

Referring to FIG. 4, after one cycle is started and the clock CK becomes logic low, the first transistor M1 and the second transistor M2 are turned on and the first node n1 and the second node In order to sufficiently transfer the input D to the node n2, only the time of two gate delays (Gate Delay) is sufficient since it passes only I3? M1 / M2. It can be seen that the processing speed is improved by two gate delays compared with the conventional one. Also, since the flip-flop 300 of the present invention uses only one of its internal clocks, the processing speed of the two-gate delay at the first stage 310 is independent of whether the input D is logic low or logic high .

The operation of the first and second latches

The seventh transistor M7 and the tenth transistor M10 are turned off in a period in which the clock CK is logic low or the inversion clock CKB is logic high so that the first latch 311 and the second latch 313 Is not performed. However, the seventh transistor M7 and the tenth transistor M10 are turned off to cut off the discharge path connected from the first power source voltage Vdd to the first node n1 or the second node n2.

Also, as in the first cycle of FIG. 4, when the input D is a logic low and the first node voltage is logic low and the second node voltage is logic high, the ninth transistor M9 is turned on by the second node voltage The first node voltage is turned on to help keep the logic low, and the twelfth transistor M12 is turned off by the first node voltage to discharge the second node voltage to the second power supply voltage Vss .

Conversely, when the input D is logic high such that the first node voltage is logic high and the second node voltage is logic low, the ninth transistor M9 is turned off such that the first node voltage is at the second power supply voltage Vss ), And the twelfth transistor M12 is turned on to help the second node voltage maintain a logic low.

The operation of the second stage

Since the thirteenth transistor M13 and the fourteenth transistor M14 of the second stage 330 are turned off while the inverted clock CKB is logic high, the second stage 330 is in the first stage 310 ) Is not received.

The 21st transistor M21 and the 24th transistor M24 are turned on and the latch operation of the third latch 331 and the fourth latch 333 is performed so that the clock CK of the previous cycle becomes logic high And maintains the data received during the interval. 4, the third node voltage is logic high and the fourth node voltage is logic low, which is the data of the previous cycle.

The twenty-first transistor M21 of the third latch 331 and the twenty-fourth transistor M24 of the fourth latch 333 are turned on because the inverted clock CKB is logic high and the third latch 331 is turned on And maintains the third node voltage (1) while inverting the node voltage (0) to the third node (n3). The fourth latch 333 holds the fourth node voltage 0 while inverting the third node voltage 1 and providing it to the fourth node n4.

<Clock logic high>

The latches of the first and second node voltages

When the clock CK is a logic high or the inverted clock CKB is a logic low, the first transistor M1 and the second transistor M2 which are the transfer transistors of the first stage 310 are turned off, Input (DD) and inverting input (DB) are not received. Instead, the seventh transistor M7 and the tenth transistor M10 are turned on, so that the first latch 311 and the second latch 313 operate to latch the first node voltage and the second node voltage.

If the input D is logic low just before the clock CK is a logic high or the inverted clock CKB is a logic low as in the first cycle of FIG. 4, then the first node voltage is also logic low, The node voltage becomes logic high. Thus, the eighth transistor M8 of the first latch 311 controlled by the second node voltage is turned off and the ninth transistor M9 is turned on, so that the first node n1 keeps the logic low. In addition, the eleventh transistor M11 of the second latch 313 controlled by the first node voltage is turned on and the twelfth transistor M12 is turned off, so that the second node n2 keeps the logic high .

If the input D immediately before the clock CK is logic high or the inverted clock CKB is logic low, then the first node voltage is also logic high and the second node voltage is logic low. The eighth transistor M8 of the first latch 311 controlled by the second node voltage is turned on and the ninth transistor M9 is turned off so that the first node n1 keeps the logic high . In addition, the eleventh transistor M11 of the second latch 313 controlled by the first node voltage is turned off and the twelfth transistor M12 is turned on so that the second node n2 keeps the logic low .

The transfer transistor turn-on of the second stage 330 by the inversion clock

The thirteenth transistor M13 and the fourteenth transistor M14 which are transferring transistors of the second stage 330 are turned on when the clock CK transits to a logical high and the inverted clock CKB becomes a logical low, The one node voltage and the second node voltage are transmitted to the third node n3 and the fourth node n4.

Pull down the third and fourth node voltages

In the process of turning on the first node voltage and the second node voltage to the third node n3 and the fourth node n4, respectively, the thirteenth transistor M13 and the fourteenth transistor M14, which are PMOS transistors, are turned on Some problems may arise.

When the PMOS transistor is turned on, the first power supply voltage Vdd, which is a logic high, is sufficiently transferred. However, the second power supply voltage Vss, which is a logic low, is not sufficiently discharged and is transferred to Vtp. Accordingly, the 13th transistor (M13) and the 14th transistor (M14), which are the PMOS transistors, are turned on, and the third node voltage or the fourth node voltage, which is logic low, is not the second power supply voltage (Vss) Receive. Here, Vtp is the threshold voltage of the thirteenth transistor M13 and the fourteenth transistor M14, which are the PMOS transistors. As shown in the first cycle of FIG. 4, if the input D is logic low, the voltage initially delivered to the third node n3 becomes Vtp. Conversely, if the input D is logic high, the voltage initially transmitted to the fourth node n4 becomes Vtp.

Thus, the second stage 330 includes a first pull down portion for pulling down the third node voltage and a second pull down portion for pulling down the fourth node voltage. The fifteenth and sixteen transistors M15 and M16 are a first pull down portion, and the seventeenth and eighteenth transistors M17 and M18 are a second pull down portion. The first pull-down portion and the second pull-down portion pull down the third node voltage or the fourth node voltage, which becomes logic low, to the second power source voltage Vss.

Final output (Q)

The final output Q is output from the fourth inverter I4 connected to the fourth node n4. Thus, the fourth node voltage is enabled and the output Q is finally output after one gate delay to pass through the fourth inverter I4.

As described above, when a separate inverter (not shown) is arranged in the third node n3, an inverted output QB having no delay can be obtained as compared with the output Q.

4, after the clock CK becomes logic high in one cycle, the thirteenth transistor M13 and the fourteenth transistor M14 are turned on and the third node n3 and the third node n3 are turned on. In order to output the final output (Q) through the fourth node (n4), a three gate delay is sufficient because only I3? M13 / M14? I4 pass. Compared with the conventional one, the processing speed is improved by a two-gate delay. Also, because the flip-flop 300 of the present invention uses only one of its internal clocks, the processing speed of the three-gate delay at the second stage 330 is independent of whether the input D is logic low or logic high .

The operation of the third and fourth latches

The third latch 331 and the fourth latch 333 are turned off because the twenty-first transistor M21 and the twenty-fourth transistor M24 are turned off in a period in which the clock CK is logic high or the inversion clock CKB is logic low. Is not performed. However, since the twenty first transistor M21 and the twenty fourth transistor M24 are turned off, the discharge path to the second power source voltage Vss is cut off.

The thirteenth transistor M13 and the fourteenth transistor M14 are connected in parallel to the first stage 310 and the fourth transistor M14 when the next cycle proceeds and the clock CK becomes logic low again and the inverted clock CKB becomes logic high. Thereby separating the second stage 330. On the other hand, since the twenty first transistor M21 and the twenty fourth transistor M24 are turned on, the third latch 331 and the fourth latch 333 latch the data of the current cycle.

Through the above operation, the flip-flop 300 of the present invention can latch the input D and output the output Q.

<Other Embodiments>

According to another embodiment, the first 310 and second 330 of FIG. 3 may be connected in reverse to FIG. 5, the flip-flop 500 according to another embodiment of the present invention includes a tenth stage 510, which operates when the inverted clock CKB is logic low, and a tenth stage 510 when the inverted clock CKB is logic high And a twentieth stage 530 that operates when the first stage is operated.

In this case, tenth stage 510 receives a delayed input DD and an inverted input DB, respectively, using a pumped transfer transistor to operate at a logic low, and includes a pull down portion instead of a pull up portion do. Thus, the tenth stage 510 here has the same structure as the second stage 330 of FIG. 3, that is, the thirteenth through twenty-fourth transducers M13 through M24 of FIG. 3, ) And an inverting input (DB), respectively.

The twentieth stage 530 receives the first node voltage and the second node voltage, respectively, using a transfer transistor, which is an NMOS transistor, to operate at a logic high, and includes a pull-up portion instead of a pull-down portion. Therefore, the twentieth stage 530 here has the same structure as the first stage 310 of FIG. 3, that is, the first through twelfth transistors M1 through M12 of FIG. 3, Voltage and the second node voltage, respectively. The fourth inverter, which is the output buffer, is connected to the second node n2 of the 20th stage 530 as it is.

The flip-flop of this embodiment is triggered at the negative edge of the clock CK to latch the input D to drive the final output Q.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (14)

A first inverter for outputting an inverted input DB inverted from an input D, a second inverter for outputting a delay input DD which inverts the inverted input again, and a second inverter for inverting the clock CK And a second stage which operates when the inverted clock is logic high and a second stage which is operated when the inverted clock is logic low,
Wherein the first stage comprises: a first transistor and a second transistor for transferring the delayed input and the inverted input to the first node and the second node, respectively, when the inverted clock is logic high; A fourth transistor for pulling up the first node; a sixth transistor for pulling up the second node when the first node voltage is logic low; and a second transistor for pulling up the first node voltage when the inversion clock is logic low. And a second latch that latches a second node voltage when the inverted clock is logic low,
The second stage includes a thirteenth transistor and a fourteenth transistor for transferring the first node voltage and the second node voltage to the third node and the fourth node when the inverted clock is logic low, A seventeenth transistor for pulling down the fourth node when the third node voltage is logic high; and a seventh transistor for pulling down the third node voltage when the inverted clock is logic high A third latch and a fourth latch for latching a fourth node voltage when the inverted clock is logic high.
The method according to claim 1,
When the first transistor and the second transistor are an NMOS transistor,
A third transistor which is provided between the first node and the first power supply voltage (Vdd) together with the fourth transistor and is turned off when the inverting input is a logic high;
And a fifth transistor which is provided between the second node and the first power supply voltage together with the sixth transistor and is turned off when the delay input is logic low.
3. The method according to claim 1 or 2,
When the thirteenth transistor and the fourteenth transistor are a PMOS transistor,
A sixth transistor provided between the third node and the second power supply voltage Vss together with the fifteenth transistor and turned off when the second node voltage is logic low;
And a seventeenth transistor provided between the fourth node and the second power supply voltage together with the seventeenth transistor and turned off when the first node voltage is logic low.
The method according to claim 1,
The first latch includes a seventh transistor, an eighth transistor and a ninth transistor arranged between a first power supply voltage Vdd and a second power supply voltage Vss,
Wherein the seventh transistor is a pull-up transistor that is turned on when the inverted clock is logic low, and wherein the eighth transistor and the ninth transistor are connected such that each gate terminal is connected to the second node, Lt; / RTI &gt;
The second latch includes a tenth transistor, an eleventh transistor and a twelfth transistor arranged between the first power supply voltage and the second power supply voltage,
Wherein the tenth transistor is a pull-up transistor that is turned on when the inverted clock is logic low, and the eleventh transistor and the twelfth transistor have a gate terminal connected to the first node, And the flip-flop circuit is connected to the flip-flop circuit.
The method according to claim 1,
The third latch includes a nineteenth transistor, a twentieth transistor and a twenty-first transistor disposed between a first power supply voltage Vdd and a second power supply voltage Vss,
Each of the nineteenth transistor and the twentieth transistor is connected to the fourth node and the interconnection node thereof is connected to the third node, and the twenty-first transistor is turned on when the inversion clock is logic high Pull-down transistor,
The fourth latch includes a twenty-second transistor, a twenty-third transistor, and a twenty-fourth transistor disposed between the first power supply voltage and the second power supply voltage,
Each of the twenty-second transistor and the twenty-third transistor is connected to the third node, the interconnection node thereof is connected to the fourth node, and the twenty-fourth transistor is turned on when the inversion clock is logic high Wherein the flip-flop circuit is a pull-down transistor.
The method according to claim 1,
And a fourth inverter for inverting the fourth node voltage to drive the final output (Q).
The method according to claim 6,
Further comprising a separate inverter for inverting the third node voltage to drive the inverted output (QB).
A first inverter for outputting an inverted input DB inverted from an input D, a second inverter for outputting a delay input DD which inverts the inverted input again, and a second inverter for inverting the clock CK A tenth stage that operates when the inverted clock is logic low and a twentieth stage that operates when the inverted clock is logic high,
The tenth stage includes a thirteenth transistor and a fourteenth transistor for transferring the delayed input and the inverted input to the third node and the fourth node respectively when the inverted clock is logic low, A seventeenth transistor for pulling down the fourth node when the third node voltage is logic high; a seventeenth transistor for pulling down the third node voltage when the inverted clock is logic high; 3 latch and a fourth latch for latching a fourth node voltage when the inverted clock is logic high,
Wherein the twentieth stage comprises: a first transistor and a second transistor for transferring the third and fourth node voltages to a first node and a second node, respectively, when the inverted clock is logic high; A sixth transistor for pulling up the second node when the first node voltage is logic low; and a sixth transistor for pulling up the first node voltage when the inverted clock is logic low A first latch and a second latch for latching a second node voltage when the inverted clock is logic low.
9. The method of claim 8,
When the thirteenth transistor and the fourteenth transistor are a PMOS transistor,
A sixth transistor, which is provided between the third node and the second power supply voltage (Vss) together with the fifteenth transistor and is turned off when the inverting input is logic low;
And a seventeenth transistor provided between the fourth node and the second power supply voltage together with the seventeenth transistor and turned off when the delay input is logic low.
10. The method according to claim 8 or 9,
When the first transistor and the second transistor are an NMOS transistor,
A third transistor which is provided between the first node and the first power supply voltage Vdd together with the fourth transistor and is turned off when the fourth node voltage is logic high;
And a fifth transistor which is provided between the second node and the first power supply voltage together with the sixth transistor and is turned off when the third node voltage is logic low.
9. The method of claim 8,
The third latch includes a nineteenth transistor, a twentieth transistor and a twenty-first transistor disposed between a first power supply voltage Vdd and a second power supply voltage Vss,
Each of the nineteenth transistor and the twentieth transistor is connected to the fourth node and the interconnection node thereof is connected to the third node, and the twenty-first transistor is turned on when the inversion clock is logic high Pull-down transistor,
The fourth latch includes a twenty-second transistor, a twenty-third transistor, and a twenty-fourth transistor disposed between the first power supply voltage and the second power supply voltage,
Each of the twenty-second transistor and the twenty-third transistor is connected to the third node, the interconnection node thereof is connected to the fourth node, and the twenty-fourth transistor is turned on when the inversion clock is logic high Wherein the flip-flop circuit is a pull-down transistor.
9. The method of claim 8,
The first latch includes a seventh transistor, an eighth transistor and a ninth transistor arranged between a first power supply voltage Vdd and a second power supply voltage Vss,
Wherein the seventh transistor is a pull-up transistor that is turned on when the inverted clock is logic low, and wherein the eighth transistor and the ninth transistor are connected such that each gate terminal is connected to the second node, Lt; / RTI &gt;
The second latch includes a tenth transistor, an eleventh transistor and a twelfth transistor arranged between the first power supply voltage and the second power supply voltage,
Wherein the tenth transistor is a pull-up transistor that is turned on when the inverted clock is logic low, and the eleventh transistor and the twelfth transistor have a gate terminal connected to the first node, And the flip-flop circuit is connected to the flip-flop circuit.
9. The method of claim 8,
And a fourth inverter for inverting the second node voltage to drive the final output (Q).
14. The method of claim 13,
Further comprising a separate inverter for inverting the first node voltage to drive the inverted output (QB).

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